49f795560bd270be91f1cba359330ef88292481e
[rpi-open-firmware.git] / bcm2708_chip / thread_ctrl.h
1 // This file was generated by the create_regs script
2 #define TH_BASE 0x18e00000
3 #define TH_APB_ID 0x74687265
4 #define TH_XCS HW_REGISTER_RW( 0x18e00000 )
5 #define TH_XCS__MASK 0xfffffffc
6 #define TH_XCS__WIDTH 32
7 #define TH_XCS__RESET 0x0155cb00
8 #define TH_XCS_THR_READIES_MSB 31
9 #define TH_XCS_THR_READIES_LSB 28
10 #define TH_XCS_PREV_FIRST_S_MSB 27
11 #define TH_XCS_PREV_FIRST_S_LSB 27
12 #define TH_XCS_MODE_2STAGE_MSB 26
13 #define TH_XCS_MODE_2STAGE_LSB 26
14 #define TH_XCS_FLUSH_2STAGE_MSB 25
15 #define TH_XCS_FLUSH_2STAGE_LSB 25
16 #define TH_XCS_STARTUP_MSB 24
17 #define TH_XCS_STARTUP_LSB 24
18 #define TH_XCS_THR_STATE3_MSB 23
19 #define TH_XCS_THR_STATE3_LSB 22
20 #define TH_XCS_THR_STATE2_MSB 21
21 #define TH_XCS_THR_STATE2_LSB 20
22 #define TH_XCS_THR_STATE1_MSB 19
23 #define TH_XCS_THR_STATE1_LSB 18
24 #define TH_XCS_THR_STATE0_MSB 17
25 #define TH_XCS_THR_STATE0_LSB 16
26 #define TH_XCS_SYS_STATE_MSB 15
27 #define TH_XCS_SYS_STATE_LSB 14
28 #define TH_XCS_NEXT_READY_MSB 13
29 #define TH_XCS_NEXT_READY_LSB 12
30 #define TH_XCS_PREV_SYS_MSB 11
31 #define TH_XCS_PREV_SYS_LSB 11
32 #define TH_XCS_PREV_IDLE_MSB 10
33 #define TH_XCS_PREV_IDLE_LSB 10
34 #define TH_XCS_PREV_THREAD_MSB 9
35 #define TH_XCS_PREV_THREAD_LSB 8
36 #define TH_XCS_THREAD_HWEN_MSB 7
37 #define TH_XCS_THREAD_HWEN_LSB 4
38 #define TH_XCS_THREAD_SYSFL_MSB 3
39 #define TH_XCS_THREAD_SYSFL_LSB 3
40 #define TH_XCS_THREAD_SYSIN_MSB 2
41 #define TH_XCS_THREAD_SYSIN_LSB 2
42 #define TH_XCFG HW_REGISTER_RW( 0x18e00004 )
43 #define TH_XCFG__MASK 0xffffffff
44 #define TH_XCFG__WIDTH 32
45 #define TH_XCFG__RESET 0000000000
46 #define TH_XCFG_SW_ENS_MSB 11
47 #define TH_XCFG_SW_ENS_LSB 8
48 #define TH_XCFG_SW_SYSFLUSH_MSB 7
49 #define TH_XCFG_SW_SYSFLUSH_LSB 7
50 #define TH_XCFG_SW_SYSINTR_MSB 6
51 #define TH_XCFG_SW_SYSINTR_LSB 6
52 #define TH_XCFG_SW_EN_SEL_MSB 4
53 #define TH_XCFG_SW_EN_SEL_LSB 4
54 #define TH_XCFG_SW_FLUSH_SEL_MSB 3
55 #define TH_XCFG_SW_FLUSH_SEL_LSB 3
56 #define TH_XCFG_SW_INTR_SEL_MSB 2
57 #define TH_XCFG_SW_INTR_SEL_LSB 2
58 #define TH_XCFG_THR_EN_MSB 0
59 #define TH_XCFG_THR_EN_LSB 0
60 #define TH_XSTPC HW_REGISTER_RW( 0x18e00008 )
61 #define TH_XSTPC__MASK 0xfffffffe
62 #define TH_XSTPC__WIDTH 32
63 #define TH_XSTPC__RESET 0000000000
64 #define TH_XSTPC__MSB 31
65 #define TH_XSTPC__LSB 1
66 #define TH_XITPC HW_REGISTER_RW( 0x18e0000c )
67 #define TH_XITPC__MASK 0xfffffffe
68 #define TH_XITPC__WIDTH 32
69 #define TH_XITPC__RESET 0000000000
70 #define TH_XITPC__MSB 31
71 #define TH_XITPC__LSB 1
72 #define TH_XT0PC HW_REGISTER_RW( 0x18e00010 )
73 #define TH_XT0PC__MASK 0xfffffffe
74 #define TH_XT0PC__WIDTH 32
75 #define TH_XT0PC__RESET 0000000000
76 #define TH_XT0PC__MSB 31
77 #define TH_XT0PC__LSB 1
78 #define TH_XT0UD HW_REGISTER_RW( 0x18e00014 )
79 #define TH_XT0UD__MASK 0xffffffff
80 #define TH_XT0UD__WIDTH 32
81 #define TH_XT0UD__RESET 0000000000
82 #define TH_XT0UD__MSB 31
83 #define TH_XT0UD__LSB 0
84 #define TH_XT1PC HW_REGISTER_RW( 0x18e00018 )
85 #define TH_XT1PC__MASK 0xfffffffe
86 #define TH_XT1PC__WIDTH 32
87 #define TH_XT1PC__RESET 0000000000
88 #define TH_XT1PC__MSB 31
89 #define TH_XT1PC__LSB 1
90 #define TH_XT1UD HW_REGISTER_RW( 0x18e0001c )
91 #define TH_XT1UD__MASK 0xffffffff
92 #define TH_XT1UD__WIDTH 32
93 #define TH_XT1UD__RESET 0000000000
94 #define TH_XT1UD__MSB 31
95 #define TH_XT1UD__LSB 0
96 #define TH_XT2PC HW_REGISTER_RW( 0x18e00020 )
97 #define TH_XT2PC__MASK 0xfffffffe
98 #define TH_XT2PC__WIDTH 32
99 #define TH_XT2PC__RESET 0000000000
100 #define TH_XT2PC__MSB 31
101 #define TH_XT2PC__LSB 1
102 #define TH_XT2UD HW_REGISTER_RW( 0x18e00024 )
103 #define TH_XT2UD__MASK 0xffffffff
104 #define TH_XT2UD__WIDTH 32
105 #define TH_XT2UD__RESET 0000000000
106 #define TH_XT2UD__MSB 31
107 #define TH_XT2UD__LSB 0
108 #define TH_XT3PC HW_REGISTER_RW( 0x18e00028 )
109 #define TH_XT3PC__MASK 0xfffffffe
110 #define TH_XT3PC__WIDTH 32
111 #define TH_XT3PC__RESET 0000000000
112 #define TH_XT3PC__MSB 31
113 #define TH_XT3PC__LSB 1
114 #define TH_XT3UD HW_REGISTER_RW( 0x18e0002c )
115 #define TH_XT3UD__MASK 0xffffffff
116 #define TH_XT3UD__WIDTH 32
117 #define TH_XT3UD__RESET 0000000000
118 #define TH_XT3UD__MSB 31
119 #define TH_XT3UD__LSB 0
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