0bedda4df461d7170c91c93634d5d84227ec6f5b
[rpi-open-firmware.git] / bcm2708_chip / txp.h
1 // This file was generated by the create_regs script
2 #define TXP_BASE 0x7e004000
3 #define TXP_APB_ID 0x20763374
4 #define TXP_DST_PTR HW_REGISTER_RW( 0x7e004000 )
5 #define TXP_DST_PTR_MASK 0xfffffffe
6 #define TXP_DST_PTR_WIDTH 32
7 #define TXP_DST_PITCH HW_REGISTER_RW( 0x7e004004 )
8 #define TXP_DST_PITCH_MASK 0xfffffff0
9 #define TXP_DST_PITCH_WIDTH 32
10 #define TXP_DIM HW_REGISTER_RW( 0x7e004008 )
11 #define TXP_DIM_MASK 0x0fff0fff
12 #define TXP_DIM_WIDTH 28
13 #define TXP_DIM_HEIGHT_BITS 27:16
14 #define TXP_DIM_HEIGHT_SET 0x0fff0000
15 #define TXP_DIM_HEIGHT_CLR 0xf000ffff
16 #define TXP_DIM_HEIGHT_MSB 27
17 #define TXP_DIM_HEIGHT_LSB 16
18 #define TXP_DIM_HEIGHT_RESET 0x0
19 #define TXP_DIM_WIDTH_BITS 11:0
20 #define TXP_DIM_WIDTH_SET 0x00000fff
21 #define TXP_DIM_WIDTH_CLR 0xfffff000
22 #define TXP_DIM_WIDTH_MSB 11
23 #define TXP_DIM_WIDTH_LSB 0
24 #define TXP_DIM_WIDTH_RESET 0x0
25 #define TXP_CTRL HW_REGISTER_RW( 0x7e00400c )
26 #define TXP_CTRL_MASK 0xffffffff
27 #define TXP_CTRL_WIDTH 32
28 #define TXP_CTRL_PILOT_BITS 31:24
29 #define TXP_CTRL_PILOT_SET 0xff000000
30 #define TXP_CTRL_PILOT_CLR 0x00ffffff
31 #define TXP_CTRL_PILOT_MSB 31
32 #define TXP_CTRL_PILOT_LSB 24
33 #define TXP_CTRL_PILOT_RESET 0x54
34 #define TXP_CTRL_VERSION_BITS 23:22
35 #define TXP_CTRL_VERSION_SET 0x00c00000
36 #define TXP_CTRL_VERSION_CLR 0xff3fffff
37 #define TXP_CTRL_VERSION_MSB 23
38 #define TXP_CTRL_VERSION_LSB 22
39 #define TXP_CTRL_VERSION_RESET 0x1
40 #define TXP_CTRL_POWERDOWN_BITS 21:21
41 #define TXP_CTRL_POWERDOWN_SET 0x00200000
42 #define TXP_CTRL_POWERDOWN_CLR 0xffdfffff
43 #define TXP_CTRL_POWERDOWN_MSB 21
44 #define TXP_CTRL_POWERDOWN_LSB 21
45 #define TXP_CTRL_POWERDOWN_RESET 0x0
46 #define TXP_CTRL_ALPHA_ENABLE_BITS 20:20
47 #define TXP_CTRL_ALPHA_ENABLE_SET 0x00100000
48 #define TXP_CTRL_ALPHA_ENABLE_CLR 0xffefffff
49 #define TXP_CTRL_ALPHA_ENABLE_MSB 20
50 #define TXP_CTRL_ALPHA_ENABLE_LSB 20
51 #define TXP_CTRL_BWE_BITS 19:16
52 #define TXP_CTRL_BWE_SET 0x000f0000
53 #define TXP_CTRL_BWE_CLR 0xfff0ffff
54 #define TXP_CTRL_BWE_MSB 19
55 #define TXP_CTRL_BWE_LSB 16
56 #define TXP_CTRL_BWE_RESET 0xf
57 #define TXP_CTRL_VSTART_AT_EOF_BITS 15:15
58 #define TXP_CTRL_VSTART_AT_EOF_SET 0x00008000
59 #define TXP_CTRL_VSTART_AT_EOF_CLR 0xffff7fff
60 #define TXP_CTRL_VSTART_AT_EOF_MSB 15
61 #define TXP_CTRL_VSTART_AT_EOF_LSB 15
62 #define TXP_CTRL_ABORT_BITS 14:14
63 #define TXP_CTRL_ABORT_SET 0x00004000
64 #define TXP_CTRL_ABORT_CLR 0xffffbfff
65 #define TXP_CTRL_ABORT_MSB 14
66 #define TXP_CTRL_ABORT_LSB 14
67 #define TXP_CTRL_DITHER_BITS 13:13
68 #define TXP_CTRL_DITHER_SET 0x00002000
69 #define TXP_CTRL_DITHER_CLR 0xffffdfff
70 #define TXP_CTRL_DITHER_MSB 13
71 #define TXP_CTRL_DITHER_LSB 13
72 #define TXP_CTRL_ALPHA_INVERT_BITS 12:12
73 #define TXP_CTRL_ALPHA_INVERT_SET 0x00001000
74 #define TXP_CTRL_ALPHA_INVERT_CLR 0xffffefff
75 #define TXP_CTRL_ALPHA_INVERT_MSB 12
76 #define TXP_CTRL_ALPHA_INVERT_LSB 12
77 #define TXP_CTRL_FORMAT_BITS 11:8
78 #define TXP_CTRL_FORMAT_SET 0x00000f00
79 #define TXP_CTRL_FORMAT_CLR 0xfffff0ff
80 #define TXP_CTRL_FORMAT_MSB 11
81 #define TXP_CTRL_FORMAT_LSB 8
82 #define TXP_CTRL_LINEAR_UTILE_BITS 7:7
83 #define TXP_CTRL_LINEAR_UTILE_SET 0x00000080
84 #define TXP_CTRL_LINEAR_UTILE_CLR 0xffffff7f
85 #define TXP_CTRL_LINEAR_UTILE_MSB 7
86 #define TXP_CTRL_LINEAR_UTILE_LSB 7
87 #define TXP_CTRL_TRANSPOSE_BITS 6:6
88 #define TXP_CTRL_TRANSPOSE_SET 0x00000040
89 #define TXP_CTRL_TRANSPOSE_CLR 0xffffffbf
90 #define TXP_CTRL_TRANSPOSE_MSB 6
91 #define TXP_CTRL_TRANSPOSE_LSB 6
92 #define TXP_CTRL_TFORMAT_BITS 5:5
93 #define TXP_CTRL_TFORMAT_SET 0x00000020
94 #define TXP_CTRL_TFORMAT_CLR 0xffffffdf
95 #define TXP_CTRL_TFORMAT_MSB 5
96 #define TXP_CTRL_TFORMAT_LSB 5
97 #define TXP_CTRL_TEST_MODE_BITS 4:4
98 #define TXP_CTRL_TEST_MODE_SET 0x00000010
99 #define TXP_CTRL_TEST_MODE_CLR 0xffffffef
100 #define TXP_CTRL_TEST_MODE_MSB 4
101 #define TXP_CTRL_TEST_MODE_LSB 4
102 #define TXP_CTRL_FIELD_BITS 3:3
103 #define TXP_CTRL_FIELD_SET 0x00000008
104 #define TXP_CTRL_FIELD_CLR 0xfffffff7
105 #define TXP_CTRL_FIELD_MSB 3
106 #define TXP_CTRL_FIELD_LSB 3
107 #define TXP_CTRL_EI_BITS 2:2
108 #define TXP_CTRL_EI_SET 0x00000004
109 #define TXP_CTRL_EI_CLR 0xfffffffb
110 #define TXP_CTRL_EI_MSB 2
111 #define TXP_CTRL_EI_LSB 2
112 #define TXP_CTRL_BUSY_BITS 1:1
113 #define TXP_CTRL_BUSY_SET 0x00000002
114 #define TXP_CTRL_BUSY_CLR 0xfffffffd
115 #define TXP_CTRL_BUSY_MSB 1
116 #define TXP_CTRL_BUSY_LSB 1
117 #define TXP_CTRL_GO_BITS 0:0
118 #define TXP_CTRL_GO_SET 0x00000001
119 #define TXP_CTRL_GO_CLR 0xfffffffe
120 #define TXP_CTRL_GO_MSB 0
121 #define TXP_CTRL_GO_LSB 0
122 #define TXP_PROGRESS HW_REGISTER_RO( 0x7e004010 )
123 #define TXP_PROGRESS_MASK 0x00000fff
124 #define TXP_PROGRESS_WIDTH 12
125 #define TXP_PROGRESS_LINES_BITS 11:0
126 #define TXP_PROGRESS_LINES_SET 0x00000fff
127 #define TXP_PROGRESS_LINES_CLR 0xfffff000
128 #define TXP_PROGRESS_LINES_MSB 11
129 #define TXP_PROGRESS_LINES_LSB 0
130 #define TXP_XTRA HW_REGISTER_RW( 0x7e004018 )
131 #define TXP_XTRA_MASK 0x00000001
132 #define TXP_XTRA_WIDTH 1
133 #define TXP_XTRA_NOSTBY_BITS 0:0
134 #define TXP_XTRA_NOSTBY_SET 0x00000001
135 #define TXP_XTRA_NOSTBY_CLR 0xfffffffe
136 #define TXP_XTRA_NOSTBY_MSB 0
137 #define TXP_XTRA_NOSTBY_LSB 0
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