Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / uart.h
1 // This file was generated by the create_regs script
2 #define UART_BASE 0x7e201000
3 #define UART_RBRTHRDLL HW_REGISTER_RW( 0x7e201000 )
4 #define UART_IERDLM HW_REGISTER_RW( 0x7e201004 )
5 #define UART_IIR_FCR HW_REGISTER_RW( 0x7e201008 )
6 #define UART_LCR HW_REGISTER_RW( 0x7e20100c )
7 #define UART_LCR_MASK 0x000000ff
8 #define UART_LCR_WIDTH 8
9 #define UART_LCR_RESET 0000000000
10 #define UART_LCR_DLAB_BITS 7:7
11 #define UART_LCR_DLAB_SET 0x00000080
12 #define UART_LCR_DLAB_CLR 0xffffff7f
13 #define UART_LCR_DLAB_MSB 7
14 #define UART_LCR_DLAB_LSB 7
15 #define UART_LCR_SBC_BITS 6:6
16 #define UART_LCR_SBC_SET 0x00000040
17 #define UART_LCR_SBC_CLR 0xffffffbf
18 #define UART_LCR_SBC_MSB 6
19 #define UART_LCR_SBC_LSB 6
20 #define UART_LCR_SP_BITS 5:5
21 #define UART_LCR_SP_SET 0x00000020
22 #define UART_LCR_SP_CLR 0xffffffdf
23 #define UART_LCR_SP_MSB 5
24 #define UART_LCR_SP_LSB 5
25 #define UART_LCR_EPS_BITS 4:4
26 #define UART_LCR_EPS_SET 0x00000010
27 #define UART_LCR_EPS_CLR 0xffffffef
28 #define UART_LCR_EPS_MSB 4
29 #define UART_LCR_EPS_LSB 4
30 #define UART_LCR_PEN_BITS 3:3
31 #define UART_LCR_PEN_SET 0x00000008
32 #define UART_LCR_PEN_CLR 0xfffffff7
33 #define UART_LCR_PEN_MSB 3
34 #define UART_LCR_PEN_LSB 3
35 #define UART_LCR_STB_BITS 2:2
36 #define UART_LCR_STB_SET 0x00000004
37 #define UART_LCR_STB_CLR 0xfffffffb
38 #define UART_LCR_STB_MSB 2
39 #define UART_LCR_STB_LSB 2
40 #define UART_LCR_WLS_BITS 1:0
41 #define UART_LCR_WLS_SET 0x00000003
42 #define UART_LCR_WLS_CLR 0xfffffffc
43 #define UART_LCR_WLS_MSB 1
44 #define UART_LCR_WLS_LSB 0
45 #define UART_LCR_LOOP_BITS 4:4
46 #define UART_LCR_LOOP_SET 0x00000010
47 #define UART_LCR_LOOP_CLR 0xffffffef
48 #define UART_LCR_LOOP_MSB 4
49 #define UART_LCR_LOOP_LSB 4
50 #define UART_LCR_OUT2_BITS 3:3
51 #define UART_LCR_OUT2_SET 0x00000008
52 #define UART_LCR_OUT2_CLR 0xfffffff7
53 #define UART_LCR_OUT2_MSB 3
54 #define UART_LCR_OUT2_LSB 3
55 #define UART_LCR_OUT1_BITS 2:2
56 #define UART_LCR_OUT1_SET 0x00000004
57 #define UART_LCR_OUT1_CLR 0xfffffffb
58 #define UART_LCR_OUT1_MSB 2
59 #define UART_LCR_OUT1_LSB 2
60 #define UART_LCR_RTS_BITS 1:1
61 #define UART_LCR_RTS_SET 0x00000002
62 #define UART_LCR_RTS_CLR 0xfffffffd
63 #define UART_LCR_RTS_MSB 1
64 #define UART_LCR_RTS_LSB 1
65 #define UART_LCR_DTR_BITS 0:0
66 #define UART_LCR_DTR_SET 0x00000001
67 #define UART_LCR_DTR_CLR 0xfffffffe
68 #define UART_LCR_DTR_MSB 0
69 #define UART_LCR_DTR_LSB 0
70 #define UART_MCR HW_REGISTER_RW( 0x7e201010 )
71 #define UART_MCR_MASK 0x0000001f
72 #define UART_MCR_WIDTH 5
73 #define UART_MCR_RESET 0000000000
74 #define UART_LSR HW_REGISTER_RW( 0x7e201014 )
75 #define UART_LSR_MASK 0x000000ff
76 #define UART_LSR_WIDTH 8
77 #define UART_LSR_RESET 0000000000
78 #define UART_LSR_RFE_BITS 7:7
79 #define UART_LSR_RFE_SET 0x00000080
80 #define UART_LSR_RFE_CLR 0xffffff7f
81 #define UART_LSR_RFE_MSB 7
82 #define UART_LSR_RFE_LSB 7
83 #define UART_LSR_TEMT_BITS 6:6
84 #define UART_LSR_TEMT_SET 0x00000040
85 #define UART_LSR_TEMT_CLR 0xffffffbf
86 #define UART_LSR_TEMT_MSB 6
87 #define UART_LSR_TEMT_LSB 6
88 #define UART_LSR_THRE_BITS 5:5
89 #define UART_LSR_THRE_SET 0x00000020
90 #define UART_LSR_THRE_CLR 0xffffffdf
91 #define UART_LSR_THRE_MSB 5
92 #define UART_LSR_THRE_LSB 5
93 #define UART_LSR_BI_BITS 4:4
94 #define UART_LSR_BI_SET 0x00000010
95 #define UART_LSR_BI_CLR 0xffffffef
96 #define UART_LSR_BI_MSB 4
97 #define UART_LSR_BI_LSB 4
98 #define UART_LSR_FE_BITS 3:3
99 #define UART_LSR_FE_SET 0x00000008
100 #define UART_LSR_FE_CLR 0xfffffff7
101 #define UART_LSR_FE_MSB 3
102 #define UART_LSR_FE_LSB 3
103 #define UART_LSR_PE_BITS 2:2
104 #define UART_LSR_PE_SET 0x00000004
105 #define UART_LSR_PE_CLR 0xfffffffb
106 #define UART_LSR_PE_MSB 2
107 #define UART_LSR_PE_LSB 2
108 #define UART_LSR_OE_BITS 1:1
109 #define UART_LSR_OE_SET 0x00000002
110 #define UART_LSR_OE_CLR 0xfffffffd
111 #define UART_LSR_OE_MSB 1
112 #define UART_LSR_OE_LSB 1
113 #define UART_LSR_DR_BITS 0:0
114 #define UART_LSR_DR_SET 0x00000001
115 #define UART_LSR_DR_CLR 0xfffffffe
116 #define UART_LSR_DR_MSB 0
117 #define UART_LSR_DR_LSB 0
118 #define UART_MSR HW_REGISTER_RW( 0x7e201018 )
119 #define UART_MSR_MASK 0x000000ff
120 #define UART_MSR_WIDTH 8
121 #define UART_MSR_RESET 0000000000
122 #define UART_MSR_DCD_BITS 7:7
123 #define UART_MSR_DCD_SET 0x00000080
124 #define UART_MSR_DCD_CLR 0xffffff7f
125 #define UART_MSR_DCD_MSB 7
126 #define UART_MSR_DCD_LSB 7
127 #define UART_MSR_RI_BITS 6:6
128 #define UART_MSR_RI_SET 0x00000040
129 #define UART_MSR_RI_CLR 0xffffffbf
130 #define UART_MSR_RI_MSB 6
131 #define UART_MSR_RI_LSB 6
132 #define UART_MSR_DSR_BITS 5:5
133 #define UART_MSR_DSR_SET 0x00000020
134 #define UART_MSR_DSR_CLR 0xffffffdf
135 #define UART_MSR_DSR_MSB 5
136 #define UART_MSR_DSR_LSB 5
137 #define UART_MSR_CTS_BITS 4:4
138 #define UART_MSR_CTS_SET 0x00000010
139 #define UART_MSR_CTS_CLR 0xffffffef
140 #define UART_MSR_CTS_MSB 4
141 #define UART_MSR_CTS_LSB 4
142 #define UART_MSR_DDCD_BITS 3:3
143 #define UART_MSR_DDCD_SET 0x00000008
144 #define UART_MSR_DDCD_CLR 0xfffffff7
145 #define UART_MSR_DDCD_MSB 3
146 #define UART_MSR_DDCD_LSB 3
147 #define UART_MSR_TERI_BITS 2:2
148 #define UART_MSR_TERI_SET 0x00000004
149 #define UART_MSR_TERI_CLR 0xfffffffb
150 #define UART_MSR_TERI_MSB 2
151 #define UART_MSR_TERI_LSB 2
152 #define UART_MSR_DDSR_BITS 1:1
153 #define UART_MSR_DDSR_SET 0x00000002
154 #define UART_MSR_DDSR_CLR 0xfffffffd
155 #define UART_MSR_DDSR_MSB 1
156 #define UART_MSR_DDSR_LSB 1
157 #define UART_MSR_DCTS_BITS 0:0
158 #define UART_MSR_DCTS_SET 0x00000001
159 #define UART_MSR_DCTS_CLR 0xfffffffe
160 #define UART_MSR_DCTS_MSB 0
161 #define UART_MSR_DCTS_LSB 0
162 #define UART_SCR HW_REGISTER_RW( 0x7e20101c )
163 #define UART_SCR_MASK 0x000000ff
164 #define UART_SCR_WIDTH 8
165 #define UART_SCR_RESET 0000000000
166 #define UART_EN HW_REGISTER_RW( 0x7e201020 )
167 #define UART_EN_MASK 0x00000002
168 #define UART_EN_WIDTH 2
169 #define UART_EN_RESET 0000000000
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