Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / usb.h
1 // This file was generated by the create_regs script
2 #define USB_BASE 0x7e980000
3 #define USB_APB_ID 0x75736230
4 #define USB_GOTGCTL HW_REGISTER_RW( 0x7e980000 )
5 #define USB_GOTGCTL_MASK 0x000f0f03
6 #define USB_GOTGCTL_WIDTH 20
7 #define USB_GOTGCTL_B_SES_VLD_BITS 19:19
8 #define USB_GOTGCTL_B_SES_VLD_SET 0x00080000
9 #define USB_GOTGCTL_B_SES_VLD_CLR 0xfff7ffff
10 #define USB_GOTGCTL_B_SES_VLD_MSB 19
11 #define USB_GOTGCTL_B_SES_VLD_LSB 19
12 #define USB_GOTGCTL_B_SES_VLD_RESET 0x0
13 #define USB_GOTGCTL_A_SES_VLD_BITS 18:18
14 #define USB_GOTGCTL_A_SES_VLD_SET 0x00040000
15 #define USB_GOTGCTL_A_SES_VLD_CLR 0xfffbffff
16 #define USB_GOTGCTL_A_SES_VLD_MSB 18
17 #define USB_GOTGCTL_A_SES_VLD_LSB 18
18 #define USB_GOTGCTL_A_SES_VLD_RESET 0x0
19 #define USB_GOTGCTL_DBNC_TIME_BITS 17:17
20 #define USB_GOTGCTL_DBNC_TIME_SET 0x00020000
21 #define USB_GOTGCTL_DBNC_TIME_CLR 0xfffdffff
22 #define USB_GOTGCTL_DBNC_TIME_MSB 17
23 #define USB_GOTGCTL_DBNC_TIME_LSB 17
24 #define USB_GOTGCTL_DBNC_TIME_RESET 0x0
25 #define USB_GOTGCTL_CON_ID_STS_BITS 16:16
26 #define USB_GOTGCTL_CON_ID_STS_SET 0x00010000
27 #define USB_GOTGCTL_CON_ID_STS_CLR 0xfffeffff
28 #define USB_GOTGCTL_CON_ID_STS_MSB 16
29 #define USB_GOTGCTL_CON_ID_STS_LSB 16
30 #define USB_GOTGCTL_CON_ID_STS_RESET 0x0
31 #define USB_GOTGCTL_DEV_HNP_EN_BITS 11:11
32 #define USB_GOTGCTL_DEV_HNP_EN_SET 0x00000800
33 #define USB_GOTGCTL_DEV_HNP_EN_CLR 0xfffff7ff
34 #define USB_GOTGCTL_DEV_HNP_EN_MSB 11
35 #define USB_GOTGCTL_DEV_HNP_EN_LSB 11
36 #define USB_GOTGCTL_DEV_HNP_EN_RESET 0x0
37 #define USB_GOTGCTL_HST_SET_HNP_EN_BITS 10:10
38 #define USB_GOTGCTL_HST_SET_HNP_EN_SET 0x00000400
39 #define USB_GOTGCTL_HST_SET_HNP_EN_CLR 0xfffffbff
40 #define USB_GOTGCTL_HST_SET_HNP_EN_MSB 10
41 #define USB_GOTGCTL_HST_SET_HNP_EN_LSB 10
42 #define USB_GOTGCTL_HST_SET_HNP_EN_RESET 0x0
43 #define USB_GOTGCTL_HNP_REQ_BITS 9:9
44 #define USB_GOTGCTL_HNP_REQ_SET 0x00000200
45 #define USB_GOTGCTL_HNP_REQ_CLR 0xfffffdff
46 #define USB_GOTGCTL_HNP_REQ_MSB 9
47 #define USB_GOTGCTL_HNP_REQ_LSB 9
48 #define USB_GOTGCTL_HNP_REQ_RESET 0x0
49 #define USB_GOTGCTL_HST_NEG_SCS_BITS 8:8
50 #define USB_GOTGCTL_HST_NEG_SCS_SET 0x00000100
51 #define USB_GOTGCTL_HST_NEG_SCS_CLR 0xfffffeff
52 #define USB_GOTGCTL_HST_NEG_SCS_MSB 8
53 #define USB_GOTGCTL_HST_NEG_SCS_LSB 8
54 #define USB_GOTGCTL_HST_NEG_SCS_RESET 0x0
55 #define USB_GOTGCTL_SES_REQ_BITS 1:1
56 #define USB_GOTGCTL_SES_REQ_SET 0x00000002
57 #define USB_GOTGCTL_SES_REQ_CLR 0xfffffffd
58 #define USB_GOTGCTL_SES_REQ_MSB 1
59 #define USB_GOTGCTL_SES_REQ_LSB 1
60 #define USB_GOTGCTL_SES_REQ_RESET 0x0
61 #define USB_GOTGCTL_SES_REQ_SCS_BITS 0:0
62 #define USB_GOTGCTL_SES_REQ_SCS_SET 0x00000001
63 #define USB_GOTGCTL_SES_REQ_SCS_CLR 0xfffffffe
64 #define USB_GOTGCTL_SES_REQ_SCS_MSB 0
65 #define USB_GOTGCTL_SES_REQ_SCS_LSB 0
66 #define USB_GOTGCTL_SES_REQ_SCS_RESET 0x0
67 #define USB_GOTGINT HW_REGISTER_RW( 0x7e980004 )
68 #define USB_GOTGINT_MASK 0x000e0304
69 #define USB_GOTGINT_WIDTH 20
70 #define USB_GOTGINT_DBNCE_DONE_BITS 19:19
71 #define USB_GOTGINT_DBNCE_DONE_SET 0x00080000
72 #define USB_GOTGINT_DBNCE_DONE_CLR 0xfff7ffff
73 #define USB_GOTGINT_DBNCE_DONE_MSB 19
74 #define USB_GOTGINT_DBNCE_DONE_LSB 19
75 #define USB_GOTGINT_DBNCE_DONE_RESET 0x0
76 #define USB_GOTGINT_A_DEV_TOUT_CHG_BITS 18:18
77 #define USB_GOTGINT_A_DEV_TOUT_CHG_SET 0x00040000
78 #define USB_GOTGINT_A_DEV_TOUT_CHG_CLR 0xfffbffff
79 #define USB_GOTGINT_A_DEV_TOUT_CHG_MSB 18
80 #define USB_GOTGINT_A_DEV_TOUT_CHG_LSB 18
81 #define USB_GOTGINT_A_DEV_TOUT_CHG_RESET 0x0
82 #define USB_GOTGINT_HST_NEG_DET_BITS 17:17
83 #define USB_GOTGINT_HST_NEG_DET_SET 0x00020000
84 #define USB_GOTGINT_HST_NEG_DET_CLR 0xfffdffff
85 #define USB_GOTGINT_HST_NEG_DET_MSB 17
86 #define USB_GOTGINT_HST_NEG_DET_LSB 17
87 #define USB_GOTGINT_HST_NEG_DET_RESET 0x0
88 #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_BITS 9:9
89 #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_SET 0x00000200
90 #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_CLR 0xfffffdff
91 #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_MSB 9
92 #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_LSB 9
93 #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_RESET 0x0
94 #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_BITS 8:8
95 #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_SET 0x00000100
96 #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_CLR 0xfffffeff
97 #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_MSB 8
98 #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_LSB 8
99 #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_RESET 0x0
100 #define USB_GOTGINT_SES_END_DET_BITS 2:2
101 #define USB_GOTGINT_SES_END_DET_SET 0x00000004
102 #define USB_GOTGINT_SES_END_DET_CLR 0xfffffffb
103 #define USB_GOTGINT_SES_END_DET_MSB 2
104 #define USB_GOTGINT_SES_END_DET_LSB 2
105 #define USB_GOTGINT_SES_END_DET_RESET 0x0
106 #define USB_GAHBCFG HW_REGISTER_RW( 0x7e980008 )
107 #define USB_GAHBCFG_MASK 0x000001bf
108 #define USB_GAHBCFG_WIDTH 9
109 #define USB_GAHBCFG_P_TXF_EMP_LVL_BITS 8:8
110 #define USB_GAHBCFG_P_TXF_EMP_LVL_SET 0x00000100
111 #define USB_GAHBCFG_P_TXF_EMP_LVL_CLR 0xfffffeff
112 #define USB_GAHBCFG_P_TXF_EMP_LVL_MSB 8
113 #define USB_GAHBCFG_P_TXF_EMP_LVL_LSB 8
114 #define USB_GAHBCFG_P_TXF_EMP_LVL_RESET 0x0
115 #define USB_GAHBCFG_NP_TXF_EMP_LVL_BITS 7:7
116 #define USB_GAHBCFG_NP_TXF_EMP_LVL_SET 0x00000080
117 #define USB_GAHBCFG_NP_TXF_EMP_LVL_CLR 0xffffff7f
118 #define USB_GAHBCFG_NP_TXF_EMP_LVL_MSB 7
119 #define USB_GAHBCFG_NP_TXF_EMP_LVL_LSB 7
120 #define USB_GAHBCFG_NP_TXF_EMP_LVL_RESET 0x0
121 #define USB_GAHBCFG_DMA_EN_BITS 5:5
122 #define USB_GAHBCFG_DMA_EN_SET 0x00000020
123 #define USB_GAHBCFG_DMA_EN_CLR 0xffffffdf
124 #define USB_GAHBCFG_DMA_EN_MSB 5
125 #define USB_GAHBCFG_DMA_EN_LSB 5
126 #define USB_GAHBCFG_DMA_EN_RESET 0x0
127 #define USB_GAHBCFG_H_BST_LEN_BITS 4:1
128 #define USB_GAHBCFG_H_BST_LEN_SET 0x0000001e
129 #define USB_GAHBCFG_H_BST_LEN_CLR 0xffffffe1
130 #define USB_GAHBCFG_H_BST_LEN_MSB 4
131 #define USB_GAHBCFG_H_BST_LEN_LSB 1
132 #define USB_GAHBCFG_H_BST_LEN_RESET 0x0
133 #define USB_GAHBCFG_GLBL_INTR_MSK_BITS 0:0
134 #define USB_GAHBCFG_GLBL_INTR_MSK_SET 0x00000001
135 #define USB_GAHBCFG_GLBL_INTR_MSK_CLR 0xfffffffe
136 #define USB_GAHBCFG_GLBL_INTR_MSK_MSB 0
137 #define USB_GAHBCFG_GLBL_INTR_MSK_LSB 0
138 #define USB_GAHBCFG_GLBL_INTR_MSK_RESET 0x0
139 #define USB_GUSBCFG HW_REGISTER_RW( 0x7e98000c )
140 #define USB_GUSBCFG_MASK 0xe3ffbfff
141 #define USB_GUSBCFG_WIDTH 32
142 #define USB_GUSBCFG_CORRUPT_TX_BITS 31:31
143 #define USB_GUSBCFG_CORRUPT_TX_SET 0x80000000
144 #define USB_GUSBCFG_CORRUPT_TX_CLR 0x7fffffff
145 #define USB_GUSBCFG_CORRUPT_TX_MSB 31
146 #define USB_GUSBCFG_CORRUPT_TX_LSB 31
147 #define USB_GUSBCFG_CORRUPT_TX_RESET 0x0
148 #define USB_GUSBCFG_FORCE_DEV_MODE_BITS 30:30
149 #define USB_GUSBCFG_FORCE_DEV_MODE_SET 0x40000000
150 #define USB_GUSBCFG_FORCE_DEV_MODE_CLR 0xbfffffff
151 #define USB_GUSBCFG_FORCE_DEV_MODE_MSB 30
152 #define USB_GUSBCFG_FORCE_DEV_MODE_LSB 30
153 #define USB_GUSBCFG_FORCE_DEV_MODE_RESET 0x0
154 #define USB_GUSBCFG_FORCE_HST_MODE_BITS 29:29
155 #define USB_GUSBCFG_FORCE_HST_MODE_SET 0x20000000
156 #define USB_GUSBCFG_FORCE_HST_MODE_CLR 0xdfffffff
157 #define USB_GUSBCFG_FORCE_HST_MODE_MSB 29
158 #define USB_GUSBCFG_FORCE_HST_MODE_LSB 29
159 #define USB_GUSBCFG_FORCE_HST_MODE_RESET 0x0
160 #define USB_GUSBCFG_ULPI_IF_PROT_DIS_BITS 25:25
161 #define USB_GUSBCFG_ULPI_IF_PROT_DIS_SET 0x02000000
162 #define USB_GUSBCFG_ULPI_IF_PROT_DIS_CLR 0xfdffffff
163 #define USB_GUSBCFG_ULPI_IF_PROT_DIS_MSB 25
164 #define USB_GUSBCFG_ULPI_IF_PROT_DIS_LSB 25
165 #define USB_GUSBCFG_ULPI_IF_PROT_DIS_RESET 0x0
166 #define USB_GUSBCFG_IND_PASS_THRU_BITS 24:24
167 #define USB_GUSBCFG_IND_PASS_THRU_SET 0x01000000
168 #define USB_GUSBCFG_IND_PASS_THRU_CLR 0xfeffffff
169 #define USB_GUSBCFG_IND_PASS_THRU_MSB 24
170 #define USB_GUSBCFG_IND_PASS_THRU_LSB 24
171 #define USB_GUSBCFG_IND_PASS_THRU_RESET 0x0
172 #define USB_GUSBCFG_IND_COMP_BITS 23:23
173 #define USB_GUSBCFG_IND_COMP_SET 0x00800000
174 #define USB_GUSBCFG_IND_COMP_CLR 0xff7fffff
175 #define USB_GUSBCFG_IND_COMP_MSB 23
176 #define USB_GUSBCFG_IND_COMP_LSB 23
177 #define USB_GUSBCFG_IND_COMP_RESET 0x0
178 #define USB_GUSBCFG_TERM_SEL_DL_PULSE_BITS 22:22
179 #define USB_GUSBCFG_TERM_SEL_DL_PULSE_SET 0x00400000
180 #define USB_GUSBCFG_TERM_SEL_DL_PULSE_CLR 0xffbfffff
181 #define USB_GUSBCFG_TERM_SEL_DL_PULSE_MSB 22
182 #define USB_GUSBCFG_TERM_SEL_DL_PULSE_LSB 22
183 #define USB_GUSBCFG_TERM_SEL_DL_PULSE_RESET 0x0
184 #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_BITS 21:21
185 #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_SET 0x00200000
186 #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_CLR 0xffdfffff
187 #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_MSB 21
188 #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_LSB 21
189 #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_RESET 0x0
190 #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_BITS 20:20
191 #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_SET 0x00100000
192 #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_CLR 0xffefffff
193 #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_MSB 20
194 #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_LSB 20
195 #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_RESET 0x0
196 #define USB_GUSBCFG_ULPI_CLK_SUS_M_BITS 19:19
197 #define USB_GUSBCFG_ULPI_CLK_SUS_M_SET 0x00080000
198 #define USB_GUSBCFG_ULPI_CLK_SUS_M_CLR 0xfff7ffff
199 #define USB_GUSBCFG_ULPI_CLK_SUS_M_MSB 19
200 #define USB_GUSBCFG_ULPI_CLK_SUS_M_LSB 19
201 #define USB_GUSBCFG_ULPI_CLK_SUS_M_RESET 0x0
202 #define USB_GUSBCFG_ULPI_AUTO_RES_BITS 18:18
203 #define USB_GUSBCFG_ULPI_AUTO_RES_SET 0x00040000
204 #define USB_GUSBCFG_ULPI_AUTO_RES_CLR 0xfffbffff
205 #define USB_GUSBCFG_ULPI_AUTO_RES_MSB 18
206 #define USB_GUSBCFG_ULPI_AUTO_RES_LSB 18
207 #define USB_GUSBCFG_ULPI_AUTO_RES_RESET 0x0
208 #define USB_GUSBCFG_ULPI_FS_LS_BITS 17:17
209 #define USB_GUSBCFG_ULPI_FS_LS_SET 0x00020000
210 #define USB_GUSBCFG_ULPI_FS_LS_CLR 0xfffdffff
211 #define USB_GUSBCFG_ULPI_FS_LS_MSB 17
212 #define USB_GUSBCFG_ULPI_FS_LS_LSB 17
213 #define USB_GUSBCFG_ULPI_FS_LS_RESET 0x0
214 #define USB_GUSBCFG_OTG_I2C_SEL_BITS 16:16
215 #define USB_GUSBCFG_OTG_I2C_SEL_SET 0x00010000
216 #define USB_GUSBCFG_OTG_I2C_SEL_CLR 0xfffeffff
217 #define USB_GUSBCFG_OTG_I2C_SEL_MSB 16
218 #define USB_GUSBCFG_OTG_I2C_SEL_LSB 16
219 #define USB_GUSBCFG_OTG_I2C_SEL_RESET 0x0
220 #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_BITS 15:15
221 #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_SET 0x00008000
222 #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_CLR 0xffff7fff
223 #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_MSB 15
224 #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_LSB 15
225 #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_RESET 0x0
226 #define USB_GUSBCFG_USB_TRD_TIM_BITS 13:10
227 #define USB_GUSBCFG_USB_TRD_TIM_SET 0x00003c00
228 #define USB_GUSBCFG_USB_TRD_TIM_CLR 0xffffc3ff
229 #define USB_GUSBCFG_USB_TRD_TIM_MSB 13
230 #define USB_GUSBCFG_USB_TRD_TIM_LSB 10
231 #define USB_GUSBCFG_USB_TRD_TIM_RESET 0x0
232 #define USB_GUSBCFG_HNP_CAP_BITS 9:9
233 #define USB_GUSBCFG_HNP_CAP_SET 0x00000200
234 #define USB_GUSBCFG_HNP_CAP_CLR 0xfffffdff
235 #define USB_GUSBCFG_HNP_CAP_MSB 9
236 #define USB_GUSBCFG_HNP_CAP_LSB 9
237 #define USB_GUSBCFG_HNP_CAP_RESET 0x0
238 #define USB_GUSBCFG_SRP_CAP_BITS 8:8
239 #define USB_GUSBCFG_SRP_CAP_SET 0x00000100
240 #define USB_GUSBCFG_SRP_CAP_CLR 0xfffffeff
241 #define USB_GUSBCFG_SRP_CAP_MSB 8
242 #define USB_GUSBCFG_SRP_CAP_LSB 8
243 #define USB_GUSBCFG_SRP_CAP_RESET 0x0
244 #define USB_GUSBCFG_DDR_SEL_BITS 7:7
245 #define USB_GUSBCFG_DDR_SEL_SET 0x00000080
246 #define USB_GUSBCFG_DDR_SEL_CLR 0xffffff7f
247 #define USB_GUSBCFG_DDR_SEL_MSB 7
248 #define USB_GUSBCFG_DDR_SEL_LSB 7
249 #define USB_GUSBCFG_DDR_SEL_RESET 0x0
250 #define USB_GUSBCFG_PHY_SEL_BITS 6:6
251 #define USB_GUSBCFG_PHY_SEL_SET 0x00000040
252 #define USB_GUSBCFG_PHY_SEL_CLR 0xffffffbf
253 #define USB_GUSBCFG_PHY_SEL_MSB 6
254 #define USB_GUSBCFG_PHY_SEL_LSB 6
255 #define USB_GUSBCFG_PHY_SEL_RESET 0x0
256 #define USB_GUSBCFG_FS_INTF_BITS 5:5
257 #define USB_GUSBCFG_FS_INTF_SET 0x00000020
258 #define USB_GUSBCFG_FS_INTF_CLR 0xffffffdf
259 #define USB_GUSBCFG_FS_INTF_MSB 5
260 #define USB_GUSBCFG_FS_INTF_LSB 5
261 #define USB_GUSBCFG_FS_INTF_RESET 0x0
262 #define USB_GUSBCFG_ULPI_UTMI_SEL_BITS 4:4
263 #define USB_GUSBCFG_ULPI_UTMI_SEL_SET 0x00000010
264 #define USB_GUSBCFG_ULPI_UTMI_SEL_CLR 0xffffffef
265 #define USB_GUSBCFG_ULPI_UTMI_SEL_MSB 4
266 #define USB_GUSBCFG_ULPI_UTMI_SEL_LSB 4
267 #define USB_GUSBCFG_ULPI_UTMI_SEL_RESET 0x0
268 #define USB_GUSBCFG_PHY_IF_BITS 3:3
269 #define USB_GUSBCFG_PHY_IF_SET 0x00000008
270 #define USB_GUSBCFG_PHY_IF_CLR 0xfffffff7
271 #define USB_GUSBCFG_PHY_IF_MSB 3
272 #define USB_GUSBCFG_PHY_IF_LSB 3
273 #define USB_GUSBCFG_PHY_IF_RESET 0x0
274 #define USB_GUSBCFG_TOUT_CAL_BITS 2:0
275 #define USB_GUSBCFG_TOUT_CAL_SET 0x00000007
276 #define USB_GUSBCFG_TOUT_CAL_CLR 0xfffffff8
277 #define USB_GUSBCFG_TOUT_CAL_MSB 2
278 #define USB_GUSBCFG_TOUT_CAL_LSB 0
279 #define USB_GUSBCFG_TOUT_CAL_RESET 0x0
280 #define USB_GRSTCTL HW_REGISTER_RW( 0x7e980010 )
281 #define USB_GRSTCTL_MASK 0xc00007ff
282 #define USB_GRSTCTL_WIDTH 32
283 #define USB_GRSTCTL_AHB_IDLE_BITS 31:31
284 #define USB_GRSTCTL_AHB_IDLE_SET 0x80000000
285 #define USB_GRSTCTL_AHB_IDLE_CLR 0x7fffffff
286 #define USB_GRSTCTL_AHB_IDLE_MSB 31
287 #define USB_GRSTCTL_AHB_IDLE_LSB 31
288 #define USB_GRSTCTL_AHB_IDLE_RESET 0x0
289 #define USB_GRSTCTL_DMA_REQ_BITS 30:30
290 #define USB_GRSTCTL_DMA_REQ_SET 0x40000000
291 #define USB_GRSTCTL_DMA_REQ_CLR 0xbfffffff
292 #define USB_GRSTCTL_DMA_REQ_MSB 30
293 #define USB_GRSTCTL_DMA_REQ_LSB 30
294 #define USB_GRSTCTL_DMA_REQ_RESET 0x0
295 #define USB_GRSTCTL_TXF_NUM_BITS 10:6
296 #define USB_GRSTCTL_TXF_NUM_SET 0x000007c0
297 #define USB_GRSTCTL_TXF_NUM_CLR 0xfffff83f
298 #define USB_GRSTCTL_TXF_NUM_MSB 10
299 #define USB_GRSTCTL_TXF_NUM_LSB 6
300 #define USB_GRSTCTL_TXF_NUM_RESET 0x0
301 #define USB_GRSTCTL_TXF_FLSH_BITS 5:5
302 #define USB_GRSTCTL_TXF_FLSH_SET 0x00000020
303 #define USB_GRSTCTL_TXF_FLSH_CLR 0xffffffdf
304 #define USB_GRSTCTL_TXF_FLSH_MSB 5
305 #define USB_GRSTCTL_TXF_FLSH_LSB 5
306 #define USB_GRSTCTL_TXF_FLSH_RESET 0x0
307 #define USB_GRSTCTL_RXF_FLSH_BITS 4:4
308 #define USB_GRSTCTL_RXF_FLSH_SET 0x00000010
309 #define USB_GRSTCTL_RXF_FLSH_CLR 0xffffffef
310 #define USB_GRSTCTL_RXF_FLSH_MSB 4
311 #define USB_GRSTCTL_RXF_FLSH_LSB 4
312 #define USB_GRSTCTL_RXF_FLSH_RESET 0x0
313 #define USB_GRSTCTL_INT_TKN_Q_FLSH_BITS 3:3
314 #define USB_GRSTCTL_INT_TKN_Q_FLSH_SET 0x00000008
315 #define USB_GRSTCTL_INT_TKN_Q_FLSH_CLR 0xfffffff7
316 #define USB_GRSTCTL_INT_TKN_Q_FLSH_MSB 3
317 #define USB_GRSTCTL_INT_TKN_Q_FLSH_LSB 3
318 #define USB_GRSTCTL_INT_TKN_Q_FLSH_RESET 0x0
319 #define USB_GRSTCTL_FRM_CNTR_RST_BITS 2:2
320 #define USB_GRSTCTL_FRM_CNTR_RST_SET 0x00000004
321 #define USB_GRSTCTL_FRM_CNTR_RST_CLR 0xfffffffb
322 #define USB_GRSTCTL_FRM_CNTR_RST_MSB 2
323 #define USB_GRSTCTL_FRM_CNTR_RST_LSB 2
324 #define USB_GRSTCTL_FRM_CNTR_RST_RESET 0x0
325 #define USB_GRSTCTL_H_SFT_RST_BITS 1:1
326 #define USB_GRSTCTL_H_SFT_RST_SET 0x00000002
327 #define USB_GRSTCTL_H_SFT_RST_CLR 0xfffffffd
328 #define USB_GRSTCTL_H_SFT_RST_MSB 1
329 #define USB_GRSTCTL_H_SFT_RST_LSB 1
330 #define USB_GRSTCTL_H_SFT_RST_RESET 0x0
331 #define USB_GRSTCTL_C_SFT_RST_BITS 0:0
332 #define USB_GRSTCTL_C_SFT_RST_SET 0x00000001
333 #define USB_GRSTCTL_C_SFT_RST_CLR 0xfffffffe
334 #define USB_GRSTCTL_C_SFT_RST_MSB 0
335 #define USB_GRSTCTL_C_SFT_RST_LSB 0
336 #define USB_GRSTCTL_C_SFT_RST_RESET 0x0
337 #define USB_GINTSTS HW_REGISTER_RW( 0x7e980014 )
338 #define USB_GINTSTS_MASK 0xffffffff
339 #define USB_GINTSTS_WIDTH 32
340 #define USB_GINTMSK HW_REGISTER_RW( 0x7e980018 )
341 #define USB_GINTMSK_MASK 0xf77effff
342 #define USB_GINTMSK_WIDTH 32
343 #define USB_GINTMSK_WK_UP_INT_BITS 31:31
344 #define USB_GINTMSK_WK_UP_INT_SET 0x80000000
345 #define USB_GINTMSK_WK_UP_INT_CLR 0x7fffffff
346 #define USB_GINTMSK_WK_UP_INT_MSB 31
347 #define USB_GINTMSK_WK_UP_INT_LSB 31
348 #define USB_GINTMSK_WK_UP_INT_RESET 0x0
349 #define USB_GINTMSK_SESS_REQ_INT_BITS 30:30
350 #define USB_GINTMSK_SESS_REQ_INT_SET 0x40000000
351 #define USB_GINTMSK_SESS_REQ_INT_CLR 0xbfffffff
352 #define USB_GINTMSK_SESS_REQ_INT_MSB 30
353 #define USB_GINTMSK_SESS_REQ_INT_LSB 30
354 #define USB_GINTMSK_SESS_REQ_INT_RESET 0x0
355 #define USB_GINTMSK_DISCONN_INT_BITS 29:29
356 #define USB_GINTMSK_DISCONN_INT_SET 0x20000000
357 #define USB_GINTMSK_DISCONN_INT_CLR 0xdfffffff
358 #define USB_GINTMSK_DISCONN_INT_MSB 29
359 #define USB_GINTMSK_DISCONN_INT_LSB 29
360 #define USB_GINTMSK_DISCONN_INT_RESET 0x0
361 #define USB_GINTMSK_CON_ID_STS_CHNG_BITS 28:28
362 #define USB_GINTMSK_CON_ID_STS_CHNG_SET 0x10000000
363 #define USB_GINTMSK_CON_ID_STS_CHNG_CLR 0xefffffff
364 #define USB_GINTMSK_CON_ID_STS_CHNG_MSB 28
365 #define USB_GINTMSK_CON_ID_STS_CHNG_LSB 28
366 #define USB_GINTMSK_CON_ID_STS_CHNG_RESET 0x0
367 #define USB_GINTMSK_P_TXF_EMP_BITS 26:26
368 #define USB_GINTMSK_P_TXF_EMP_SET 0x04000000
369 #define USB_GINTMSK_P_TXF_EMP_CLR 0xfbffffff
370 #define USB_GINTMSK_P_TXF_EMP_MSB 26
371 #define USB_GINTMSK_P_TXF_EMP_LSB 26
372 #define USB_GINTMSK_P_TXF_EMP_RESET 0x0
373 #define USB_GINTMSK_HCH_INT_BITS 25:25
374 #define USB_GINTMSK_HCH_INT_SET 0x02000000
375 #define USB_GINTMSK_HCH_INT_CLR 0xfdffffff
376 #define USB_GINTMSK_HCH_INT_MSB 25
377 #define USB_GINTMSK_HCH_INT_LSB 25
378 #define USB_GINTMSK_HCH_INT_RESET 0x0
379 #define USB_GINTMSK_PRT_INT_BITS 24:24
380 #define USB_GINTMSK_PRT_INT_SET 0x01000000
381 #define USB_GINTMSK_PRT_INT_CLR 0xfeffffff
382 #define USB_GINTMSK_PRT_INT_MSB 24
383 #define USB_GINTMSK_PRT_INT_LSB 24
384 #define USB_GINTMSK_PRT_INT_RESET 0x0
385 #define USB_GINTMSK_FET_SUSP_BITS 22:22
386 #define USB_GINTMSK_FET_SUSP_SET 0x00400000
387 #define USB_GINTMSK_FET_SUSP_CLR 0xffbfffff
388 #define USB_GINTMSK_FET_SUSP_MSB 22
389 #define USB_GINTMSK_FET_SUSP_LSB 22
390 #define USB_GINTMSK_FET_SUSP_RESET 0x0
391 #define USB_GINTMSK_INCOMPL_P_BITS 21:21
392 #define USB_GINTMSK_INCOMPL_P_SET 0x00200000
393 #define USB_GINTMSK_INCOMPL_P_CLR 0xffdfffff
394 #define USB_GINTMSK_INCOMPL_P_MSB 21
395 #define USB_GINTMSK_INCOMPL_P_LSB 21
396 #define USB_GINTMSK_INCOMPL_P_RESET 0x0
397 #define USB_GINTMSK_INCOMPL_ISO_OUT_BITS 21:21
398 #define USB_GINTMSK_INCOMPL_ISO_OUT_SET 0x00200000
399 #define USB_GINTMSK_INCOMPL_ISO_OUT_CLR 0xffdfffff
400 #define USB_GINTMSK_INCOMPL_ISO_OUT_MSB 21
401 #define USB_GINTMSK_INCOMPL_ISO_OUT_LSB 21
402 #define USB_GINTMSK_INCOMPL_ISO_OUT_RESET 0x0
403 #define USB_GINTMSK_INCOMPL_ISO_IN_BITS 20:20
404 #define USB_GINTMSK_INCOMPL_ISO_IN_SET 0x00100000
405 #define USB_GINTMSK_INCOMPL_ISO_IN_CLR 0xffefffff
406 #define USB_GINTMSK_INCOMPL_ISO_IN_MSB 20
407 #define USB_GINTMSK_INCOMPL_ISO_IN_LSB 20
408 #define USB_GINTMSK_INCOMPL_ISO_IN_RESET 0x0
409 #define USB_GINTMSK_OEP_INT_BITS 19:19
410 #define USB_GINTMSK_OEP_INT_SET 0x00080000
411 #define USB_GINTMSK_OEP_INT_CLR 0xfff7ffff
412 #define USB_GINTMSK_OEP_INT_MSB 19
413 #define USB_GINTMSK_OEP_INT_LSB 19
414 #define USB_GINTMSK_OEP_INT_RESET 0x0
415 #define USB_GINTMSK_IEP_INT_BITS 18:18
416 #define USB_GINTMSK_IEP_INT_SET 0x00040000
417 #define USB_GINTMSK_IEP_INT_CLR 0xfffbffff
418 #define USB_GINTMSK_IEP_INT_MSB 18
419 #define USB_GINTMSK_IEP_INT_LSB 18
420 #define USB_GINTMSK_IEP_INT_RESET 0x0
421 #define USB_GINTMSK_EP_MIS_BITS 17:17
422 #define USB_GINTMSK_EP_MIS_SET 0x00020000
423 #define USB_GINTMSK_EP_MIS_CLR 0xfffdffff
424 #define USB_GINTMSK_EP_MIS_MSB 17
425 #define USB_GINTMSK_EP_MIS_LSB 17
426 #define USB_GINTMSK_EP_MIS_RESET 0x0
427 #define USB_GINTMSK_EOPF_BITS 15:15
428 #define USB_GINTMSK_EOPF_SET 0x00008000
429 #define USB_GINTMSK_EOPF_CLR 0xffff7fff
430 #define USB_GINTMSK_EOPF_MSB 15
431 #define USB_GINTMSK_EOPF_LSB 15
432 #define USB_GINTMSK_EOPF_RESET 0x0
433 #define USB_GINTMSK_ISO_OUT_DROP_BITS 14:14
434 #define USB_GINTMSK_ISO_OUT_DROP_SET 0x00004000
435 #define USB_GINTMSK_ISO_OUT_DROP_CLR 0xffffbfff
436 #define USB_GINTMSK_ISO_OUT_DROP_MSB 14
437 #define USB_GINTMSK_ISO_OUT_DROP_LSB 14
438 #define USB_GINTMSK_ISO_OUT_DROP_RESET 0x0
439 #define USB_GINTMSK_ENUM_DONE_BITS 13:13
440 #define USB_GINTMSK_ENUM_DONE_SET 0x00002000
441 #define USB_GINTMSK_ENUM_DONE_CLR 0xffffdfff
442 #define USB_GINTMSK_ENUM_DONE_MSB 13
443 #define USB_GINTMSK_ENUM_DONE_LSB 13
444 #define USB_GINTMSK_ENUM_DONE_RESET 0x0
445 #define USB_GINTMSK_USB_RST_BITS 12:12
446 #define USB_GINTMSK_USB_RST_SET 0x00001000
447 #define USB_GINTMSK_USB_RST_CLR 0xffffefff
448 #define USB_GINTMSK_USB_RST_MSB 12
449 #define USB_GINTMSK_USB_RST_LSB 12
450 #define USB_GINTMSK_USB_RST_RESET 0x0
451 #define USB_GINTMSK_USB_SUSP_BITS 11:11
452 #define USB_GINTMSK_USB_SUSP_SET 0x00000800
453 #define USB_GINTMSK_USB_SUSP_CLR 0xfffff7ff
454 #define USB_GINTMSK_USB_SUSP_MSB 11
455 #define USB_GINTMSK_USB_SUSP_LSB 11
456 #define USB_GINTMSK_USB_SUSP_RESET 0x0
457 #define USB_GINTMSK_ERLY_SUSP_BITS 10:10
458 #define USB_GINTMSK_ERLY_SUSP_SET 0x00000400
459 #define USB_GINTMSK_ERLY_SUSP_CLR 0xfffffbff
460 #define USB_GINTMSK_ERLY_SUSP_MSB 10
461 #define USB_GINTMSK_ERLY_SUSP_LSB 10
462 #define USB_GINTMSK_ERLY_SUSP_RESET 0x0
463 #define USB_GINTMSK_I2C_INT_BITS 9:9
464 #define USB_GINTMSK_I2C_INT_SET 0x00000200
465 #define USB_GINTMSK_I2C_INT_CLR 0xfffffdff
466 #define USB_GINTMSK_I2C_INT_MSB 9
467 #define USB_GINTMSK_I2C_INT_LSB 9
468 #define USB_GINTMSK_I2C_INT_RESET 0x0
469 #define USB_GINTMSK_ULPI_CK_INT_BITS 8:8
470 #define USB_GINTMSK_ULPI_CK_INT_SET 0x00000100
471 #define USB_GINTMSK_ULPI_CK_INT_CLR 0xfffffeff
472 #define USB_GINTMSK_ULPI_CK_INT_MSB 8
473 #define USB_GINTMSK_ULPI_CK_INT_LSB 8
474 #define USB_GINTMSK_ULPI_CK_INT_RESET 0x0
475 #define USB_GINTMSK_GOUT_NAK_EFF_BITS 7:7
476 #define USB_GINTMSK_GOUT_NAK_EFF_SET 0x00000080
477 #define USB_GINTMSK_GOUT_NAK_EFF_CLR 0xffffff7f
478 #define USB_GINTMSK_GOUT_NAK_EFF_MSB 7
479 #define USB_GINTMSK_GOUT_NAK_EFF_LSB 7
480 #define USB_GINTMSK_GOUT_NAK_EFF_RESET 0x0
481 #define USB_GINTMSK_GIN_N_NAK_EFF_BITS 6:6
482 #define USB_GINTMSK_GIN_N_NAK_EFF_SET 0x00000040
483 #define USB_GINTMSK_GIN_N_NAK_EFF_CLR 0xffffffbf
484 #define USB_GINTMSK_GIN_N_NAK_EFF_MSB 6
485 #define USB_GINTMSK_GIN_N_NAK_EFF_LSB 6
486 #define USB_GINTMSK_GIN_N_NAK_EFF_RESET 0x0
487 #define USB_GINTMSK_NP_TXF_EMP_BITS 5:5
488 #define USB_GINTMSK_NP_TXF_EMP_SET 0x00000020
489 #define USB_GINTMSK_NP_TXF_EMP_CLR 0xffffffdf
490 #define USB_GINTMSK_NP_TXF_EMP_MSB 5
491 #define USB_GINTMSK_NP_TXF_EMP_LSB 5
492 #define USB_GINTMSK_NP_TXF_EMP_RESET 0x0
493 #define USB_GINTMSK_RXF_LVL_BITS 4:4
494 #define USB_GINTMSK_RXF_LVL_SET 0x00000010
495 #define USB_GINTMSK_RXF_LVL_CLR 0xffffffef
496 #define USB_GINTMSK_RXF_LVL_MSB 4
497 #define USB_GINTMSK_RXF_LVL_LSB 4
498 #define USB_GINTMSK_RXF_LVL_RESET 0x0
499 #define USB_GINTMSK_SOF_BITS 3:3
500 #define USB_GINTMSK_SOF_SET 0x00000008
501 #define USB_GINTMSK_SOF_CLR 0xfffffff7
502 #define USB_GINTMSK_SOF_MSB 3
503 #define USB_GINTMSK_SOF_LSB 3
504 #define USB_GINTMSK_SOF_RESET 0x0
505 #define USB_GINTMSK_OTG_INT_BITS 2:2
506 #define USB_GINTMSK_OTG_INT_SET 0x00000004
507 #define USB_GINTMSK_OTG_INT_CLR 0xfffffffb
508 #define USB_GINTMSK_OTG_INT_MSB 2
509 #define USB_GINTMSK_OTG_INT_LSB 2
510 #define USB_GINTMSK_OTG_INT_RESET 0x0
511 #define USB_GINTMSK_MODE_MIS_BITS 1:1
512 #define USB_GINTMSK_MODE_MIS_SET 0x00000002
513 #define USB_GINTMSK_MODE_MIS_CLR 0xfffffffd
514 #define USB_GINTMSK_MODE_MIS_MSB 1
515 #define USB_GINTMSK_MODE_MIS_LSB 1
516 #define USB_GINTMSK_MODE_MIS_RESET 0x0
517 #define USB_GINTMSK_CUR_MOD_BITS 0:0
518 #define USB_GINTMSK_CUR_MOD_SET 0x00000001
519 #define USB_GINTMSK_CUR_MOD_CLR 0xfffffffe
520 #define USB_GINTMSK_CUR_MOD_MSB 0
521 #define USB_GINTMSK_CUR_MOD_LSB 0
522 #define USB_GINTMSK_CUR_MOD_RESET 0x0
523 #define USB_GRXSTSR HW_REGISTER_RW( 0x7e98001c )
524 #define USB_GRXSTSR_MASK 0xffffffff
525 #define USB_GRXSTSR_WIDTH 32
526 #define USB_GRXSTSP HW_REGISTER_RW( 0x7e980020 )
527 #define USB_GRXSTSP_MASK 0x01ffffff
528 #define USB_GRXSTSP_WIDTH 25
529 #define USB_GRXSTSP_HST_PKT_STS_BITS 20:17
530 #define USB_GRXSTSP_HST_PKT_STS_SET 0x001e0000
531 #define USB_GRXSTSP_HST_PKT_STS_CLR 0xffe1ffff
532 #define USB_GRXSTSP_HST_PKT_STS_MSB 20
533 #define USB_GRXSTSP_HST_PKT_STS_LSB 17
534 #define USB_GRXSTSP_HST_PKT_STS_RESET 0x0
535 #define USB_GRXSTSP_HST_DPID_BITS 16:15
536 #define USB_GRXSTSP_HST_DPID_SET 0x00018000
537 #define USB_GRXSTSP_HST_DPID_CLR 0xfffe7fff
538 #define USB_GRXSTSP_HST_DPID_MSB 16
539 #define USB_GRXSTSP_HST_DPID_LSB 15
540 #define USB_GRXSTSP_HST_DPID_RESET 0x0
541 #define USB_GRXSTSP_HST_BCNT_BITS 14:4
542 #define USB_GRXSTSP_HST_BCNT_SET 0x00007ff0
543 #define USB_GRXSTSP_HST_BCNT_CLR 0xffff800f
544 #define USB_GRXSTSP_HST_BCNT_MSB 14
545 #define USB_GRXSTSP_HST_BCNT_LSB 4
546 #define USB_GRXSTSP_HST_BCNT_RESET 0x0
547 #define USB_GRXSTSP_HST_CH_NUM_BITS 3:0
548 #define USB_GRXSTSP_HST_CH_NUM_SET 0x0000000f
549 #define USB_GRXSTSP_HST_CH_NUM_CLR 0xfffffff0
550 #define USB_GRXSTSP_HST_CH_NUM_MSB 3
551 #define USB_GRXSTSP_HST_CH_NUM_LSB 0
552 #define USB_GRXSTSP_HST_CH_NUM_RESET 0x0
553 #define USB_GRXSTSP_DEV_FN_BITS 24:21
554 #define USB_GRXSTSP_DEV_FN_SET 0x01e00000
555 #define USB_GRXSTSP_DEV_FN_CLR 0xfe1fffff
556 #define USB_GRXSTSP_DEV_FN_MSB 24
557 #define USB_GRXSTSP_DEV_FN_LSB 21
558 #define USB_GRXSTSP_DEV_FN_RESET 0x0
559 #define USB_GRXSTSP_DEV_PKT_STS_BITS 20:17
560 #define USB_GRXSTSP_DEV_PKT_STS_SET 0x001e0000
561 #define USB_GRXSTSP_DEV_PKT_STS_CLR 0xffe1ffff
562 #define USB_GRXSTSP_DEV_PKT_STS_MSB 20
563 #define USB_GRXSTSP_DEV_PKT_STS_LSB 17
564 #define USB_GRXSTSP_DEV_PKT_STS_RESET 0x0
565 #define USB_GRXSTSP_DEV_DPID_BITS 16:15
566 #define USB_GRXSTSP_DEV_DPID_SET 0x00018000
567 #define USB_GRXSTSP_DEV_DPID_CLR 0xfffe7fff
568 #define USB_GRXSTSP_DEV_DPID_MSB 16
569 #define USB_GRXSTSP_DEV_DPID_LSB 15
570 #define USB_GRXSTSP_DEV_DPID_RESET 0x0
571 #define USB_GRXSTSP_DEV_BCNT_BITS 14:4
572 #define USB_GRXSTSP_DEV_BCNT_SET 0x00007ff0
573 #define USB_GRXSTSP_DEV_BCNT_CLR 0xffff800f
574 #define USB_GRXSTSP_DEV_BCNT_MSB 14
575 #define USB_GRXSTSP_DEV_BCNT_LSB 4
576 #define USB_GRXSTSP_DEV_BCNT_RESET 0x0
577 #define USB_GRXSTSP_DEV_EP_NUM_BITS 3:0
578 #define USB_GRXSTSP_DEV_EP_NUM_SET 0x0000000f
579 #define USB_GRXSTSP_DEV_EP_NUM_CLR 0xfffffff0
580 #define USB_GRXSTSP_DEV_EP_NUM_MSB 3
581 #define USB_GRXSTSP_DEV_EP_NUM_LSB 0
582 #define USB_GRXSTSP_DEV_EP_NUM_RESET 0x0
583 #define USB_GRXFSIZ HW_REGISTER_RW( 0x7e980024 )
584 #define USB_GRXFSIZ_MASK 0x0000ffff
585 #define USB_GRXFSIZ_WIDTH 16
586 #define USB_GRXFSIZ_GRXF_DEP_BITS 15:0
587 #define USB_GRXFSIZ_GRXF_DEP_SET 0x0000ffff
588 #define USB_GRXFSIZ_GRXF_DEP_CLR 0xffff0000
589 #define USB_GRXFSIZ_GRXF_DEP_MSB 15
590 #define USB_GRXFSIZ_GRXF_DEP_LSB 0
591 #define USB_GRXFSIZ_GRXF_DEP_RESET 0x0
592 #define USB_GNPTXFSIZ HW_REGISTER_RW( 0x7e980028 )
593 #define USB_GNPTXFSIZ_MASK 0xffffffff
594 #define USB_GNPTXFSIZ_WIDTH 32
595 #define USB_GNPTXFSIZ_NP_TXF_DEP_BITS 31:16
596 #define USB_GNPTXFSIZ_NP_TXF_DEP_SET 0xffff0000
597 #define USB_GNPTXFSIZ_NP_TXF_DEP_CLR 0x0000ffff
598 #define USB_GNPTXFSIZ_NP_TXF_DEP_MSB 31
599 #define USB_GNPTXFSIZ_NP_TXF_DEP_LSB 16
600 #define USB_GNPTXFSIZ_NP_TXF_DEP_RESET 0x0
601 #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_BITS 15:0
602 #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_SET 0x0000ffff
603 #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_CLR 0xffff0000
604 #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_MSB 15
605 #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_LSB 0
606 #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_RESET 0x0
607 #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_BITS 31:16
608 #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_SET 0xffff0000
609 #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_CLR 0x0000ffff
610 #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_MSB 31
611 #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_LSB 16
612 #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_RESET 0x0
613 #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_BITS 15:0
614 #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_SET 0x0000ffff
615 #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_CLR 0xffff0000
616 #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_MSB 15
617 #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_LSB 0
618 #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_RESET 0x0
619 #define USB_GNPTXSTS HW_REGISTER_RW( 0x7e98002c )
620 #define USB_GNPTXSTS_MASK 0x7fffffff
621 #define USB_GNPTXSTS_WIDTH 31
622 #define USB_GNPTXSTS_TX_Q_TOP_BITS 30:24
623 #define USB_GNPTXSTS_TX_Q_TOP_SET 0x7f000000
624 #define USB_GNPTXSTS_TX_Q_TOP_CLR 0x80ffffff
625 #define USB_GNPTXSTS_TX_Q_TOP_MSB 30
626 #define USB_GNPTXSTS_TX_Q_TOP_LSB 24
627 #define USB_GNPTXSTS_TX_Q_TOP_RESET 0x0
628 #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_BITS 23:16
629 #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_SET 0x00ff0000
630 #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_CLR 0xff00ffff
631 #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_MSB 23
632 #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_LSB 16
633 #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_RESET 0x0
634 #define USB_GNPTXSTS_TXF_SPC_AVAIL_BITS 15:0
635 #define USB_GNPTXSTS_TXF_SPC_AVAIL_SET 0x0000ffff
636 #define USB_GNPTXSTS_TXF_SPC_AVAIL_CLR 0xffff0000
637 #define USB_GNPTXSTS_TXF_SPC_AVAIL_MSB 15
638 #define USB_GNPTXSTS_TXF_SPC_AVAIL_LSB 0
639 #define USB_GNPTXSTS_TXF_SPC_AVAIL_RESET 0x0
640 #define USB_GI2CCTL HW_REGISTER_RW( 0x7e980030 )
641 #define USB_GI2CCTL_MASK 0xdfffffff
642 #define USB_GI2CCTL_WIDTH 32
643 #define USB_GI2CCTL_BSY_DNE_BITS 31:31
644 #define USB_GI2CCTL_BSY_DNE_SET 0x80000000
645 #define USB_GI2CCTL_BSY_DNE_CLR 0x7fffffff
646 #define USB_GI2CCTL_BSY_DNE_MSB 31
647 #define USB_GI2CCTL_BSY_DNE_LSB 31
648 #define USB_GI2CCTL_BSY_DNE_RESET 0x0
649 #define USB_GI2CCTL_RW_BITS 30:30
650 #define USB_GI2CCTL_RW_SET 0x40000000
651 #define USB_GI2CCTL_RW_CLR 0xbfffffff
652 #define USB_GI2CCTL_RW_MSB 30
653 #define USB_GI2CCTL_RW_LSB 30
654 #define USB_GI2CCTL_RW_RESET 0x0
655 #define USB_GI2CCTL_DAT_SE0_BITS 28:28
656 #define USB_GI2CCTL_DAT_SE0_SET 0x10000000
657 #define USB_GI2CCTL_DAT_SE0_CLR 0xefffffff
658 #define USB_GI2CCTL_DAT_SE0_MSB 28
659 #define USB_GI2CCTL_DAT_SE0_LSB 28
660 #define USB_GI2CCTL_DAT_SE0_RESET 0x0
661 #define USB_GI2CCTL_DEV_ADR_BITS 27:26
662 #define USB_GI2CCTL_DEV_ADR_SET 0x0c000000
663 #define USB_GI2CCTL_DEV_ADR_CLR 0xf3ffffff
664 #define USB_GI2CCTL_DEV_ADR_MSB 27
665 #define USB_GI2CCTL_DEV_ADR_LSB 26
666 #define USB_GI2CCTL_DEV_ADR_RESET 0x0
667 #define USB_GI2CCTL_SUSP_CTL_BITS 25:25
668 #define USB_GI2CCTL_SUSP_CTL_SET 0x02000000
669 #define USB_GI2CCTL_SUSP_CTL_CLR 0xfdffffff
670 #define USB_GI2CCTL_SUSP_CTL_MSB 25
671 #define USB_GI2CCTL_SUSP_CTL_LSB 25
672 #define USB_GI2CCTL_SUSP_CTL_RESET 0x0
673 #define USB_GI2CCTL_EN_BITS 23:23
674 #define USB_GI2CCTL_EN_SET 0x00800000
675 #define USB_GI2CCTL_EN_CLR 0xff7fffff
676 #define USB_GI2CCTL_EN_MSB 23
677 #define USB_GI2CCTL_EN_LSB 23
678 #define USB_GI2CCTL_EN_RESET 0x0
679 #define USB_GI2CCTL_ADDR_BITS 22:16
680 #define USB_GI2CCTL_ADDR_SET 0x007f0000
681 #define USB_GI2CCTL_ADDR_CLR 0xff80ffff
682 #define USB_GI2CCTL_ADDR_MSB 22
683 #define USB_GI2CCTL_ADDR_LSB 16
684 #define USB_GI2CCTL_ADDR_RESET 0x0
685 #define USB_GI2CCTL_REG_ADDR_BITS 15:8
686 #define USB_GI2CCTL_REG_ADDR_SET 0x0000ff00
687 #define USB_GI2CCTL_REG_ADDR_CLR 0xffff00ff
688 #define USB_GI2CCTL_REG_ADDR_MSB 15
689 #define USB_GI2CCTL_REG_ADDR_LSB 8
690 #define USB_GI2CCTL_REG_ADDR_RESET 0x0
691 #define USB_GI2CCTL_RW_DATA_BITS 7:0
692 #define USB_GI2CCTL_RW_DATA_SET 0x000000ff
693 #define USB_GI2CCTL_RW_DATA_CLR 0xffffff00
694 #define USB_GI2CCTL_RW_DATA_MSB 7
695 #define USB_GI2CCTL_RW_DATA_LSB 0
696 #define USB_GI2CCTL_RW_DATA_RESET 0x0
697 #define USB_GPVNDCTL HW_REGISTER_RW( 0x7e980034 )
698 #define USB_GPVNDCTL_MASK 0x8e7f3fff
699 #define USB_GPVNDCTL_WIDTH 32
700 #define USB_GPVNDCTL_DIS_ULPI_DRVR_BITS 31:31
701 #define USB_GPVNDCTL_DIS_ULPI_DRVR_SET 0x80000000
702 #define USB_GPVNDCTL_DIS_ULPI_DRVR_CLR 0x7fffffff
703 #define USB_GPVNDCTL_DIS_ULPI_DRVR_MSB 31
704 #define USB_GPVNDCTL_DIS_ULPI_DRVR_LSB 31
705 #define USB_GPVNDCTL_DIS_ULPI_DRVR_RESET 0x0
706 #define USB_GPVNDCTL_STS_DONE_BITS 27:27
707 #define USB_GPVNDCTL_STS_DONE_SET 0x08000000
708 #define USB_GPVNDCTL_STS_DONE_CLR 0xf7ffffff
709 #define USB_GPVNDCTL_STS_DONE_MSB 27
710 #define USB_GPVNDCTL_STS_DONE_LSB 27
711 #define USB_GPVNDCTL_STS_DONE_RESET 0x0
712 #define USB_GPVNDCTL_STS_BSY_BITS 26:26
713 #define USB_GPVNDCTL_STS_BSY_SET 0x04000000
714 #define USB_GPVNDCTL_STS_BSY_CLR 0xfbffffff
715 #define USB_GPVNDCTL_STS_BSY_MSB 26
716 #define USB_GPVNDCTL_STS_BSY_LSB 26
717 #define USB_GPVNDCTL_STS_BSY_RESET 0x0
718 #define USB_GPVNDCTL_NEW_REG_REQ_BITS 25:25
719 #define USB_GPVNDCTL_NEW_REG_REQ_SET 0x02000000
720 #define USB_GPVNDCTL_NEW_REG_REQ_CLR 0xfdffffff
721 #define USB_GPVNDCTL_NEW_REG_REQ_MSB 25
722 #define USB_GPVNDCTL_NEW_REG_REQ_LSB 25
723 #define USB_GPVNDCTL_NEW_REG_REQ_RESET 0x0
724 #define USB_GPVNDCTL_REG_WR_BITS 22:22
725 #define USB_GPVNDCTL_REG_WR_SET 0x00400000
726 #define USB_GPVNDCTL_REG_WR_CLR 0xffbfffff
727 #define USB_GPVNDCTL_REG_WR_MSB 22
728 #define USB_GPVNDCTL_REG_WR_LSB 22
729 #define USB_GPVNDCTL_REG_WR_RESET 0x0
730 #define USB_GPVNDCTL_REG_ADDR_BITS 21:16
731 #define USB_GPVNDCTL_REG_ADDR_SET 0x003f0000
732 #define USB_GPVNDCTL_REG_ADDR_CLR 0xffc0ffff
733 #define USB_GPVNDCTL_REG_ADDR_MSB 21
734 #define USB_GPVNDCTL_REG_ADDR_LSB 16
735 #define USB_GPVNDCTL_REG_ADDR_RESET 0x0
736 #define USB_GPVNDCTL_CTRL_UTMI_BITS 11:8
737 #define USB_GPVNDCTL_CTRL_UTMI_SET 0x00000f00
738 #define USB_GPVNDCTL_CTRL_UTMI_CLR 0xfffff0ff
739 #define USB_GPVNDCTL_CTRL_UTMI_MSB 11
740 #define USB_GPVNDCTL_CTRL_UTMI_LSB 8
741 #define USB_GPVNDCTL_CTRL_UTMI_RESET 0x0
742 #define USB_GPVNDCTL_CTRL_ULPI_BITS 13:8
743 #define USB_GPVNDCTL_CTRL_ULPI_SET 0x00003f00
744 #define USB_GPVNDCTL_CTRL_ULPI_CLR 0xffffc0ff
745 #define USB_GPVNDCTL_CTRL_ULPI_MSB 13
746 #define USB_GPVNDCTL_CTRL_ULPI_LSB 8
747 #define USB_GPVNDCTL_CTRL_ULPI_RESET 0x0
748 #define USB_GPVNDCTL_REG_DATA_BITS 7:0
749 #define USB_GPVNDCTL_REG_DATA_SET 0x000000ff
750 #define USB_GPVNDCTL_REG_DATA_CLR 0xffffff00
751 #define USB_GPVNDCTL_REG_DATA_MSB 7
752 #define USB_GPVNDCTL_REG_DATA_LSB 0
753 #define USB_GPVNDCTL_REG_DATA_RESET 0x0
754 #define USB_GGPIO HW_REGISTER_RW( 0x7e980038 )
755 #define USB_GGPIO_MASK 0xffffffff
756 #define USB_GGPIO_WIDTH 32
757 #define USB_GGPIO_GPO_BITS 31:16
758 #define USB_GGPIO_GPO_SET 0xffff0000
759 #define USB_GGPIO_GPO_CLR 0x0000ffff
760 #define USB_GGPIO_GPO_MSB 31
761 #define USB_GGPIO_GPO_LSB 16
762 #define USB_GGPIO_GPO_RESET 0x0
763 #define USB_GGPIO_GPI_BITS 15:0
764 #define USB_GGPIO_GPI_SET 0x0000ffff
765 #define USB_GGPIO_GPI_CLR 0xffff0000
766 #define USB_GGPIO_GPI_MSB 15
767 #define USB_GGPIO_GPI_LSB 0
768 #define USB_GGPIO_GPI_RESET 0x0
769 #define USB_GUID HW_REGISTER_RW( 0x7e98003c )
770 #define USB_GUID_MASK 0xffffffff
771 #define USB_GUID_WIDTH 32
772 #define USB_GSNPSID HW_REGISTER_RW( 0x7e980040 )
773 #define USB_GSNPSID_MASK 0xffffffff
774 #define USB_GSNPSID_WIDTH 32
775 #define USB_GHWCFG1 HW_REGISTER_RW( 0x7e980044 )
776 #define USB_GHWCFG1_MASK 0xffffffff
777 #define USB_GHWCFG1_WIDTH 32
778 #define USB_GHWCFG2 HW_REGISTER_RW( 0x7e980048 )
779 #define USB_GHWCFG2_MASK 0x7fcfffff
780 #define USB_GHWCFG2_WIDTH 31
781 #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_BITS 30:26
782 #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_SET 0x7c000000
783 #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_CLR 0x83ffffff
784 #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_MSB 30
785 #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_LSB 26
786 #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_RESET 0x0
787 #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_BITS 25:24
788 #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_SET 0x03000000
789 #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_CLR 0xfcffffff
790 #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_MSB 25
791 #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_LSB 24
792 #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_RESET 0x0
793 #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_BITS 23:22
794 #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_SET 0x00c00000
795 #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_CLR 0xff3fffff
796 #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_MSB 23
797 #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_LSB 22
798 #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_RESET 0x0
799 #define USB_GHWCFG2_DFIFO_DYNAMIC_BITS 19:19
800 #define USB_GHWCFG2_DFIFO_DYNAMIC_SET 0x00080000
801 #define USB_GHWCFG2_DFIFO_DYNAMIC_CLR 0xfff7ffff
802 #define USB_GHWCFG2_DFIFO_DYNAMIC_MSB 19
803 #define USB_GHWCFG2_DFIFO_DYNAMIC_LSB 19
804 #define USB_GHWCFG2_DFIFO_DYNAMIC_RESET 0x0
805 #define USB_GHWCFG2_EN_PERIO_HOST_BITS 18:18
806 #define USB_GHWCFG2_EN_PERIO_HOST_SET 0x00040000
807 #define USB_GHWCFG2_EN_PERIO_HOST_CLR 0xfffbffff
808 #define USB_GHWCFG2_EN_PERIO_HOST_MSB 18
809 #define USB_GHWCFG2_EN_PERIO_HOST_LSB 18
810 #define USB_GHWCFG2_EN_PERIO_HOST_RESET 0x0
811 #define USB_GHWCFG2_NUM_HOST_CHAN_BITS 14:17
812 #define USB_GHWCFG2_NUM_HOST_CHAN_SET 0x0000000000
813 #define USB_GHWCFG2_NUM_HOST_CHAN_CLR 0xffffffff11
814 #define USB_GHWCFG2_NUM_HOST_CHAN_MSB 14
815 #define USB_GHWCFG2_NUM_HOST_CHAN_LSB 17
816 #define USB_GHWCFG2_NUM_HOST_CHAN_RESET 0x0
817 #define USB_GHWCFG2_NUM_EPS_BITS 10:13
818 #define USB_GHWCFG2_NUM_EPS_SET 0x0000000000
819 #define USB_GHWCFG2_NUM_EPS_CLR 0xffffffff11
820 #define USB_GHWCFG2_NUM_EPS_MSB 10
821 #define USB_GHWCFG2_NUM_EPS_LSB 13
822 #define USB_GHWCFG2_NUM_EPS_RESET 0x0
823 #define USB_GHWCFG2_FSPHY_INTERFACE_BITS 9:8
824 #define USB_GHWCFG2_FSPHY_INTERFACE_SET 0x00000300
825 #define USB_GHWCFG2_FSPHY_INTERFACE_CLR 0xfffffcff
826 #define USB_GHWCFG2_FSPHY_INTERFACE_MSB 9
827 #define USB_GHWCFG2_FSPHY_INTERFACE_LSB 8
828 #define USB_GHWCFG2_FSPHY_INTERFACE_RESET 0x0
829 #define USB_GHWCFG2_HSPHY_INTERFACE_BITS 7:6
830 #define USB_GHWCFG2_HSPHY_INTERFACE_SET 0x000000c0
831 #define USB_GHWCFG2_HSPHY_INTERFACE_CLR 0xffffff3f
832 #define USB_GHWCFG2_HSPHY_INTERFACE_MSB 7
833 #define USB_GHWCFG2_HSPHY_INTERFACE_LSB 6
834 #define USB_GHWCFG2_HSPHY_INTERFACE_RESET 0x0
835 #define USB_GHWCFG2_SINGLE_POINT_BITS 5:5
836 #define USB_GHWCFG2_SINGLE_POINT_SET 0x00000020
837 #define USB_GHWCFG2_SINGLE_POINT_CLR 0xffffffdf
838 #define USB_GHWCFG2_SINGLE_POINT_MSB 5
839 #define USB_GHWCFG2_SINGLE_POINT_LSB 5
840 #define USB_GHWCFG2_SINGLE_POINT_RESET 0x0
841 #define USB_GHWCFG2_ARCHITECTURE_BITS 4:3
842 #define USB_GHWCFG2_ARCHITECTURE_SET 0x00000018
843 #define USB_GHWCFG2_ARCHITECTURE_CLR 0xffffffe7
844 #define USB_GHWCFG2_ARCHITECTURE_MSB 4
845 #define USB_GHWCFG2_ARCHITECTURE_LSB 3
846 #define USB_GHWCFG2_ARCHITECTURE_RESET 0x0
847 #define USB_GHWCFG2_MODE_BITS 2:0
848 #define USB_GHWCFG2_MODE_SET 0x00000007
849 #define USB_GHWCFG2_MODE_CLR 0xfffffff8
850 #define USB_GHWCFG2_MODE_MSB 2
851 #define USB_GHWCFG2_MODE_LSB 0
852 #define USB_GHWCFG2_MODE_RESET 0x0
853 #define USB_GHWCFG3 HW_REGISTER_RW( 0x7e98004c )
854 #define USB_GHWCFG3_MASK 0xffff0fff
855 #define USB_GHWCFG3_WIDTH 32
856 #define USB_GHWCFG3_DFIFO_DEPTH_BITS 31:16
857 #define USB_GHWCFG3_DFIFO_DEPTH_SET 0xffff0000
858 #define USB_GHWCFG3_DFIFO_DEPTH_CLR 0x0000ffff
859 #define USB_GHWCFG3_DFIFO_DEPTH_MSB 31
860 #define USB_GHWCFG3_DFIFO_DEPTH_LSB 16
861 #define USB_GHWCFG3_DFIFO_DEPTH_RESET 0x0
862 #define USB_GHWCFG3_SYNC_RESET_TYPE_BITS 11:11
863 #define USB_GHWCFG3_SYNC_RESET_TYPE_SET 0x00000800
864 #define USB_GHWCFG3_SYNC_RESET_TYPE_CLR 0xfffff7ff
865 #define USB_GHWCFG3_SYNC_RESET_TYPE_MSB 11
866 #define USB_GHWCFG3_SYNC_RESET_TYPE_LSB 11
867 #define USB_GHWCFG3_SYNC_RESET_TYPE_RESET 0x0
868 #define USB_GHWCFG3_RM_OPT_FEATURES_BITS 10:10
869 #define USB_GHWCFG3_RM_OPT_FEATURES_SET 0x00000400
870 #define USB_GHWCFG3_RM_OPT_FEATURES_CLR 0xfffffbff
871 #define USB_GHWCFG3_RM_OPT_FEATURES_MSB 10
872 #define USB_GHWCFG3_RM_OPT_FEATURES_LSB 10
873 #define USB_GHWCFG3_RM_OPT_FEATURES_RESET 0x0
874 #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_BITS 9:9
875 #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_SET 0x00000200
876 #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_CLR 0xfffffdff
877 #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_MSB 9
878 #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_LSB 9
879 #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_RESET 0x0
880 #define USB_GHWCFG3_I2C_INTERFACE_BITS 8:8
881 #define USB_GHWCFG3_I2C_INTERFACE_SET 0x00000100
882 #define USB_GHWCFG3_I2C_INTERFACE_CLR 0xfffffeff
883 #define USB_GHWCFG3_I2C_INTERFACE_MSB 8
884 #define USB_GHWCFG3_I2C_INTERFACE_LSB 8
885 #define USB_GHWCFG3_I2C_INTERFACE_RESET 0x0
886 #define USB_GHWCFG3_MODE_BITS 7:7
887 #define USB_GHWCFG3_MODE_SET 0x00000080
888 #define USB_GHWCFG3_MODE_CLR 0xffffff7f
889 #define USB_GHWCFG3_MODE_MSB 7
890 #define USB_GHWCFG3_MODE_LSB 7
891 #define USB_GHWCFG3_MODE_RESET 0x0
892 #define USB_GHWCFG3_PACKET_COUNT_WIDTH_BITS 6:4
893 #define USB_GHWCFG3_PACKET_COUNT_WIDTH_SET 0x00000070
894 #define USB_GHWCFG3_PACKET_COUNT_WIDTH_CLR 0xffffff8f
895 #define USB_GHWCFG3_PACKET_COUNT_WIDTH_MSB 6
896 #define USB_GHWCFG3_PACKET_COUNT_WIDTH_LSB 4
897 #define USB_GHWCFG3_PACKET_COUNT_WIDTH_RESET 0x0
898 #define USB_GHWCFG3_TRANS_COUNT_WIDTH_BITS 3:0
899 #define USB_GHWCFG3_TRANS_COUNT_WIDTH_SET 0x0000000f
900 #define USB_GHWCFG3_TRANS_COUNT_WIDTH_CLR 0xfffffff0
901 #define USB_GHWCFG3_TRANS_COUNT_WIDTH_MSB 3
902 #define USB_GHWCFG3_TRANS_COUNT_WIDTH_LSB 0
903 #define USB_GHWCFG3_TRANS_COUNT_WIDTH_RESET 0x0
904 #define USB_GHWCFG4 HW_REGISTER_RW( 0x7e980050 )
905 #define USB_GHWCFG4_MASK 0xffffc03f
906 #define USB_GHWCFG4_WIDTH 32
907 #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_BITS 31:31
908 #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_SET 0x80000000
909 #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_CLR 0x7fffffff
910 #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_MSB 31
911 #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_LSB 31
912 #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_RESET 0x0
913 #define USB_GHWCFG4_EN_DESC_DMA_BITS 30:30
914 #define USB_GHWCFG4_EN_DESC_DMA_SET 0x40000000
915 #define USB_GHWCFG4_EN_DESC_DMA_CLR 0xbfffffff
916 #define USB_GHWCFG4_EN_DESC_DMA_MSB 30
917 #define USB_GHWCFG4_EN_DESC_DMA_LSB 30
918 #define USB_GHWCFG4_EN_DESC_DMA_RESET 0x0
919 #define USB_GHWCFG4_NUM_IN_EPS_BITS 27:26
920 #define USB_GHWCFG4_NUM_IN_EPS_SET 0x0c000000
921 #define USB_GHWCFG4_NUM_IN_EPS_CLR 0xf3ffffff
922 #define USB_GHWCFG4_NUM_IN_EPS_MSB 27
923 #define USB_GHWCFG4_NUM_IN_EPS_LSB 26
924 #define USB_GHWCFG4_NUM_IN_EPS_RESET 0x0
925 #define USB_GHWCFG4_EN_DED_TX_FIFO_BITS 25:25
926 #define USB_GHWCFG4_EN_DED_TX_FIFO_SET 0x02000000
927 #define USB_GHWCFG4_EN_DED_TX_FIFO_CLR 0xfdffffff
928 #define USB_GHWCFG4_EN_DED_TX_FIFO_MSB 25
929 #define USB_GHWCFG4_EN_DED_TX_FIFO_LSB 25
930 #define USB_GHWCFG4_EN_DED_TX_FIFO_RESET 0x0
931 #define USB_GHWCFG4_EN_SESSIONEND_FILTER_BITS 24:24
932 #define USB_GHWCFG4_EN_SESSIONEND_FILTER_SET 0x01000000
933 #define USB_GHWCFG4_EN_SESSIONEND_FILTER_CLR 0xfeffffff
934 #define USB_GHWCFG4_EN_SESSIONEND_FILTER_MSB 24
935 #define USB_GHWCFG4_EN_SESSIONEND_FILTER_LSB 24
936 #define USB_GHWCFG4_EN_SESSIONEND_FILTER_RESET 0x0
937 #define USB_GHWCFG4_EN_B_VALID_FILTER_BITS 23:23
938 #define USB_GHWCFG4_EN_B_VALID_FILTER_SET 0x00800000
939 #define USB_GHWCFG4_EN_B_VALID_FILTER_CLR 0xff7fffff
940 #define USB_GHWCFG4_EN_B_VALID_FILTER_MSB 23
941 #define USB_GHWCFG4_EN_B_VALID_FILTER_LSB 23
942 #define USB_GHWCFG4_EN_B_VALID_FILTER_RESET 0x0
943 #define USB_GHWCFG4_EN_A_VALID_FILTER_BITS 22:22
944 #define USB_GHWCFG4_EN_A_VALID_FILTER_SET 0x00400000
945 #define USB_GHWCFG4_EN_A_VALID_FILTER_CLR 0xffbfffff
946 #define USB_GHWCFG4_EN_A_VALID_FILTER_MSB 22
947 #define USB_GHWCFG4_EN_A_VALID_FILTER_LSB 22
948 #define USB_GHWCFG4_EN_A_VALID_FILTER_RESET 0x0
949 #define USB_GHWCFG4_EN_VBUSVALID_FILTER_BITS 21:21
950 #define USB_GHWCFG4_EN_VBUSVALID_FILTER_SET 0x00200000
951 #define USB_GHWCFG4_EN_VBUSVALID_FILTER_CLR 0xffdfffff
952 #define USB_GHWCFG4_EN_VBUSVALID_FILTER_MSB 21
953 #define USB_GHWCFG4_EN_VBUSVALID_FILTER_LSB 21
954 #define USB_GHWCFG4_EN_VBUSVALID_FILTER_RESET 0x0
955 #define USB_GHWCFG4_EN_IDDIG_FILTER_BITS 20:20
956 #define USB_GHWCFG4_EN_IDDIG_FILTER_SET 0x00100000
957 #define USB_GHWCFG4_EN_IDDIG_FILTER_CLR 0xffefffff
958 #define USB_GHWCFG4_EN_IDDIG_FILTER_MSB 20
959 #define USB_GHWCFG4_EN_IDDIG_FILTER_LSB 20
960 #define USB_GHWCFG4_EN_IDDIG_FILTER_RESET 0x0
961 #define USB_GHWCFG4_NUM_CRL_EPS_BITS 19:16
962 #define USB_GHWCFG4_NUM_CRL_EPS_SET 0x000f0000
963 #define USB_GHWCFG4_NUM_CRL_EPS_CLR 0xfff0ffff
964 #define USB_GHWCFG4_NUM_CRL_EPS_MSB 19
965 #define USB_GHWCFG4_NUM_CRL_EPS_LSB 16
966 #define USB_GHWCFG4_NUM_CRL_EPS_RESET 0x0
967 #define USB_GHWCFG4_HSPHY_DWIDTH_BITS 15:14
968 #define USB_GHWCFG4_HSPHY_DWIDTH_SET 0x0000c000
969 #define USB_GHWCFG4_HSPHY_DWIDTH_CLR 0xffff3fff
970 #define USB_GHWCFG4_HSPHY_DWIDTH_MSB 15
971 #define USB_GHWCFG4_HSPHY_DWIDTH_LSB 14
972 #define USB_GHWCFG4_HSPHY_DWIDTH_RESET 0x0
973 #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_BITS 5:5
974 #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_SET 0x00000020
975 #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_CLR 0xffffffdf
976 #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_MSB 5
977 #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_LSB 5
978 #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_RESET 0x0
979 #define USB_GHWCFG4_EN_PWROPT_BITS 4:4
980 #define USB_GHWCFG4_EN_PWROPT_SET 0x00000010
981 #define USB_GHWCFG4_EN_PWROPT_CLR 0xffffffef
982 #define USB_GHWCFG4_EN_PWROPT_MSB 4
983 #define USB_GHWCFG4_EN_PWROPT_LSB 4
984 #define USB_GHWCFG4_EN_PWROPT_RESET 0x0
985 #define USB_GHWCFG4_NUM_PERIO_EPS_BITS 3:0
986 #define USB_GHWCFG4_NUM_PERIO_EPS_SET 0x0000000f
987 #define USB_GHWCFG4_NUM_PERIO_EPS_CLR 0xfffffff0
988 #define USB_GHWCFG4_NUM_PERIO_EPS_MSB 3
989 #define USB_GHWCFG4_NUM_PERIO_EPS_LSB 0
990 #define USB_GHWCFG4_NUM_PERIO_EPS_RESET 0x0
991 #define USB_GLPMCFG HW_REGISTER_RW( 0x7e980054 )
992 #define USB_GLPMCFG_MASK 0xffffffff
993 #define USB_GLPMCFG_WIDTH 32
994 #define USB_GAXIDEV HW_REGISTER_RW( 0x7e980054 )
995 #define USB_GAXIDEV_MASK 0xffffffff
996 #define USB_GAXIDEV_WIDTH 32
997 #define USB_GMDIOCSR HW_REGISTER_RW( 0x7e980080 )
998 #define USB_GMDIOCSR_MASK 0x0000ffff
999 #define USB_GMDIOCSR_WIDTH 16
1000 #define USB_GMDIOGEN HW_REGISTER_RW( 0x7e980084 )
1001 #define USB_GMDIOGEN_MASK 0xffffffff
1002 #define USB_GMDIOGEN_WIDTH 32
1003 #define USB_GVBUSDRV HW_REGISTER_RW( 0x7e980088 )
1004 #define USB_GVBUSDRV_MASK 0x0000ffff
1005 #define USB_GVBUSDRV_WIDTH 16
1006 #define USB_HPTXFSIZ HW_REGISTER_RW( 0x7e980100 )
1007 #define USB_HPTXFSIZ_MASK 0xffffffff
1008 #define USB_HPTXFSIZ_WIDTH 32
1009 #define USB_DPTXFSIZ1 HW_REGISTER_RW( 0x7e980104 )
1010 #define USB_DPTXFSIZ1_MASK 0xffffffff
1011 #define USB_DPTXFSIZ1_WIDTH 32
1012 #define USB_DPTXFSIZ2 HW_REGISTER_RW( 0x7e980108 )
1013 #define USB_DPTXFSIZ2_MASK 0xffffffff
1014 #define USB_DPTXFSIZ2_WIDTH 32
1015 #define USB_DPTXFSIZ3 HW_REGISTER_RW( 0x7e98010c )
1016 #define USB_DPTXFSIZ3_MASK 0xffffffff
1017 #define USB_DPTXFSIZ3_WIDTH 32
1018 #define USB_DPTXFSIZ4 HW_REGISTER_RW( 0x7e980110 )
1019 #define USB_DPTXFSIZ4_MASK 0xffffffff
1020 #define USB_DPTXFSIZ4_WIDTH 32
1021 #define USB_DPTXFSIZ5 HW_REGISTER_RW( 0x7e980114 )
1022 #define USB_DPTXFSIZ5_MASK 0xffffffff
1023 #define USB_DPTXFSIZ5_WIDTH 32
1024 #define USB_DPTXFSIZ6 HW_REGISTER_RW( 0x7e980118 )
1025 #define USB_DPTXFSIZ6_MASK 0xffffffff
1026 #define USB_DPTXFSIZ6_WIDTH 32
1027 #define USB_DPTXFSIZ7 HW_REGISTER_RW( 0x7e98011c )
1028 #define USB_DPTXFSIZ7_MASK 0xffffffff
1029 #define USB_DPTXFSIZ7_WIDTH 32
1030 #define USB_DPTXFSIZ8 HW_REGISTER_RW( 0x7e980120 )
1031 #define USB_DPTXFSIZ8_MASK 0xffffffff
1032 #define USB_DPTXFSIZ8_WIDTH 32
1033 #define USB_DPTXFSIZ9 HW_REGISTER_RW( 0x7e980124 )
1034 #define USB_DPTXFSIZ9_MASK 0xffffffff
1035 #define USB_DPTXFSIZ9_WIDTH 32
1036 #define USB_DPTXFSIZ10 HW_REGISTER_RW( 0x7e980128 )
1037 #define USB_DPTXFSIZ10_MASK 0xffffffff
1038 #define USB_DPTXFSIZ10_WIDTH 32
1039 #define USB_DPTXFSIZ11 HW_REGISTER_RW( 0x7e98012c )
1040 #define USB_DPTXFSIZ11_MASK 0xffffffff
1041 #define USB_DPTXFSIZ11_WIDTH 32
1042 #define USB_DPTXFSIZ12 HW_REGISTER_RW( 0x7e980130 )
1043 #define USB_DPTXFSIZ12_MASK 0xffffffff
1044 #define USB_DPTXFSIZ12_WIDTH 32
1045 #define USB_DPTXFSIZ13 HW_REGISTER_RW( 0x7e980134 )
1046 #define USB_DPTXFSIZ13_MASK 0xffffffff
1047 #define USB_DPTXFSIZ13_WIDTH 32
1048 #define USB_DPTXFSIZ14 HW_REGISTER_RW( 0x7e980138 )
1049 #define USB_DPTXFSIZ14_MASK 0xffffffff
1050 #define USB_DPTXFSIZ14_WIDTH 32
1051 #define USB_DPTXFSIZ15 HW_REGISTER_RW( 0x7e98013c )
1052 #define USB_DPTXFSIZ15_MASK 0xffffffff
1053 #define USB_DPTXFSIZ15_WIDTH 32
1054 #define USB_DIEPTXF1 HW_REGISTER_RW( 0x7e980104 )
1055 #define USB_DIEPTXF1_MASK 0xffffffff
1056 #define USB_DIEPTXF1_WIDTH 32
1057 #define USB_DIEPTXF1_FIFO_SIZE_BITS 31:16
1058 #define USB_DIEPTXF1_FIFO_SIZE_SET 0xffff0000
1059 #define USB_DIEPTXF1_FIFO_SIZE_CLR 0x0000ffff
1060 #define USB_DIEPTXF1_FIFO_SIZE_MSB 31
1061 #define USB_DIEPTXF1_FIFO_SIZE_LSB 16
1062 #define USB_DIEPTXF1_FIFO_SIZE_RESET 0x0
1063 #define USB_DIEPTXF1_FIFO_STADDR_BITS 15:0
1064 #define USB_DIEPTXF1_FIFO_STADDR_SET 0x0000ffff
1065 #define USB_DIEPTXF1_FIFO_STADDR_CLR 0xffff0000
1066 #define USB_DIEPTXF1_FIFO_STADDR_MSB 15
1067 #define USB_DIEPTXF1_FIFO_STADDR_LSB 0
1068 #define USB_DIEPTXF1_FIFO_STADDR_RESET 0x0
1069 #define USB_DIEPTXF2 HW_REGISTER_RW( 0x7e980108 )
1070 #define USB_DIEPTXF2_MASK 0xffffffff
1071 #define USB_DIEPTXF2_WIDTH 32
1072 #define USB_DIEPTXF3 HW_REGISTER_RW( 0x7e98010c )
1073 #define USB_DIEPTXF3_MASK 0xffffffff
1074 #define USB_DIEPTXF3_WIDTH 32
1075 #define USB_DIEPTXF4 HW_REGISTER_RW( 0x7e980110 )
1076 #define USB_DIEPTXF4_MASK 0xffffffff
1077 #define USB_DIEPTXF4_WIDTH 32
1078 #define USB_DIEPTXF5 HW_REGISTER_RW( 0x7e980114 )
1079 #define USB_DIEPTXF5_MASK 0xffffffff
1080 #define USB_DIEPTXF5_WIDTH 32
1081 #define USB_DIEPTXF6 HW_REGISTER_RW( 0x7e980118 )
1082 #define USB_DIEPTXF6_MASK 0xffffffff
1083 #define USB_DIEPTXF6_WIDTH 32
1084 #define USB_DIEPTXF7 HW_REGISTER_RW( 0x7e98011c )
1085 #define USB_DIEPTXF7_MASK 0xffffffff
1086 #define USB_DIEPTXF7_WIDTH 32
1087 #define USB_DIEPTXF8 HW_REGISTER_RW( 0x7e980120 )
1088 #define USB_DIEPTXF8_MASK 0xffffffff
1089 #define USB_DIEPTXF8_WIDTH 32
1090 #define USB_DIEPTXF9 HW_REGISTER_RW( 0x7e980124 )
1091 #define USB_DIEPTXF9_MASK 0xffffffff
1092 #define USB_DIEPTXF9_WIDTH 32
1093 #define USB_DIEPTXF10 HW_REGISTER_RW( 0x7e980128 )
1094 #define USB_DIEPTXF10_MASK 0xffffffff
1095 #define USB_DIEPTXF10_WIDTH 32
1096 #define USB_DIEPTXF11 HW_REGISTER_RW( 0x7e98012c )
1097 #define USB_DIEPTXF11_MASK 0xffffffff
1098 #define USB_DIEPTXF11_WIDTH 32
1099 #define USB_DIEPTXF12 HW_REGISTER_RW( 0x7e980130 )
1100 #define USB_DIEPTXF12_MASK 0xffffffff
1101 #define USB_DIEPTXF12_WIDTH 32
1102 #define USB_DIEPTXF13 HW_REGISTER_RW( 0x7e980134 )
1103 #define USB_DIEPTXF13_MASK 0xffffffff
1104 #define USB_DIEPTXF13_WIDTH 32
1105 #define USB_DIEPTXF14 HW_REGISTER_RW( 0x7e980138 )
1106 #define USB_DIEPTXF14_MASK 0xffffffff
1107 #define USB_DIEPTXF14_WIDTH 32
1108 #define USB_DIEPTXF15 HW_REGISTER_RW( 0x7e98013c )
1109 #define USB_DIEPTXF15_MASK 0xffffffff
1110 #define USB_DIEPTXF15_WIDTH 32
1111 #define USB_HCFG HW_REGISTER_RW( 0x7e980400 )
1112 #define USB_HCFG_MASK 0x00000007
1113 #define USB_HCFG_WIDTH 3
1114 #define USB_HCFG_LS_SUPP_BITS 2:2
1115 #define USB_HCFG_LS_SUPP_SET 0x00000004
1116 #define USB_HCFG_LS_SUPP_CLR 0xfffffffb
1117 #define USB_HCFG_LS_SUPP_MSB 2
1118 #define USB_HCFG_LS_SUPP_LSB 2
1119 #define USB_HCFG_LS_SUPP_RESET 0x0
1120 #define USB_HCFG_LS_PHY_CLK_SEL_BITS 1:0
1121 #define USB_HCFG_LS_PHY_CLK_SEL_SET 0x00000003
1122 #define USB_HCFG_LS_PHY_CLK_SEL_CLR 0xfffffffc
1123 #define USB_HCFG_LS_PHY_CLK_SEL_MSB 1
1124 #define USB_HCFG_LS_PHY_CLK_SEL_LSB 0
1125 #define USB_HCFG_LS_PHY_CLK_SEL_RESET 0x0
1126 #define USB_HFIR HW_REGISTER_RW( 0x7e980404 )
1127 #define USB_HFIR_MASK 0x0000ffff
1128 #define USB_HFIR_WIDTH 16
1129 #define USB_HFIR_IN_BITS 15:0
1130 #define USB_HFIR_IN_SET 0x0000ffff
1131 #define USB_HFIR_IN_CLR 0xffff0000
1132 #define USB_HFIR_IN_MSB 15
1133 #define USB_HFIR_IN_LSB 0
1134 #define USB_HFIR_IN_RESET 0x0
1135 #define USB_HFNUM HW_REGISTER_RW( 0x7e980408 )
1136 #define USB_HFNUM_MASK 0xffffffff
1137 #define USB_HFNUM_WIDTH 32
1138 #define USB_HFNUM_REM_BITS 31:16
1139 #define USB_HFNUM_REM_SET 0xffff0000
1140 #define USB_HFNUM_REM_CLR 0x0000ffff
1141 #define USB_HFNUM_REM_MSB 31
1142 #define USB_HFNUM_REM_LSB 16
1143 #define USB_HFNUM_REM_RESET 0x0
1144 #define USB_HFNUM_NUM_BITS 15:0
1145 #define USB_HFNUM_NUM_SET 0x0000ffff
1146 #define USB_HFNUM_NUM_CLR 0xffff0000
1147 #define USB_HFNUM_NUM_MSB 15
1148 #define USB_HFNUM_NUM_LSB 0
1149 #define USB_HFNUM_NUM_RESET 0x0
1150 #define USB_HPTXSTS HW_REGISTER_RW( 0x7e980410 )
1151 #define USB_HPTXSTS_MASK 0xffffffff
1152 #define USB_HPTXSTS_WIDTH 32
1153 #define USB_HPTXSTS_HPTXQTOP_BITS 31:24
1154 #define USB_HPTXSTS_HPTXQTOP_SET 0xff000000
1155 #define USB_HPTXSTS_HPTXQTOP_CLR 0x00ffffff
1156 #define USB_HPTXSTS_HPTXQTOP_MSB 31
1157 #define USB_HPTXSTS_HPTXQTOP_LSB 24
1158 #define USB_HPTXSTS_HPTXQTOP_RESET 0x0
1159 #define USB_HPTXSTS_HPTXQSPCAVAIL_BITS 23:16
1160 #define USB_HPTXSTS_HPTXQSPCAVAIL_SET 0x00ff0000
1161 #define USB_HPTXSTS_HPTXQSPCAVAIL_CLR 0xff00ffff
1162 #define USB_HPTXSTS_HPTXQSPCAVAIL_MSB 23
1163 #define USB_HPTXSTS_HPTXQSPCAVAIL_LSB 16
1164 #define USB_HPTXSTS_HPTXQSPCAVAIL_RESET 0x0
1165 #define USB_HPTXSTS_HPTXFSPCAVAIL_BITS 15:0
1166 #define USB_HPTXSTS_HPTXFSPCAVAIL_SET 0x0000ffff
1167 #define USB_HPTXSTS_HPTXFSPCAVAIL_CLR 0xffff0000
1168 #define USB_HPTXSTS_HPTXFSPCAVAIL_MSB 15
1169 #define USB_HPTXSTS_HPTXFSPCAVAIL_LSB 0
1170 #define USB_HPTXSTS_HPTXFSPCAVAIL_RESET 0x0
1171 #define USB_HAINT HW_REGISTER_RW( 0x7e980414 )
1172 #define USB_HAINT_MASK 0xffffffff
1173 #define USB_HAINT_WIDTH 32
1174 #define USB_HAINTMSK HW_REGISTER_RW( 0x7e980418 )
1175 #define USB_HAINTMSK_MASK 0xffffffff
1176 #define USB_HAINTMSK_WIDTH 32
1177 #define USB_HPRT HW_REGISTER_RW( 0x7e980440 )
1178 #define USB_HPRT_MASK 0x0007fdff
1179 #define USB_HPRT_WIDTH 19
1180 #define USB_HPRT_SPD_BITS 18:17
1181 #define USB_HPRT_SPD_SET 0x00060000
1182 #define USB_HPRT_SPD_CLR 0xfff9ffff
1183 #define USB_HPRT_SPD_MSB 18
1184 #define USB_HPRT_SPD_LSB 17
1185 #define USB_HPRT_SPD_RESET 0x0
1186 #define USB_HPRT_TST_CTL_BITS 16:13
1187 #define USB_HPRT_TST_CTL_SET 0x0001e000
1188 #define USB_HPRT_TST_CTL_CLR 0xfffe1fff
1189 #define USB_HPRT_TST_CTL_MSB 16
1190 #define USB_HPRT_TST_CTL_LSB 13
1191 #define USB_HPRT_TST_CTL_RESET 0x0
1192 #define USB_HPRT_PWR_BITS 12:12
1193 #define USB_HPRT_PWR_SET 0x00001000
1194 #define USB_HPRT_PWR_CLR 0xffffefff
1195 #define USB_HPRT_PWR_MSB 12
1196 #define USB_HPRT_PWR_LSB 12
1197 #define USB_HPRT_PWR_RESET 0x0
1198 #define USB_HPRT_LN_STS_BITS 11:10
1199 #define USB_HPRT_LN_STS_SET 0x00000c00
1200 #define USB_HPRT_LN_STS_CLR 0xfffff3ff
1201 #define USB_HPRT_LN_STS_MSB 11
1202 #define USB_HPRT_LN_STS_LSB 10
1203 #define USB_HPRT_LN_STS_RESET 0x0
1204 #define USB_HPRT_RST_BITS 8:8
1205 #define USB_HPRT_RST_SET 0x00000100
1206 #define USB_HPRT_RST_CLR 0xfffffeff
1207 #define USB_HPRT_RST_MSB 8
1208 #define USB_HPRT_RST_LSB 8
1209 #define USB_HPRT_RST_RESET 0x0
1210 #define USB_HPRT_SUSP_BITS 7:7
1211 #define USB_HPRT_SUSP_SET 0x00000080
1212 #define USB_HPRT_SUSP_CLR 0xffffff7f
1213 #define USB_HPRT_SUSP_MSB 7
1214 #define USB_HPRT_SUSP_LSB 7
1215 #define USB_HPRT_SUSP_RESET 0x0
1216 #define USB_HPRT_RES_BITS 6:6
1217 #define USB_HPRT_RES_SET 0x00000040
1218 #define USB_HPRT_RES_CLR 0xffffffbf
1219 #define USB_HPRT_RES_MSB 6
1220 #define USB_HPRT_RES_LSB 6
1221 #define USB_HPRT_RES_RESET 0x0
1222 #define USB_HPRT_OVR_CURR_CHNG_BITS 5:5
1223 #define USB_HPRT_OVR_CURR_CHNG_SET 0x00000020
1224 #define USB_HPRT_OVR_CURR_CHNG_CLR 0xffffffdf
1225 #define USB_HPRT_OVR_CURR_CHNG_MSB 5
1226 #define USB_HPRT_OVR_CURR_CHNG_LSB 5
1227 #define USB_HPRT_OVR_CURR_CHNG_RESET 0x0
1228 #define USB_HPRT_OVR_CURR_ACT_BITS 4:4
1229 #define USB_HPRT_OVR_CURR_ACT_SET 0x00000010
1230 #define USB_HPRT_OVR_CURR_ACT_CLR 0xffffffef
1231 #define USB_HPRT_OVR_CURR_ACT_MSB 4
1232 #define USB_HPRT_OVR_CURR_ACT_LSB 4
1233 #define USB_HPRT_OVR_CURR_ACT_RESET 0x0
1234 #define USB_HPRT_EN_CHNG_BITS 3:3
1235 #define USB_HPRT_EN_CHNG_SET 0x00000008
1236 #define USB_HPRT_EN_CHNG_CLR 0xfffffff7
1237 #define USB_HPRT_EN_CHNG_MSB 3
1238 #define USB_HPRT_EN_CHNG_LSB 3
1239 #define USB_HPRT_EN_CHNG_RESET 0x0
1240 #define USB_HPRT_ENA_BITS 2:2
1241 #define USB_HPRT_ENA_SET 0x00000004
1242 #define USB_HPRT_ENA_CLR 0xfffffffb
1243 #define USB_HPRT_ENA_MSB 2
1244 #define USB_HPRT_ENA_LSB 2
1245 #define USB_HPRT_ENA_RESET 0x0
1246 #define USB_HPRT_CONN_DET_BITS 1:1
1247 #define USB_HPRT_CONN_DET_SET 0x00000002
1248 #define USB_HPRT_CONN_DET_CLR 0xfffffffd
1249 #define USB_HPRT_CONN_DET_MSB 1
1250 #define USB_HPRT_CONN_DET_LSB 1
1251 #define USB_HPRT_CONN_DET_RESET 0x0
1252 #define USB_HPRT_CONN_STS_BITS 0:0
1253 #define USB_HPRT_CONN_STS_SET 0x00000001
1254 #define USB_HPRT_CONN_STS_CLR 0xfffffffe
1255 #define USB_HPRT_CONN_STS_MSB 0
1256 #define USB_HPRT_CONN_STS_LSB 0
1257 #define USB_HPRT_CONN_STS_RESET 0x0
1258 #define USB_HCCHAR0 HW_REGISTER_RW( 0x7e980500 )
1259 #define USB_HCCHAR0_MASK 0xffffffff
1260 #define USB_HCCHAR0_WIDTH 32
1261 #define USB_HCCHAR0_CH_ENA_BITS 31:31
1262 #define USB_HCCHAR0_CH_ENA_SET 0x80000000
1263 #define USB_HCCHAR0_CH_ENA_CLR 0x7fffffff
1264 #define USB_HCCHAR0_CH_ENA_MSB 31
1265 #define USB_HCCHAR0_CH_ENA_LSB 31
1266 #define USB_HCCHAR0_CH_ENA_RESET 0x0
1267 #define USB_HCCHAR0_CH_DIS_BITS 30:30
1268 #define USB_HCCHAR0_CH_DIS_SET 0x40000000
1269 #define USB_HCCHAR0_CH_DIS_CLR 0xbfffffff
1270 #define USB_HCCHAR0_CH_DIS_MSB 30
1271 #define USB_HCCHAR0_CH_DIS_LSB 30
1272 #define USB_HCCHAR0_CH_DIS_RESET 0x0
1273 #define USB_HCCHAR0_ODD_FRM_BITS 29:29
1274 #define USB_HCCHAR0_ODD_FRM_SET 0x20000000
1275 #define USB_HCCHAR0_ODD_FRM_CLR 0xdfffffff
1276 #define USB_HCCHAR0_ODD_FRM_MSB 29
1277 #define USB_HCCHAR0_ODD_FRM_LSB 29
1278 #define USB_HCCHAR0_ODD_FRM_RESET 0x0
1279 #define USB_HCCHAR0_DEV_ADDR_BITS 28:22
1280 #define USB_HCCHAR0_DEV_ADDR_SET 0x1fc00000
1281 #define USB_HCCHAR0_DEV_ADDR_CLR 0xe03fffff
1282 #define USB_HCCHAR0_DEV_ADDR_MSB 28
1283 #define USB_HCCHAR0_DEV_ADDR_LSB 22
1284 #define USB_HCCHAR0_DEV_ADDR_RESET 0x0
1285 #define USB_HCCHAR0_MC_EC_BITS 21:20
1286 #define USB_HCCHAR0_MC_EC_SET 0x00300000
1287 #define USB_HCCHAR0_MC_EC_CLR 0xffcfffff
1288 #define USB_HCCHAR0_MC_EC_MSB 21
1289 #define USB_HCCHAR0_MC_EC_LSB 20
1290 #define USB_HCCHAR0_MC_EC_RESET 0x0
1291 #define USB_HCCHAR0_EP_TYPE_BITS 19:18
1292 #define USB_HCCHAR0_EP_TYPE_SET 0x000c0000
1293 #define USB_HCCHAR0_EP_TYPE_CLR 0xfff3ffff
1294 #define USB_HCCHAR0_EP_TYPE_MSB 19
1295 #define USB_HCCHAR0_EP_TYPE_LSB 18
1296 #define USB_HCCHAR0_EP_TYPE_RESET 0x0
1297 #define USB_HCCHAR0_LSPD_DEV_BITS 17:17
1298 #define USB_HCCHAR0_LSPD_DEV_SET 0x00020000
1299 #define USB_HCCHAR0_LSPD_DEV_CLR 0xfffdffff
1300 #define USB_HCCHAR0_LSPD_DEV_MSB 17
1301 #define USB_HCCHAR0_LSPD_DEV_LSB 17
1302 #define USB_HCCHAR0_LSPD_DEV_RESET 0x0
1303 #define USB_HCCHAR0_EP_DIR_BITS 15:15
1304 #define USB_HCCHAR0_EP_DIR_SET 0x00008000
1305 #define USB_HCCHAR0_EP_DIR_CLR 0xffff7fff
1306 #define USB_HCCHAR0_EP_DIR_MSB 15
1307 #define USB_HCCHAR0_EP_DIR_LSB 15
1308 #define USB_HCCHAR0_EP_DIR_RESET 0x0
1309 #define USB_HCCHAR0_EP_NUM_BITS 14:11
1310 #define USB_HCCHAR0_EP_NUM_SET 0x00007800
1311 #define USB_HCCHAR0_EP_NUM_CLR 0xffff87ff
1312 #define USB_HCCHAR0_EP_NUM_MSB 14
1313 #define USB_HCCHAR0_EP_NUM_LSB 11
1314 #define USB_HCCHAR0_EP_NUM_RESET 0x0
1315 #define USB_HCCHAR0_MPS_BITS 10:0
1316 #define USB_HCCHAR0_MPS_SET 0x000007ff
1317 #define USB_HCCHAR0_MPS_CLR 0xfffff800
1318 #define USB_HCCHAR0_MPS_MSB 10
1319 #define USB_HCCHAR0_MPS_LSB 0
1320 #define USB_HCCHAR0_MPS_RESET 0x0
1321 #define USB_HCSPLT0 HW_REGISTER_RW( 0x7e980504 )
1322 #define USB_HCSPLT0_MASK 0xffffffff
1323 #define USB_HCSPLT0_WIDTH 32
1324 #define USB_HCSPLT0_SPLT_ENA_BITS 31:31
1325 #define USB_HCSPLT0_SPLT_ENA_SET 0x80000000
1326 #define USB_HCSPLT0_SPLT_ENA_CLR 0x7fffffff
1327 #define USB_HCSPLT0_SPLT_ENA_MSB 31
1328 #define USB_HCSPLT0_SPLT_ENA_LSB 31
1329 #define USB_HCSPLT0_SPLT_ENA_RESET 0x0
1330 #define USB_HCSPLT0_COMP_SPLT_BITS 16:16
1331 #define USB_HCSPLT0_COMP_SPLT_SET 0x00010000
1332 #define USB_HCSPLT0_COMP_SPLT_CLR 0xfffeffff
1333 #define USB_HCSPLT0_COMP_SPLT_MSB 16
1334 #define USB_HCSPLT0_COMP_SPLT_LSB 16
1335 #define USB_HCSPLT0_COMP_SPLT_RESET 0x0
1336 #define USB_HCSPLT0_XACT_POS_BITS 15:14
1337 #define USB_HCSPLT0_XACT_POS_SET 0x0000c000
1338 #define USB_HCSPLT0_XACT_POS_CLR 0xffff3fff
1339 #define USB_HCSPLT0_XACT_POS_MSB 15
1340 #define USB_HCSPLT0_XACT_POS_LSB 14
1341 #define USB_HCSPLT0_XACT_POS_RESET 0x0
1342 #define USB_HCSPLT0_HUB_ADDR_BITS 13:7
1343 #define USB_HCSPLT0_HUB_ADDR_SET 0x00003f80
1344 #define USB_HCSPLT0_HUB_ADDR_CLR 0xffffc07f
1345 #define USB_HCSPLT0_HUB_ADDR_MSB 13
1346 #define USB_HCSPLT0_HUB_ADDR_LSB 7
1347 #define USB_HCSPLT0_HUB_ADDR_RESET 0x0
1348 #define USB_HCSPLT0_PRT_ADDR_BITS 6:0
1349 #define USB_HCSPLT0_PRT_ADDR_SET 0x0000007f
1350 #define USB_HCSPLT0_PRT_ADDR_CLR 0xffffff80
1351 #define USB_HCSPLT0_PRT_ADDR_MSB 6
1352 #define USB_HCSPLT0_PRT_ADDR_LSB 0
1353 #define USB_HCSPLT0_PRT_ADDR_RESET 0x0
1354 #define USB_HCINT0 HW_REGISTER_RW( 0x7e980508 )
1355 #define USB_HCINT0_MASK 0xffffffff
1356 #define USB_HCINT0_WIDTH 32
1357 #define USB_HCINT0_DATA_TGL_ERR_BITS 10:10
1358 #define USB_HCINT0_DATA_TGL_ERR_SET 0x00000400
1359 #define USB_HCINT0_DATA_TGL_ERR_CLR 0xfffffbff
1360 #define USB_HCINT0_DATA_TGL_ERR_MSB 10
1361 #define USB_HCINT0_DATA_TGL_ERR_LSB 10
1362 #define USB_HCINT0_DATA_TGL_ERR_RESET 0x0
1363 #define USB_HCINT0_FRM_OVRUN_BITS 9:9
1364 #define USB_HCINT0_FRM_OVRUN_SET 0x00000200
1365 #define USB_HCINT0_FRM_OVRUN_CLR 0xfffffdff
1366 #define USB_HCINT0_FRM_OVRUN_MSB 9
1367 #define USB_HCINT0_FRM_OVRUN_LSB 9
1368 #define USB_HCINT0_FRM_OVRUN_RESET 0x0
1369 #define USB_HCINT0_BBL_ERR_BITS 8:8
1370 #define USB_HCINT0_BBL_ERR_SET 0x00000100
1371 #define USB_HCINT0_BBL_ERR_CLR 0xfffffeff
1372 #define USB_HCINT0_BBL_ERR_MSB 8
1373 #define USB_HCINT0_BBL_ERR_LSB 8
1374 #define USB_HCINT0_BBL_ERR_RESET 0x0
1375 #define USB_HCINT0_XACT_ERR_BITS 7:7
1376 #define USB_HCINT0_XACT_ERR_SET 0x00000080
1377 #define USB_HCINT0_XACT_ERR_CLR 0xffffff7f
1378 #define USB_HCINT0_XACT_ERR_MSB 7
1379 #define USB_HCINT0_XACT_ERR_LSB 7
1380 #define USB_HCINT0_XACT_ERR_RESET 0x0
1381 #define USB_HCINT0_NYET_BITS 6:6
1382 #define USB_HCINT0_NYET_SET 0x00000040
1383 #define USB_HCINT0_NYET_CLR 0xffffffbf
1384 #define USB_HCINT0_NYET_MSB 6
1385 #define USB_HCINT0_NYET_LSB 6
1386 #define USB_HCINT0_NYET_RESET 0x0
1387 #define USB_HCINT0_ACK_BITS 5:5
1388 #define USB_HCINT0_ACK_SET 0x00000020
1389 #define USB_HCINT0_ACK_CLR 0xffffffdf
1390 #define USB_HCINT0_ACK_MSB 5
1391 #define USB_HCINT0_ACK_LSB 5
1392 #define USB_HCINT0_ACK_RESET 0x0
1393 #define USB_HCINT0_NAK_BITS 4:4
1394 #define USB_HCINT0_NAK_SET 0x00000010
1395 #define USB_HCINT0_NAK_CLR 0xffffffef
1396 #define USB_HCINT0_NAK_MSB 4
1397 #define USB_HCINT0_NAK_LSB 4
1398 #define USB_HCINT0_NAK_RESET 0x0
1399 #define USB_HCINT0_STALL_BITS 3:3
1400 #define USB_HCINT0_STALL_SET 0x00000008
1401 #define USB_HCINT0_STALL_CLR 0xfffffff7
1402 #define USB_HCINT0_STALL_MSB 3
1403 #define USB_HCINT0_STALL_LSB 3
1404 #define USB_HCINT0_STALL_RESET 0x0
1405 #define USB_HCINT0_AHB_ERR_BITS 2:2
1406 #define USB_HCINT0_AHB_ERR_SET 0x00000004
1407 #define USB_HCINT0_AHB_ERR_CLR 0xfffffffb
1408 #define USB_HCINT0_AHB_ERR_MSB 2
1409 #define USB_HCINT0_AHB_ERR_LSB 2
1410 #define USB_HCINT0_AHB_ERR_RESET 0x0
1411 #define USB_HCINT0_CH_HLTD_BITS 1:1
1412 #define USB_HCINT0_CH_HLTD_SET 0x00000002
1413 #define USB_HCINT0_CH_HLTD_CLR 0xfffffffd
1414 #define USB_HCINT0_CH_HLTD_MSB 1
1415 #define USB_HCINT0_CH_HLTD_LSB 1
1416 #define USB_HCINT0_CH_HLTD_RESET 0x0
1417 #define USB_HCINT0_XFER_COMPL_BITS 0:0
1418 #define USB_HCINT0_XFER_COMPL_SET 0x00000001
1419 #define USB_HCINT0_XFER_COMPL_CLR 0xfffffffe
1420 #define USB_HCINT0_XFER_COMPL_MSB 0
1421 #define USB_HCINT0_XFER_COMPL_LSB 0
1422 #define USB_HCINT0_XFER_COMPL_RESET 0x0
1423 #define USB_HCINTMSK0 HW_REGISTER_RW( 0x7e98050c )
1424 #define USB_HCINTMSK0_MASK 0xffffffff
1425 #define USB_HCINTMSK0_WIDTH 32
1426 #define USB_HCTSIZ0 HW_REGISTER_RW( 0x7e980510 )
1427 #define USB_HCTSIZ0_MASK 0xffffffff
1428 #define USB_HCTSIZ0_WIDTH 32
1429 #define USB_HCTSIZ0_DO_PNG_BITS 31:31
1430 #define USB_HCTSIZ0_DO_PNG_SET 0x80000000
1431 #define USB_HCTSIZ0_DO_PNG_CLR 0x7fffffff
1432 #define USB_HCTSIZ0_DO_PNG_MSB 31
1433 #define USB_HCTSIZ0_DO_PNG_LSB 31
1434 #define USB_HCTSIZ0_DO_PNG_RESET 0x0
1435 #define USB_HCTSIZ0_PID_BITS 30:29
1436 #define USB_HCTSIZ0_PID_SET 0x60000000
1437 #define USB_HCTSIZ0_PID_CLR 0x9fffffff
1438 #define USB_HCTSIZ0_PID_MSB 30
1439 #define USB_HCTSIZ0_PID_LSB 29
1440 #define USB_HCTSIZ0_PID_RESET 0x0
1441 #define USB_HCTSIZ0_PKT_CNT_BITS 28:19
1442 #define USB_HCTSIZ0_PKT_CNT_SET 0x1ff80000
1443 #define USB_HCTSIZ0_PKT_CNT_CLR 0xe007ffff
1444 #define USB_HCTSIZ0_PKT_CNT_MSB 28
1445 #define USB_HCTSIZ0_PKT_CNT_LSB 19
1446 #define USB_HCTSIZ0_PKT_CNT_RESET 0x0
1447 #define USB_HCTSIZ0_XFER_SIZE_BITS 18:0
1448 #define USB_HCTSIZ0_XFER_SIZE_SET 0x0007ffff
1449 #define USB_HCTSIZ0_XFER_SIZE_CLR 0xfff80000
1450 #define USB_HCTSIZ0_XFER_SIZE_MSB 18
1451 #define USB_HCTSIZ0_XFER_SIZE_LSB 0
1452 #define USB_HCTSIZ0_XFER_SIZE_RESET 0x0
1453 #define USB_HCDMA0 HW_REGISTER_RW( 0x7e980514 )
1454 #define USB_HCDMA0_MASK 0xffffffff
1455 #define USB_HCDMA0_WIDTH 32
1456 #define USB_HCCHAR1 HW_REGISTER_RW( 0x7e980520 )
1457 #define USB_HCCHAR1_MASK 0xffffffff
1458 #define USB_HCCHAR1_WIDTH 32
1459 #define USB_HCSPLT1 HW_REGISTER_RW( 0x7e980524 )
1460 #define USB_HCSPLT1_MASK 0xffffffff
1461 #define USB_HCSPLT1_WIDTH 32
1462 #define USB_HCINT1 HW_REGISTER_RW( 0x7e980528 )
1463 #define USB_HCINT1_MASK 0xffffffff
1464 #define USB_HCINT1_WIDTH 32
1465 #define USB_HCINTMSK1 HW_REGISTER_RW( 0x7e98052c )
1466 #define USB_HCINTMSK1_MASK 0xffffffff
1467 #define USB_HCINTMSK1_WIDTH 32
1468 #define USB_HCTSIZ1 HW_REGISTER_RW( 0x7e980530 )
1469 #define USB_HCTSIZ1_MASK 0xffffffff
1470 #define USB_HCTSIZ1_WIDTH 32
1471 #define USB_HCDMA1 HW_REGISTER_RW( 0x7e980534 )
1472 #define USB_HCDMA1_MASK 0xffffffff
1473 #define USB_HCDMA1_WIDTH 32
1474 #define USB_HCCHAR2 HW_REGISTER_RW( 0x7e980540 )
1475 #define USB_HCCHAR2_MASK 0xffffffff
1476 #define USB_HCCHAR2_WIDTH 32
1477 #define USB_HCSPLT2 HW_REGISTER_RW( 0x7e980544 )
1478 #define USB_HCSPLT2_MASK 0xffffffff
1479 #define USB_HCSPLT2_WIDTH 32
1480 #define USB_HCINT2 HW_REGISTER_RW( 0x7e980548 )
1481 #define USB_HCINT2_MASK 0xffffffff
1482 #define USB_HCINT2_WIDTH 32
1483 #define USB_HCINTMSK2 HW_REGISTER_RW( 0x7e98054c )
1484 #define USB_HCINTMSK2_MASK 0xffffffff
1485 #define USB_HCINTMSK2_WIDTH 32
1486 #define USB_HCTSIZ2 HW_REGISTER_RW( 0x7e980550 )
1487 #define USB_HCTSIZ2_MASK 0xffffffff
1488 #define USB_HCTSIZ2_WIDTH 32
1489 #define USB_HCDMA2 HW_REGISTER_RW( 0x7e980554 )
1490 #define USB_HCDMA2_MASK 0xffffffff
1491 #define USB_HCDMA2_WIDTH 32
1492 #define USB_HCCHAR3 HW_REGISTER_RW( 0x7e980560 )
1493 #define USB_HCCHAR3_MASK 0xffffffff
1494 #define USB_HCCHAR3_WIDTH 32
1495 #define USB_HCSPLT3 HW_REGISTER_RW( 0x7e980564 )
1496 #define USB_HCSPLT3_MASK 0xffffffff
1497 #define USB_HCSPLT3_WIDTH 32
1498 #define USB_HCINT3 HW_REGISTER_RW( 0x7e980568 )
1499 #define USB_HCINT3_MASK 0xffffffff
1500 #define USB_HCINT3_WIDTH 32
1501 #define USB_HCINTMSK3 HW_REGISTER_RW( 0x7e98056c )
1502 #define USB_HCINTMSK3_MASK 0xffffffff
1503 #define USB_HCINTMSK3_WIDTH 32
1504 #define USB_HCTSIZ3 HW_REGISTER_RW( 0x7e980570 )
1505 #define USB_HCTSIZ3_MASK 0xffffffff
1506 #define USB_HCTSIZ3_WIDTH 32
1507 #define USB_HCDMA3 HW_REGISTER_RW( 0x7e980574 )
1508 #define USB_HCDMA3_MASK 0xffffffff
1509 #define USB_HCDMA3_WIDTH 32
1510 #define USB_HCCHAR4 HW_REGISTER_RW( 0x7e980580 )
1511 #define USB_HCCHAR4_MASK 0xffffffff
1512 #define USB_HCCHAR4_WIDTH 32
1513 #define USB_HCSPLT4 HW_REGISTER_RW( 0x7e980584 )
1514 #define USB_HCSPLT4_MASK 0xffffffff
1515 #define USB_HCSPLT4_WIDTH 32
1516 #define USB_HCINT4 HW_REGISTER_RW( 0x7e980588 )
1517 #define USB_HCINT4_MASK 0xffffffff
1518 #define USB_HCINT4_WIDTH 32
1519 #define USB_HCINTMSK4 HW_REGISTER_RW( 0x7e98058c )
1520 #define USB_HCINTMSK4_MASK 0xffffffff
1521 #define USB_HCINTMSK4_WIDTH 32
1522 #define USB_HCTSIZ4 HW_REGISTER_RW( 0x7e980590 )
1523 #define USB_HCTSIZ4_MASK 0xffffffff
1524 #define USB_HCTSIZ4_WIDTH 32
1525 #define USB_HCDMA4 HW_REGISTER_RW( 0x7e980594 )
1526 #define USB_HCDMA4_MASK 0xffffffff
1527 #define USB_HCDMA4_WIDTH 32
1528 #define USB_HCCHAR5 HW_REGISTER_RW( 0x7e9805a0 )
1529 #define USB_HCCHAR5_MASK 0xffffffff
1530 #define USB_HCCHAR5_WIDTH 32
1531 #define USB_HCSPLT5 HW_REGISTER_RW( 0x7e9805a4 )
1532 #define USB_HCSPLT5_MASK 0xffffffff
1533 #define USB_HCSPLT5_WIDTH 32
1534 #define USB_HCINT5 HW_REGISTER_RW( 0x7e9805a8 )
1535 #define USB_HCINT5_MASK 0xffffffff
1536 #define USB_HCINT5_WIDTH 32
1537 #define USB_HCINTMSK5 HW_REGISTER_RW( 0x7e9805ac )
1538 #define USB_HCINTMSK5_MASK 0xffffffff
1539 #define USB_HCINTMSK5_WIDTH 32
1540 #define USB_HCTSIZ5 HW_REGISTER_RW( 0x7e9805b0 )
1541 #define USB_HCTSIZ5_MASK 0xffffffff
1542 #define USB_HCTSIZ5_WIDTH 32
1543 #define USB_HCDMA5 HW_REGISTER_RW( 0x7e9805b4 )
1544 #define USB_HCDMA5_MASK 0xffffffff
1545 #define USB_HCDMA5_WIDTH 32
1546 #define USB_HCCHAR6 HW_REGISTER_RW( 0x7e9805c0 )
1547 #define USB_HCCHAR6_MASK 0xffffffff
1548 #define USB_HCCHAR6_WIDTH 32
1549 #define USB_HCSPLT6 HW_REGISTER_RW( 0x7e9805c4 )
1550 #define USB_HCSPLT6_MASK 0xffffffff
1551 #define USB_HCSPLT6_WIDTH 32
1552 #define USB_HCINT6 HW_REGISTER_RW( 0x7e9805c8 )
1553 #define USB_HCINT6_MASK 0xffffffff
1554 #define USB_HCINT6_WIDTH 32
1555 #define USB_HCINTMSK6 HW_REGISTER_RW( 0x7e9805cc )
1556 #define USB_HCINTMSK6_MASK 0xffffffff
1557 #define USB_HCINTMSK6_WIDTH 32
1558 #define USB_HCTSIZ6 HW_REGISTER_RW( 0x7e9805d0 )
1559 #define USB_HCTSIZ6_MASK 0xffffffff
1560 #define USB_HCTSIZ6_WIDTH 32
1561 #define USB_HCDMA6 HW_REGISTER_RW( 0x7e9805d4 )
1562 #define USB_HCDMA6_MASK 0xffffffff
1563 #define USB_HCDMA6_WIDTH 32
1564 #define USB_HCCHAR7 HW_REGISTER_RW( 0x7e9805e0 )
1565 #define USB_HCCHAR7_MASK 0xffffffff
1566 #define USB_HCCHAR7_WIDTH 32
1567 #define USB_HCSPLT7 HW_REGISTER_RW( 0x7e9805e4 )
1568 #define USB_HCSPLT7_MASK 0xffffffff
1569 #define USB_HCSPLT7_WIDTH 32
1570 #define USB_HCINT7 HW_REGISTER_RW( 0x7e9805e8 )
1571 #define USB_HCINT7_MASK 0xffffffff
1572 #define USB_HCINT7_WIDTH 32
1573 #define USB_HCINTMSK7 HW_REGISTER_RW( 0x7e9805ec )
1574 #define USB_HCINTMSK7_MASK 0xffffffff
1575 #define USB_HCINTMSK7_WIDTH 32
1576 #define USB_HCTSIZ7 HW_REGISTER_RW( 0x7e9805f0 )
1577 #define USB_HCTSIZ7_MASK 0xffffffff
1578 #define USB_HCTSIZ7_WIDTH 32
1579 #define USB_HCDMA7 HW_REGISTER_RW( 0x7e9805f4 )
1580 #define USB_HCDMA7_MASK 0xffffffff
1581 #define USB_HCDMA7_WIDTH 32
1582 #define USB_DCFG HW_REGISTER_RW( 0x7e980800 )
1583 #define USB_DCFG_MASK 0x03fc1ff7
1584 #define USB_DCFG_WIDTH 26
1585 #define USB_DCFG_PER_SCH_INTV_BITS 25:24
1586 #define USB_DCFG_PER_SCH_INTV_SET 0x03000000
1587 #define USB_DCFG_PER_SCH_INTV_CLR 0xfcffffff
1588 #define USB_DCFG_PER_SCH_INTV_MSB 25
1589 #define USB_DCFG_PER_SCH_INTV_LSB 24
1590 #define USB_DCFG_PER_SCH_INTV_RESET 0x0
1591 #define USB_DCFG_DESC_DMA_BITS 23:23
1592 #define USB_DCFG_DESC_DMA_SET 0x00800000
1593 #define USB_DCFG_DESC_DMA_CLR 0xff7fffff
1594 #define USB_DCFG_DESC_DMA_MSB 23
1595 #define USB_DCFG_DESC_DMA_LSB 23
1596 #define USB_DCFG_DESC_DMA_RESET 0x0
1597 #define USB_DCFG_EP_MIS_CNT_BITS 22:18
1598 #define USB_DCFG_EP_MIS_CNT_SET 0x007c0000
1599 #define USB_DCFG_EP_MIS_CNT_CLR 0xff83ffff
1600 #define USB_DCFG_EP_MIS_CNT_MSB 22
1601 #define USB_DCFG_EP_MIS_CNT_LSB 18
1602 #define USB_DCFG_EP_MIS_CNT_RESET 0x0
1603 #define USB_DCFG_PER_FR_INT_BITS 12:11
1604 #define USB_DCFG_PER_FR_INT_SET 0x00001800
1605 #define USB_DCFG_PER_FR_INT_CLR 0xffffe7ff
1606 #define USB_DCFG_PER_FR_INT_MSB 12
1607 #define USB_DCFG_PER_FR_INT_LSB 11
1608 #define USB_DCFG_PER_FR_INT_RESET 0x0
1609 #define USB_DCFG_DEV_ADDR_BITS 10:4
1610 #define USB_DCFG_DEV_ADDR_SET 0x000007f0
1611 #define USB_DCFG_DEV_ADDR_CLR 0xfffff80f
1612 #define USB_DCFG_DEV_ADDR_MSB 10
1613 #define USB_DCFG_DEV_ADDR_LSB 4
1614 #define USB_DCFG_DEV_ADDR_RESET 0x0
1615 #define USB_DCFG_NZ_STS_OUT_HSHK_BITS 2:2
1616 #define USB_DCFG_NZ_STS_OUT_HSHK_SET 0x00000004
1617 #define USB_DCFG_NZ_STS_OUT_HSHK_CLR 0xfffffffb
1618 #define USB_DCFG_NZ_STS_OUT_HSHK_MSB 2
1619 #define USB_DCFG_NZ_STS_OUT_HSHK_LSB 2
1620 #define USB_DCFG_NZ_STS_OUT_HSHK_RESET 0x0
1621 #define USB_DCFG_DEV_SPD_BITS 1:0
1622 #define USB_DCFG_DEV_SPD_SET 0x00000003
1623 #define USB_DCFG_DEV_SPD_CLR 0xfffffffc
1624 #define USB_DCFG_DEV_SPD_MSB 1
1625 #define USB_DCFG_DEV_SPD_LSB 0
1626 #define USB_DCFG_DEV_SPD_RESET 0x0
1627 #define USB_DCTL HW_REGISTER_RW( 0x7e980804 )
1628 #define USB_DCTL_MASK 0x0000efff
1629 #define USB_DCTL_WIDTH 16
1630 #define USB_DCTL_IGN_FRM_NUM_BITS 15:15
1631 #define USB_DCTL_IGN_FRM_NUM_SET 0x00008000
1632 #define USB_DCTL_IGN_FRM_NUM_CLR 0xffff7fff
1633 #define USB_DCTL_IGN_FRM_NUM_MSB 15
1634 #define USB_DCTL_IGN_FRM_NUM_LSB 15
1635 #define USB_DCTL_IGN_FRM_NUM_RESET 0x0
1636 #define USB_DCTL_GMC_BITS 14:13
1637 #define USB_DCTL_GMC_SET 0x00006000
1638 #define USB_DCTL_GMC_CLR 0xffff9fff
1639 #define USB_DCTL_GMC_MSB 14
1640 #define USB_DCTL_GMC_LSB 13
1641 #define USB_DCTL_GMC_RESET 0x0
1642 #define USB_DCTL_PWRON_PRG_DONE_BITS 11:11
1643 #define USB_DCTL_PWRON_PRG_DONE_SET 0x00000800
1644 #define USB_DCTL_PWRON_PRG_DONE_CLR 0xfffff7ff
1645 #define USB_DCTL_PWRON_PRG_DONE_MSB 11
1646 #define USB_DCTL_PWRON_PRG_DONE_LSB 11
1647 #define USB_DCTL_PWRON_PRG_DONE_RESET 0x0
1648 #define USB_DCTL_CGOUT_NAK_BITS 10:10
1649 #define USB_DCTL_CGOUT_NAK_SET 0x00000400
1650 #define USB_DCTL_CGOUT_NAK_CLR 0xfffffbff
1651 #define USB_DCTL_CGOUT_NAK_MSB 10
1652 #define USB_DCTL_CGOUT_NAK_LSB 10
1653 #define USB_DCTL_CGOUT_NAK_RESET 0x0
1654 #define USB_DCTL_SGOUT_NAK_BITS 9:9
1655 #define USB_DCTL_SGOUT_NAK_SET 0x00000200
1656 #define USB_DCTL_SGOUT_NAK_CLR 0xfffffdff
1657 #define USB_DCTL_SGOUT_NAK_MSB 9
1658 #define USB_DCTL_SGOUT_NAK_LSB 9
1659 #define USB_DCTL_SGOUT_NAK_RESET 0x0
1660 #define USB_DCTL_CGNP_IN_NAK_BITS 8:8
1661 #define USB_DCTL_CGNP_IN_NAK_SET 0x00000100
1662 #define USB_DCTL_CGNP_IN_NAK_CLR 0xfffffeff
1663 #define USB_DCTL_CGNP_IN_NAK_MSB 8
1664 #define USB_DCTL_CGNP_IN_NAK_LSB 8
1665 #define USB_DCTL_CGNP_IN_NAK_RESET 0x0
1666 #define USB_DCTL_SGNP_IN_NAK_BITS 7:7
1667 #define USB_DCTL_SGNP_IN_NAK_SET 0x00000080
1668 #define USB_DCTL_SGNP_IN_NAK_CLR 0xffffff7f
1669 #define USB_DCTL_SGNP_IN_NAK_MSB 7
1670 #define USB_DCTL_SGNP_IN_NAK_LSB 7
1671 #define USB_DCTL_SGNP_IN_NAK_RESET 0x0
1672 #define USB_DCTL_TST_CTL_BITS 6:4
1673 #define USB_DCTL_TST_CTL_SET 0x00000070
1674 #define USB_DCTL_TST_CTL_CLR 0xffffff8f
1675 #define USB_DCTL_TST_CTL_MSB 6
1676 #define USB_DCTL_TST_CTL_LSB 4
1677 #define USB_DCTL_TST_CTL_RESET 0x0
1678 #define USB_DCTL_GOUT_NAK_STS_BITS 3:3
1679 #define USB_DCTL_GOUT_NAK_STS_SET 0x00000008
1680 #define USB_DCTL_GOUT_NAK_STS_CLR 0xfffffff7
1681 #define USB_DCTL_GOUT_NAK_STS_MSB 3
1682 #define USB_DCTL_GOUT_NAK_STS_LSB 3
1683 #define USB_DCTL_GOUT_NAK_STS_RESET 0x0
1684 #define USB_DCTL_GNP_IN_NAK_STS_BITS 2:2
1685 #define USB_DCTL_GNP_IN_NAK_STS_SET 0x00000004
1686 #define USB_DCTL_GNP_IN_NAK_STS_CLR 0xfffffffb
1687 #define USB_DCTL_GNP_IN_NAK_STS_MSB 2
1688 #define USB_DCTL_GNP_IN_NAK_STS_LSB 2
1689 #define USB_DCTL_GNP_IN_NAK_STS_RESET 0x0
1690 #define USB_DCTL_SFT_DISCON_BITS 1:1
1691 #define USB_DCTL_SFT_DISCON_SET 0x00000002
1692 #define USB_DCTL_SFT_DISCON_CLR 0xfffffffd
1693 #define USB_DCTL_SFT_DISCON_MSB 1
1694 #define USB_DCTL_SFT_DISCON_LSB 1
1695 #define USB_DCTL_SFT_DISCON_RESET 0x0
1696 #define USB_DCTL_RMT_WKUP_SIG_BITS 0:0
1697 #define USB_DCTL_RMT_WKUP_SIG_SET 0x00000001
1698 #define USB_DCTL_RMT_WKUP_SIG_CLR 0xfffffffe
1699 #define USB_DCTL_RMT_WKUP_SIG_MSB 0
1700 #define USB_DCTL_RMT_WKUP_SIG_LSB 0
1701 #define USB_DCTL_RMT_WKUP_SIG_RESET 0x0
1702 #define USB_DSTS HW_REGISTER_RW( 0x7e980808 )
1703 #define USB_DSTS_MASK 0x003fff0f
1704 #define USB_DSTS_WIDTH 22
1705 #define USB_DSTS_SOF_FN_BITS 21:8
1706 #define USB_DSTS_SOF_FN_SET 0x003fff00
1707 #define USB_DSTS_SOF_FN_CLR 0xffc000ff
1708 #define USB_DSTS_SOF_FN_MSB 21
1709 #define USB_DSTS_SOF_FN_LSB 8
1710 #define USB_DSTS_SOF_FN_RESET 0x0
1711 #define USB_DSTS_ERRTIC_ERR_BITS 3:3
1712 #define USB_DSTS_ERRTIC_ERR_SET 0x00000008
1713 #define USB_DSTS_ERRTIC_ERR_CLR 0xfffffff7
1714 #define USB_DSTS_ERRTIC_ERR_MSB 3
1715 #define USB_DSTS_ERRTIC_ERR_LSB 3
1716 #define USB_DSTS_ERRTIC_ERR_RESET 0x0
1717 #define USB_DSTS_ENUM_SPD_BITS 2:1
1718 #define USB_DSTS_ENUM_SPD_SET 0x00000006
1719 #define USB_DSTS_ENUM_SPD_CLR 0xfffffff9
1720 #define USB_DSTS_ENUM_SPD_MSB 2
1721 #define USB_DSTS_ENUM_SPD_LSB 1
1722 #define USB_DSTS_ENUM_SPD_RESET 0x0
1723 #define USB_DSTS_SUSP_STS_BITS 0:0
1724 #define USB_DSTS_SUSP_STS_SET 0x00000001
1725 #define USB_DSTS_SUSP_STS_CLR 0xfffffffe
1726 #define USB_DSTS_SUSP_STS_MSB 0
1727 #define USB_DSTS_SUSP_STS_LSB 0
1728 #define USB_DSTS_SUSP_STS_RESET 0x0
1729 #define USB_DIEPMSK HW_REGISTER_RW( 0x7e980810 )
1730 #define USB_DIEPMSK_MASK 0xffffffff
1731 #define USB_DIEPMSK_WIDTH 32
1732 #define USB_DOEPMSK HW_REGISTER_RW( 0x7e980814 )
1733 #define USB_DOEPMSK_MASK 0xffffffff
1734 #define USB_DOEPMSK_WIDTH 32
1735 #define USB_DAINT HW_REGISTER_RW( 0x7e980818 )
1736 #define USB_DAINT_MASK 0xffffffff
1737 #define USB_DAINT_WIDTH 32
1738 #define USB_DAINT_OUT_EP_INT_BITS 31:16
1739 #define USB_DAINT_OUT_EP_INT_SET 0xffff0000
1740 #define USB_DAINT_OUT_EP_INT_CLR 0x0000ffff
1741 #define USB_DAINT_OUT_EP_INT_MSB 31
1742 #define USB_DAINT_OUT_EP_INT_LSB 16
1743 #define USB_DAINT_OUT_EP_INT_RESET 0x0
1744 #define USB_DAINT_IN_EP_INT_BITS 15:0
1745 #define USB_DAINT_IN_EP_INT_SET 0x0000ffff
1746 #define USB_DAINT_IN_EP_INT_CLR 0xffff0000
1747 #define USB_DAINT_IN_EP_INT_MSB 15
1748 #define USB_DAINT_IN_EP_INT_LSB 0
1749 #define USB_DAINT_IN_EP_INT_RESET 0x0
1750 #define USB_DAINTMSK HW_REGISTER_RW( 0x7e98081c )
1751 #define USB_DAINTMSK_MASK 0xffffffff
1752 #define USB_DAINTMSK_WIDTH 32
1753 #define USB_DTKNQR1 HW_REGISTER_RW( 0x7e980820 )
1754 #define USB_DTKNQR1_MASK 0xffffffff
1755 #define USB_DTKNQR1_WIDTH 32
1756 #define USB_DTKNQR2 HW_REGISTER_RW( 0x7e980824 )
1757 #define USB_DTKNQR2_MASK 0xffffffff
1758 #define USB_DTKNQR2_WIDTH 32
1759 #define USB_DVBUSDIS HW_REGISTER_RW( 0x7e980828 )
1760 #define USB_DVBUSDIS_MASK 0x0000ffff
1761 #define USB_DVBUSDIS_WIDTH 16
1762 #define USB_DVBUSPULSE HW_REGISTER_RW( 0x7e98082c )
1763 #define USB_DVBUSPULSE_MASK 0x00000fff
1764 #define USB_DVBUSPULSE_WIDTH 12
1765 #define USB_DVBUSPULSE_PULSE_BITS 11:0
1766 #define USB_DVBUSPULSE_PULSE_SET 0x00000fff
1767 #define USB_DVBUSPULSE_PULSE_CLR 0xfffff000
1768 #define USB_DVBUSPULSE_PULSE_MSB 11
1769 #define USB_DVBUSPULSE_PULSE_LSB 0
1770 #define USB_DVBUSPULSE_PULSE_RESET 0x0
1771 #define USB_DTKNQR3 HW_REGISTER_RW( 0x7e980830 )
1772 #define USB_DTKNQR3_MASK 0xffffffff
1773 #define USB_DTKNQR3_WIDTH 32
1774 #define USB_DTKNQR4 HW_REGISTER_RW( 0x7e980834 )
1775 #define USB_DTKNQR4_MASK 0xffffffff
1776 #define USB_DTKNQR4_WIDTH 32
1777 #define USB_DTHRCTL HW_REGISTER_RW( 0x7e980830 )
1778 #define USB_DTHRCTL_MASK 0x0fff0fff
1779 #define USB_DTHRCTL_WIDTH 28
1780 #define USB_DTHRCTL_ARB_PRK_EN_BITS 27:27
1781 #define USB_DTHRCTL_ARB_PRK_EN_SET 0x08000000
1782 #define USB_DTHRCTL_ARB_PRK_EN_CLR 0xf7ffffff
1783 #define USB_DTHRCTL_ARB_PRK_EN_MSB 27
1784 #define USB_DTHRCTL_ARB_PRK_EN_LSB 27
1785 #define USB_DTHRCTL_ARB_PRK_EN_RESET 0x0
1786 #define USB_DTHRCTL_RX_THR_LEN_BITS 26:17
1787 #define USB_DTHRCTL_RX_THR_LEN_SET 0x07fe0000
1788 #define USB_DTHRCTL_RX_THR_LEN_CLR 0xf801ffff
1789 #define USB_DTHRCTL_RX_THR_LEN_MSB 26
1790 #define USB_DTHRCTL_RX_THR_LEN_LSB 17
1791 #define USB_DTHRCTL_RX_THR_LEN_RESET 0x0
1792 #define USB_DTHRCTL_RX_THR_EN_BITS 16:16
1793 #define USB_DTHRCTL_RX_THR_EN_SET 0x00010000
1794 #define USB_DTHRCTL_RX_THR_EN_CLR 0xfffeffff
1795 #define USB_DTHRCTL_RX_THR_EN_MSB 16
1796 #define USB_DTHRCTL_RX_THR_EN_LSB 16
1797 #define USB_DTHRCTL_RX_THR_EN_RESET 0x0
1798 #define USB_DTHRCTL_TX_THR_LEN_BITS 10:2
1799 #define USB_DTHRCTL_TX_THR_LEN_SET 0x000007fc
1800 #define USB_DTHRCTL_TX_THR_LEN_CLR 0xfffff803
1801 #define USB_DTHRCTL_TX_THR_LEN_MSB 10
1802 #define USB_DTHRCTL_TX_THR_LEN_LSB 2
1803 #define USB_DTHRCTL_TX_THR_LEN_RESET 0x0
1804 #define USB_DTHRCTL_ISO_THR_EN_BITS 1:1
1805 #define USB_DTHRCTL_ISO_THR_EN_SET 0x00000002
1806 #define USB_DTHRCTL_ISO_THR_EN_CLR 0xfffffffd
1807 #define USB_DTHRCTL_ISO_THR_EN_MSB 1
1808 #define USB_DTHRCTL_ISO_THR_EN_LSB 1
1809 #define USB_DTHRCTL_ISO_THR_EN_RESET 0x0
1810 #define USB_DTHRCTL_NON_ISO_THR_EN_BITS 0:0
1811 #define USB_DTHRCTL_NON_ISO_THR_EN_SET 0x00000001
1812 #define USB_DTHRCTL_NON_ISO_THR_EN_CLR 0xfffffffe
1813 #define USB_DTHRCTL_NON_ISO_THR_EN_MSB 0
1814 #define USB_DTHRCTL_NON_ISO_THR_EN_LSB 0
1815 #define USB_DTHRCTL_NON_ISO_THR_EN_RESET 0x0
1816 #define USB_DIEPEMPMSK HW_REGISTER_RW( 0x7e980834 )
1817 #define USB_DIEPEMPMSK_MASK 0x0000ffff
1818 #define USB_DIEPEMPMSK_WIDTH 16
1819 #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_BITS 15:0
1820 #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_SET 0x0000ffff
1821 #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_CLR 0xffff0000
1822 #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_MSB 15
1823 #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_LSB 0
1824 #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_RESET 0x0
1825 #define USB_DIEPCTL0 HW_REGISTER_RW( 0x7e980900 )
1826 #define USB_DIEPCTL0_MASK 0xffffffff
1827 #define USB_DIEPCTL0_WIDTH 32
1828 #define USB_DIEPCTL0_ENA_BITS 31:31
1829 #define USB_DIEPCTL0_ENA_SET 0x80000000
1830 #define USB_DIEPCTL0_ENA_CLR 0x7fffffff
1831 #define USB_DIEPCTL0_ENA_MSB 31
1832 #define USB_DIEPCTL0_ENA_LSB 31
1833 #define USB_DIEPCTL0_ENA_RESET 0x0
1834 #define USB_DIEPCTL0_DIS_BITS 30:30
1835 #define USB_DIEPCTL0_DIS_SET 0x40000000
1836 #define USB_DIEPCTL0_DIS_CLR 0xbfffffff
1837 #define USB_DIEPCTL0_DIS_MSB 30
1838 #define USB_DIEPCTL0_DIS_LSB 30
1839 #define USB_DIEPCTL0_DIS_RESET 0x0
1840 #define USB_DIEPCTL0_SET_D1_PID_BITS 29:29
1841 #define USB_DIEPCTL0_SET_D1_PID_SET 0x20000000
1842 #define USB_DIEPCTL0_SET_D1_PID_CLR 0xdfffffff
1843 #define USB_DIEPCTL0_SET_D1_PID_MSB 29
1844 #define USB_DIEPCTL0_SET_D1_PID_LSB 29
1845 #define USB_DIEPCTL0_SET_D1_PID_RESET 0x0
1846 #define USB_DIEPCTL0_SET_ODD_FR_BITS 29:29
1847 #define USB_DIEPCTL0_SET_ODD_FR_SET 0x20000000
1848 #define USB_DIEPCTL0_SET_ODD_FR_CLR 0xdfffffff
1849 #define USB_DIEPCTL0_SET_ODD_FR_MSB 29
1850 #define USB_DIEPCTL0_SET_ODD_FR_LSB 29
1851 #define USB_DIEPCTL0_SET_ODD_FR_RESET 0x0
1852 #define USB_DIEPCTL0_SET_D0_PID_BITS 28:28
1853 #define USB_DIEPCTL0_SET_D0_PID_SET 0x10000000
1854 #define USB_DIEPCTL0_SET_D0_PID_CLR 0xefffffff
1855 #define USB_DIEPCTL0_SET_D0_PID_MSB 28
1856 #define USB_DIEPCTL0_SET_D0_PID_LSB 28
1857 #define USB_DIEPCTL0_SET_D0_PID_RESET 0x0
1858 #define USB_DIEPCTL0_SET_EVEN_FR_BITS 28:28
1859 #define USB_DIEPCTL0_SET_EVEN_FR_SET 0x10000000
1860 #define USB_DIEPCTL0_SET_EVEN_FR_CLR 0xefffffff
1861 #define USB_DIEPCTL0_SET_EVEN_FR_MSB 28
1862 #define USB_DIEPCTL0_SET_EVEN_FR_LSB 28
1863 #define USB_DIEPCTL0_SET_EVEN_FR_RESET 0x0
1864 #define USB_DIEPCTL0_SNAK_BITS 27:27
1865 #define USB_DIEPCTL0_SNAK_SET 0x08000000
1866 #define USB_DIEPCTL0_SNAK_CLR 0xf7ffffff
1867 #define USB_DIEPCTL0_SNAK_MSB 27
1868 #define USB_DIEPCTL0_SNAK_LSB 27
1869 #define USB_DIEPCTL0_SNAK_RESET 0x0
1870 #define USB_DIEPCTL0_CNAK_BITS 26:26
1871 #define USB_DIEPCTL0_CNAK_SET 0x04000000
1872 #define USB_DIEPCTL0_CNAK_CLR 0xfbffffff
1873 #define USB_DIEPCTL0_CNAK_MSB 26
1874 #define USB_DIEPCTL0_CNAK_LSB 26
1875 #define USB_DIEPCTL0_CNAK_RESET 0x0
1876 #define USB_DIEPCTL0_TXF_NUM_BITS 25:22
1877 #define USB_DIEPCTL0_TXF_NUM_SET 0x03c00000
1878 #define USB_DIEPCTL0_TXF_NUM_CLR 0xfc3fffff
1879 #define USB_DIEPCTL0_TXF_NUM_MSB 25
1880 #define USB_DIEPCTL0_TXF_NUM_LSB 22
1881 #define USB_DIEPCTL0_TXF_NUM_RESET 0x0
1882 #define USB_DIEPCTL0_STALL_BITS 21:21
1883 #define USB_DIEPCTL0_STALL_SET 0x00200000
1884 #define USB_DIEPCTL0_STALL_CLR 0xffdfffff
1885 #define USB_DIEPCTL0_STALL_MSB 21
1886 #define USB_DIEPCTL0_STALL_LSB 21
1887 #define USB_DIEPCTL0_STALL_RESET 0x0
1888 #define USB_DIEPCTL0_SNP_BITS 20:20
1889 #define USB_DIEPCTL0_SNP_SET 0x00100000
1890 #define USB_DIEPCTL0_SNP_CLR 0xffefffff
1891 #define USB_DIEPCTL0_SNP_MSB 20
1892 #define USB_DIEPCTL0_SNP_LSB 20
1893 #define USB_DIEPCTL0_SNP_RESET 0x0
1894 #define USB_DIEPCTL0_TYPE_BITS 19:18
1895 #define USB_DIEPCTL0_TYPE_SET 0x000c0000
1896 #define USB_DIEPCTL0_TYPE_CLR 0xfff3ffff
1897 #define USB_DIEPCTL0_TYPE_MSB 19
1898 #define USB_DIEPCTL0_TYPE_LSB 18
1899 #define USB_DIEPCTL0_TYPE_RESET 0x0
1900 #define USB_DIEPCTL0_NAK_STS_BITS 17:17
1901 #define USB_DIEPCTL0_NAK_STS_SET 0x00020000
1902 #define USB_DIEPCTL0_NAK_STS_CLR 0xfffdffff
1903 #define USB_DIEPCTL0_NAK_STS_MSB 17
1904 #define USB_DIEPCTL0_NAK_STS_LSB 17
1905 #define USB_DIEPCTL0_NAK_STS_RESET 0x0
1906 #define USB_DIEPCTL0_DPID_BITS 16:16
1907 #define USB_DIEPCTL0_DPID_SET 0x00010000
1908 #define USB_DIEPCTL0_DPID_CLR 0xfffeffff
1909 #define USB_DIEPCTL0_DPID_MSB 16
1910 #define USB_DIEPCTL0_DPID_LSB 16
1911 #define USB_DIEPCTL0_DPID_RESET 0x0
1912 #define USB_DIEPCTL0_EO_FR_NUM_BITS 16:16
1913 #define USB_DIEPCTL0_EO_FR_NUM_SET 0x00010000
1914 #define USB_DIEPCTL0_EO_FR_NUM_CLR 0xfffeffff
1915 #define USB_DIEPCTL0_EO_FR_NUM_MSB 16
1916 #define USB_DIEPCTL0_EO_FR_NUM_LSB 16
1917 #define USB_DIEPCTL0_EO_FR_NUM_RESET 0x0
1918 #define USB_DIEPCTL0_USB_ACT_EP_BITS 15:15
1919 #define USB_DIEPCTL0_USB_ACT_EP_SET 0x00008000
1920 #define USB_DIEPCTL0_USB_ACT_EP_CLR 0xffff7fff
1921 #define USB_DIEPCTL0_USB_ACT_EP_MSB 15
1922 #define USB_DIEPCTL0_USB_ACT_EP_LSB 15
1923 #define USB_DIEPCTL0_USB_ACT_EP_RESET 0x0
1924 #define USB_DIEPCTL0_NEXT_EP_BITS 14:11
1925 #define USB_DIEPCTL0_NEXT_EP_SET 0x00007800
1926 #define USB_DIEPCTL0_NEXT_EP_CLR 0xffff87ff
1927 #define USB_DIEPCTL0_NEXT_EP_MSB 14
1928 #define USB_DIEPCTL0_NEXT_EP_LSB 11
1929 #define USB_DIEPCTL0_NEXT_EP_RESET 0x0
1930 #define USB_DIEPCTL0_MPS_BITS 10:0
1931 #define USB_DIEPCTL0_MPS_SET 0x000007ff
1932 #define USB_DIEPCTL0_MPS_CLR 0xfffff800
1933 #define USB_DIEPCTL0_MPS_MSB 10
1934 #define USB_DIEPCTL0_MPS_LSB 0
1935 #define USB_DIEPCTL0_MPS_RESET 0x0
1936 #define USB_DIEPINT0 HW_REGISTER_RW( 0x7e980908 )
1937 #define USB_DIEPINT0_MASK 0xffffffff
1938 #define USB_DIEPINT0_WIDTH 32
1939 #define USB_DIEPINT0_BNA_BITS 9:9
1940 #define USB_DIEPINT0_BNA_SET 0x00000200
1941 #define USB_DIEPINT0_BNA_CLR 0xfffffdff
1942 #define USB_DIEPINT0_BNA_MSB 9
1943 #define USB_DIEPINT0_BNA_LSB 9
1944 #define USB_DIEPINT0_BNA_RESET 0x0
1945 #define USB_DIEPINT0_TX_FIFO_UNDRN_BITS 8:8
1946 #define USB_DIEPINT0_TX_FIFO_UNDRN_SET 0x00000100
1947 #define USB_DIEPINT0_TX_FIFO_UNDRN_CLR 0xfffffeff
1948 #define USB_DIEPINT0_TX_FIFO_UNDRN_MSB 8
1949 #define USB_DIEPINT0_TX_FIFO_UNDRN_LSB 8
1950 #define USB_DIEPINT0_TX_FIFO_UNDRN_RESET 0x0
1951 #define USB_DIEPINT0_OUT_PKT_ERR_BITS 8:8
1952 #define USB_DIEPINT0_OUT_PKT_ERR_SET 0x00000100
1953 #define USB_DIEPINT0_OUT_PKT_ERR_CLR 0xfffffeff
1954 #define USB_DIEPINT0_OUT_PKT_ERR_MSB 8
1955 #define USB_DIEPINT0_OUT_PKT_ERR_LSB 8
1956 #define USB_DIEPINT0_OUT_PKT_ERR_RESET 0x0
1957 #define USB_DIEPINT0_TXF_EMPTY_BITS 7:7
1958 #define USB_DIEPINT0_TXF_EMPTY_SET 0x00000080
1959 #define USB_DIEPINT0_TXF_EMPTY_CLR 0xffffff7f
1960 #define USB_DIEPINT0_TXF_EMPTY_MSB 7
1961 #define USB_DIEPINT0_TXF_EMPTY_LSB 7
1962 #define USB_DIEPINT0_TXF_EMPTY_RESET 0x0
1963 #define USB_DIEPINT0_IN_EP_NAK_EFF_BITS 6:6
1964 #define USB_DIEPINT0_IN_EP_NAK_EFF_SET 0x00000040
1965 #define USB_DIEPINT0_IN_EP_NAK_EFF_CLR 0xffffffbf
1966 #define USB_DIEPINT0_IN_EP_NAK_EFF_MSB 6
1967 #define USB_DIEPINT0_IN_EP_NAK_EFF_LSB 6
1968 #define USB_DIEPINT0_IN_EP_NAK_EFF_RESET 0x0
1969 #define USB_DIEPINT0_BACK2BACK_SETUP_BITS 6:6
1970 #define USB_DIEPINT0_BACK2BACK_SETUP_SET 0x00000040
1971 #define USB_DIEPINT0_BACK2BACK_SETUP_CLR 0xffffffbf
1972 #define USB_DIEPINT0_BACK2BACK_SETUP_MSB 6
1973 #define USB_DIEPINT0_BACK2BACK_SETUP_LSB 6
1974 #define USB_DIEPINT0_BACK2BACK_SETUP_RESET 0x0
1975 #define USB_DIEPINT0_IN_TKN_EP_MIS_BITS 5:5
1976 #define USB_DIEPINT0_IN_TKN_EP_MIS_SET 0x00000020
1977 #define USB_DIEPINT0_IN_TKN_EP_MIS_CLR 0xffffffdf
1978 #define USB_DIEPINT0_IN_TKN_EP_MIS_MSB 5
1979 #define USB_DIEPINT0_IN_TKN_EP_MIS_LSB 5
1980 #define USB_DIEPINT0_IN_TKN_EP_MIS_RESET 0x0
1981 #define USB_DIEPINT0_STS_PHSE_RCVD_BITS 5:5
1982 #define USB_DIEPINT0_STS_PHSE_RCVD_SET 0x00000020
1983 #define USB_DIEPINT0_STS_PHSE_RCVD_CLR 0xffffffdf
1984 #define USB_DIEPINT0_STS_PHSE_RCVD_MSB 5
1985 #define USB_DIEPINT0_STS_PHSE_RCVD_LSB 5
1986 #define USB_DIEPINT0_STS_PHSE_RCVD_RESET 0x0
1987 #define USB_DIEPINT0_IN_TKN_TXFEMP_BITS 4:4
1988 #define USB_DIEPINT0_IN_TKN_TXFEMP_SET 0x00000010
1989 #define USB_DIEPINT0_IN_TKN_TXFEMP_CLR 0xffffffef
1990 #define USB_DIEPINT0_IN_TKN_TXFEMP_MSB 4
1991 #define USB_DIEPINT0_IN_TKN_TXFEMP_LSB 4
1992 #define USB_DIEPINT0_IN_TKN_TXFEMP_RESET 0x0
1993 #define USB_DIEPINT0_OUT_TKN_EP_DIS_BITS 4:4
1994 #define USB_DIEPINT0_OUT_TKN_EP_DIS_SET 0x00000010
1995 #define USB_DIEPINT0_OUT_TKN_EP_DIS_CLR 0xffffffef
1996 #define USB_DIEPINT0_OUT_TKN_EP_DIS_MSB 4
1997 #define USB_DIEPINT0_OUT_TKN_EP_DIS_LSB 4
1998 #define USB_DIEPINT0_OUT_TKN_EP_DIS_RESET 0x0
1999 #define USB_DIEPINT0_TIMEOUT_BITS 3:3
2000 #define USB_DIEPINT0_TIMEOUT_SET 0x00000008
2001 #define USB_DIEPINT0_TIMEOUT_CLR 0xfffffff7
2002 #define USB_DIEPINT0_TIMEOUT_MSB 3
2003 #define USB_DIEPINT0_TIMEOUT_LSB 3
2004 #define USB_DIEPINT0_TIMEOUT_RESET 0x0
2005 #define USB_DIEPINT0_SETUP_BITS 3:3
2006 #define USB_DIEPINT0_SETUP_SET 0x00000008
2007 #define USB_DIEPINT0_SETUP_CLR 0xfffffff7
2008 #define USB_DIEPINT0_SETUP_MSB 3
2009 #define USB_DIEPINT0_SETUP_LSB 3
2010 #define USB_DIEPINT0_SETUP_RESET 0x0
2011 #define USB_DIEPINT0_AHB_ERR_BITS 2:2
2012 #define USB_DIEPINT0_AHB_ERR_SET 0x00000004
2013 #define USB_DIEPINT0_AHB_ERR_CLR 0xfffffffb
2014 #define USB_DIEPINT0_AHB_ERR_MSB 2
2015 #define USB_DIEPINT0_AHB_ERR_LSB 2
2016 #define USB_DIEPINT0_AHB_ERR_RESET 0x0
2017 #define USB_DIEPINT0_EP_DISBLD_BITS 1:1
2018 #define USB_DIEPINT0_EP_DISBLD_SET 0x00000002
2019 #define USB_DIEPINT0_EP_DISBLD_CLR 0xfffffffd
2020 #define USB_DIEPINT0_EP_DISBLD_MSB 1
2021 #define USB_DIEPINT0_EP_DISBLD_LSB 1
2022 #define USB_DIEPINT0_EP_DISBLD_RESET 0x0
2023 #define USB_DIEPINT0_XFER_COMPL_BITS 0:0
2024 #define USB_DIEPINT0_XFER_COMPL_SET 0x00000001
2025 #define USB_DIEPINT0_XFER_COMPL_CLR 0xfffffffe
2026 #define USB_DIEPINT0_XFER_COMPL_MSB 0
2027 #define USB_DIEPINT0_XFER_COMPL_LSB 0
2028 #define USB_DIEPINT0_XFER_COMPL_RESET 0x0
2029 #define USB_DIEPTSIZ0 HW_REGISTER_RW( 0x7e980910 )
2030 #define USB_DIEPTSIZ0_MASK 0xffffffff
2031 #define USB_DIEPTSIZ0_WIDTH 32
2032 #define USB_DIEPTSIZ0_SUP_CNT_BITS 30:29
2033 #define USB_DIEPTSIZ0_SUP_CNT_SET 0x60000000
2034 #define USB_DIEPTSIZ0_SUP_CNT_CLR 0x9fffffff
2035 #define USB_DIEPTSIZ0_SUP_CNT_MSB 30
2036 #define USB_DIEPTSIZ0_SUP_CNT_LSB 29
2037 #define USB_DIEPTSIZ0_SUP_CNT_RESET 0x0
2038 #define USB_DIEPTSIZ0_RX_DPID_BITS 30:29
2039 #define USB_DIEPTSIZ0_RX_DPID_SET 0x60000000
2040 #define USB_DIEPTSIZ0_RX_DPID_CLR 0x9fffffff
2041 #define USB_DIEPTSIZ0_RX_DPID_MSB 30
2042 #define USB_DIEPTSIZ0_RX_DPID_LSB 29
2043 #define USB_DIEPTSIZ0_RX_DPID_RESET 0x0
2044 #define USB_DIEPTSIZ0_MC_BITS 30:29
2045 #define USB_DIEPTSIZ0_MC_SET 0x60000000
2046 #define USB_DIEPTSIZ0_MC_CLR 0x9fffffff
2047 #define USB_DIEPTSIZ0_MC_MSB 30
2048 #define USB_DIEPTSIZ0_MC_LSB 29
2049 #define USB_DIEPTSIZ0_MC_RESET 0x0
2050 #define USB_DIEPTSIZ0_PKT_CNT_BITS 28:19
2051 #define USB_DIEPTSIZ0_PKT_CNT_SET 0x1ff80000
2052 #define USB_DIEPTSIZ0_PKT_CNT_CLR 0xe007ffff
2053 #define USB_DIEPTSIZ0_PKT_CNT_MSB 28
2054 #define USB_DIEPTSIZ0_PKT_CNT_LSB 19
2055 #define USB_DIEPTSIZ0_PKT_CNT_RESET 0x0
2056 #define USB_DIEPTSIZ0_XFERSIZE_BITS 18:0
2057 #define USB_DIEPTSIZ0_XFERSIZE_SET 0x0007ffff
2058 #define USB_DIEPTSIZ0_XFERSIZE_CLR 0xfff80000
2059 #define USB_DIEPTSIZ0_XFERSIZE_MSB 18
2060 #define USB_DIEPTSIZ0_XFERSIZE_LSB 0
2061 #define USB_DIEPTSIZ0_XFERSIZE_RESET 0x0
2062 #define USB_DIEPDMA0 HW_REGISTER_RW( 0x7e980914 )
2063 #define USB_DIEPDMA0_MASK 0xffffffff
2064 #define USB_DIEPDMA0_WIDTH 32
2065 #define USB_DTXFSTS0 HW_REGISTER_RW( 0x7e980918 )
2066 #define USB_DTXFSTS0_MASK 0xffffffff
2067 #define USB_DTXFSTS0_WIDTH 32
2068 #define USB_DTXFSTS0_SPC_AVAIL_BITS 31:16
2069 #define USB_DTXFSTS0_SPC_AVAIL_SET 0xffff0000
2070 #define USB_DTXFSTS0_SPC_AVAIL_CLR 0x0000ffff
2071 #define USB_DTXFSTS0_SPC_AVAIL_MSB 31
2072 #define USB_DTXFSTS0_SPC_AVAIL_LSB 16
2073 #define USB_DTXFSTS0_SPC_AVAIL_RESET 0x0
2074 #define USB_DIEPDMAB0 HW_REGISTER_RW( 0x7e980918 )
2075 #define USB_DIEPDMAB0_MASK 0xffffffff
2076 #define USB_DIEPDMAB0_WIDTH 32
2077 #define USB_DIEPCTL1 HW_REGISTER_RW( 0x7e980920 )
2078 #define USB_DIEPCTL1_MASK 0xffffffff
2079 #define USB_DIEPCTL1_WIDTH 32
2080 #define USB_DIEPINT1 HW_REGISTER_RW( 0x7e980928 )
2081 #define USB_DIEPINT1_MASK 0xffffffff
2082 #define USB_DIEPINT1_WIDTH 32
2083 #define USB_DIEPTSIZ1 HW_REGISTER_RW( 0x7e980930 )
2084 #define USB_DIEPTSIZ1_MASK 0xffffffff
2085 #define USB_DIEPTSIZ1_WIDTH 32
2086 #define USB_DIEPDMA1 HW_REGISTER_RW( 0x7e980934 )
2087 #define USB_DIEPDMA1_MASK 0xffffffff
2088 #define USB_DIEPDMA1_WIDTH 32
2089 #define USB_DTXFSTS1 HW_REGISTER_RW( 0x7e980938 )
2090 #define USB_DTXFSTS1_MASK 0xffffffff
2091 #define USB_DTXFSTS1_WIDTH 32
2092 #define USB_DIEPDMAB1 HW_REGISTER_RW( 0x7e980938 )
2093 #define USB_DIEPDMAB1_MASK 0xffffffff
2094 #define USB_DIEPDMAB1_WIDTH 32
2095 #define USB_DIEPCTL2 HW_REGISTER_RW( 0x7e980940 )
2096 #define USB_DIEPCTL2_MASK 0xffffffff
2097 #define USB_DIEPCTL2_WIDTH 32
2098 #define USB_DIEPINT2 HW_REGISTER_RW( 0x7e980948 )
2099 #define USB_DIEPINT2_MASK 0xffffffff
2100 #define USB_DIEPINT2_WIDTH 32
2101 #define USB_DIEPTSIZ2 HW_REGISTER_RW( 0x7e980950 )
2102 #define USB_DIEPTSIZ2_MASK 0xffffffff
2103 #define USB_DIEPTSIZ2_WIDTH 32
2104 #define USB_DIEPDMA2 HW_REGISTER_RW( 0x7e980954 )
2105 #define USB_DIEPDMA2_MASK 0xffffffff
2106 #define USB_DIEPDMA2_WIDTH 32
2107 #define USB_DTXFSTS2 HW_REGISTER_RW( 0x7e980958 )
2108 #define USB_DTXFSTS2_MASK 0xffffffff
2109 #define USB_DTXFSTS2_WIDTH 32
2110 #define USB_DIEPDMAB2 HW_REGISTER_RW( 0x7e980958 )
2111 #define USB_DIEPDMAB2_MASK 0xffffffff
2112 #define USB_DIEPDMAB2_WIDTH 32
2113 #define USB_DIEPCTL3 HW_REGISTER_RW( 0x7e980960 )
2114 #define USB_DIEPCTL3_MASK 0xffffffff
2115 #define USB_DIEPCTL3_WIDTH 32
2116 #define USB_DIEPINT3 HW_REGISTER_RW( 0x7e980968 )
2117 #define USB_DIEPINT3_MASK 0xffffffff
2118 #define USB_DIEPINT3_WIDTH 32
2119 #define USB_DIEPTSIZ3 HW_REGISTER_RW( 0x7e980970 )
2120 #define USB_DIEPTSIZ3_MASK 0xffffffff
2121 #define USB_DIEPTSIZ3_WIDTH 32
2122 #define USB_DIEPDMA3 HW_REGISTER_RW( 0x7e980974 )
2123 #define USB_DIEPDMA3_MASK 0xffffffff
2124 #define USB_DIEPDMA3_WIDTH 32
2125 #define USB_DTXFSTS3 HW_REGISTER_RW( 0x7e980978 )
2126 #define USB_DTXFSTS3_MASK 0xffffffff
2127 #define USB_DTXFSTS3_WIDTH 32
2128 #define USB_DIEPDMAB3 HW_REGISTER_RW( 0x7e980978 )
2129 #define USB_DIEPDMAB3_MASK 0xffffffff
2130 #define USB_DIEPDMAB3_WIDTH 32
2131 #define USB_DIEPCTL4 HW_REGISTER_RW( 0x7e980980 )
2132 #define USB_DIEPCTL4_MASK 0xffffffff
2133 #define USB_DIEPCTL4_WIDTH 32
2134 #define USB_DIEPINT4 HW_REGISTER_RW( 0x7e980988 )
2135 #define USB_DIEPINT4_MASK 0xffffffff
2136 #define USB_DIEPINT4_WIDTH 32
2137 #define USB_DIEPTSIZ4 HW_REGISTER_RW( 0x7e980990 )
2138 #define USB_DIEPTSIZ4_MASK 0xffffffff
2139 #define USB_DIEPTSIZ4_WIDTH 32
2140 #define USB_DIEPDMA4 HW_REGISTER_RW( 0x7e980994 )
2141 #define USB_DIEPDMA4_MASK 0xffffffff
2142 #define USB_DIEPDMA4_WIDTH 32
2143 #define USB_DTXFSTS4 HW_REGISTER_RW( 0x7e980998 )
2144 #define USB_DTXFSTS4_MASK 0xffffffff
2145 #define USB_DTXFSTS4_WIDTH 32
2146 #define USB_DIEPDMAB4 HW_REGISTER_RW( 0x7e980998 )
2147 #define USB_DIEPDMAB4_MASK 0xffffffff
2148 #define USB_DIEPDMAB4_WIDTH 32
2149 #define USB_DIEPCTL5 HW_REGISTER_RW( 0x7e9809a0 )
2150 #define USB_DIEPCTL5_MASK 0xffffffff
2151 #define USB_DIEPCTL5_WIDTH 32
2152 #define USB_DIEPINT5 HW_REGISTER_RW( 0x7e9809a8 )
2153 #define USB_DIEPINT5_MASK 0xffffffff
2154 #define USB_DIEPINT5_WIDTH 32
2155 #define USB_DIEPTSIZ5 HW_REGISTER_RW( 0x7e9809b0 )
2156 #define USB_DIEPTSIZ5_MASK 0xffffffff
2157 #define USB_DIEPTSIZ5_WIDTH 32
2158 #define USB_DIEPDMA5 HW_REGISTER_RW( 0x7e9809b4 )
2159 #define USB_DIEPDMA5_MASK 0xffffffff
2160 #define USB_DIEPDMA5_WIDTH 32
2161 #define USB_DTXFSTS5 HW_REGISTER_RW( 0x7e9809b8 )
2162 #define USB_DTXFSTS5_MASK 0xffffffff
2163 #define USB_DTXFSTS5_WIDTH 32
2164 #define USB_DIEPDMAB5 HW_REGISTER_RW( 0x7e9809b8 )
2165 #define USB_DIEPDMAB5_MASK 0xffffffff
2166 #define USB_DIEPDMAB5_WIDTH 32
2167 #define USB_DIEPCTL6 HW_REGISTER_RW( 0x7e9809c0 )
2168 #define USB_DIEPCTL6_MASK 0xffffffff
2169 #define USB_DIEPCTL6_WIDTH 32
2170 #define USB_DIEPINT6 HW_REGISTER_RW( 0x7e9809c8 )
2171 #define USB_DIEPINT6_MASK 0xffffffff
2172 #define USB_DIEPINT6_WIDTH 32
2173 #define USB_DIEPTSIZ6 HW_REGISTER_RW( 0x7e9809d0 )
2174 #define USB_DIEPTSIZ6_MASK 0xffffffff
2175 #define USB_DIEPTSIZ6_WIDTH 32
2176 #define USB_DIEPDMA6 HW_REGISTER_RW( 0x7e9809d4 )
2177 #define USB_DIEPDMA6_MASK 0xffffffff
2178 #define USB_DIEPDMA6_WIDTH 32
2179 #define USB_DTXFSTS6 HW_REGISTER_RW( 0x7e9809d8 )
2180 #define USB_DTXFSTS6_MASK 0xffffffff
2181 #define USB_DTXFSTS6_WIDTH 32
2182 #define USB_DIEPDMAB6 HW_REGISTER_RW( 0x7e9809d8 )
2183 #define USB_DIEPDMAB6_MASK 0xffffffff
2184 #define USB_DIEPDMAB6_WIDTH 32
2185 #define USB_DIEPCTL7 HW_REGISTER_RW( 0x7e9809e0 )
2186 #define USB_DIEPCTL7_MASK 0xffffffff
2187 #define USB_DIEPCTL7_WIDTH 32
2188 #define USB_DIEPINT7 HW_REGISTER_RW( 0x7e9809e8 )
2189 #define USB_DIEPINT7_MASK 0xffffffff
2190 #define USB_DIEPINT7_WIDTH 32
2191 #define USB_DIEPTSIZ7 HW_REGISTER_RW( 0x7e9809f0 )
2192 #define USB_DIEPTSIZ7_MASK 0xffffffff
2193 #define USB_DIEPTSIZ7_WIDTH 32
2194 #define USB_DIEPDMA7 HW_REGISTER_RW( 0x7e9809f4 )
2195 #define USB_DIEPDMA7_MASK 0xffffffff
2196 #define USB_DIEPDMA7_WIDTH 32
2197 #define USB_DTXFSTS7 HW_REGISTER_RW( 0x7e9809f8 )
2198 #define USB_DTXFSTS7_MASK 0xffffffff
2199 #define USB_DTXFSTS7_WIDTH 32
2200 #define USB_DIEPDMAB7 HW_REGISTER_RW( 0x7e9809f8 )
2201 #define USB_DIEPDMAB7_MASK 0xffffffff
2202 #define USB_DIEPDMAB7_WIDTH 32
2203 #define USB_DIEPCTL8 HW_REGISTER_RW( 0x7e980a00 )
2204 #define USB_DIEPCTL8_MASK 0xffffffff
2205 #define USB_DIEPCTL8_WIDTH 32
2206 #define USB_DIEPINT8 HW_REGISTER_RW( 0x7e980a08 )
2207 #define USB_DIEPINT8_MASK 0xffffffff
2208 #define USB_DIEPINT8_WIDTH 32
2209 #define USB_DIEPTSIZ8 HW_REGISTER_RW( 0x7e980a10 )
2210 #define USB_DIEPTSIZ8_MASK 0xffffffff
2211 #define USB_DIEPTSIZ8_WIDTH 32
2212 #define USB_DIEPDMA8 HW_REGISTER_RW( 0x7e980a14 )
2213 #define USB_DIEPDMA8_MASK 0xffffffff
2214 #define USB_DIEPDMA8_WIDTH 32
2215 #define USB_DTXFSTS8 HW_REGISTER_RW( 0x7e980a18 )
2216 #define USB_DTXFSTS8_MASK 0xffffffff
2217 #define USB_DTXFSTS8_WIDTH 32
2218 #define USB_DIEPDMAB8 HW_REGISTER_RW( 0x7e980a18 )
2219 #define USB_DIEPDMAB8_MASK 0xffffffff
2220 #define USB_DIEPDMAB8_WIDTH 32
2221 #define USB_DIEPCTL9 HW_REGISTER_RW( 0x7e980a20 )
2222 #define USB_DIEPCTL9_MASK 0xffffffff
2223 #define USB_DIEPCTL9_WIDTH 32
2224 #define USB_DIEPINT9 HW_REGISTER_RW( 0x7e980a28 )
2225 #define USB_DIEPINT9_MASK 0xffffffff
2226 #define USB_DIEPINT9_WIDTH 32
2227 #define USB_DIEPTSIZ9 HW_REGISTER_RW( 0x7e980a30 )
2228 #define USB_DIEPTSIZ9_MASK 0xffffffff
2229 #define USB_DIEPTSIZ9_WIDTH 32
2230 #define USB_DIEPDMA9 HW_REGISTER_RW( 0x7e980a34 )
2231 #define USB_DIEPDMA9_MASK 0xffffffff
2232 #define USB_DIEPDMA9_WIDTH 32
2233 #define USB_DTXFSTS9 HW_REGISTER_RW( 0x7e980a38 )
2234 #define USB_DTXFSTS9_MASK 0xffffffff
2235 #define USB_DTXFSTS9_WIDTH 32
2236 #define USB_DIEPDMAB9 HW_REGISTER_RW( 0x7e980a38 )
2237 #define USB_DIEPDMAB9_MASK 0xffffffff
2238 #define USB_DIEPDMAB9_WIDTH 32
2239 #define USB_DIEPCTL10 HW_REGISTER_RW( 0x7e980a40 )
2240 #define USB_DIEPCTL10_MASK 0xffffffff
2241 #define USB_DIEPCTL10_WIDTH 32
2242 #define USB_DIEPINT10 HW_REGISTER_RW( 0x7e980a48 )
2243 #define USB_DIEPINT10_MASK 0xffffffff
2244 #define USB_DIEPINT10_WIDTH 32
2245 #define USB_DIEPTSIZ10 HW_REGISTER_RW( 0x7e980a50 )
2246 #define USB_DIEPTSIZ10_MASK 0xffffffff
2247 #define USB_DIEPTSIZ10_WIDTH 32
2248 #define USB_DIEPDMA10 HW_REGISTER_RW( 0x7e980a54 )
2249 #define USB_DIEPDMA10_MASK 0xffffffff
2250 #define USB_DIEPDMA10_WIDTH 32
2251 #define USB_DTXFSTS10 HW_REGISTER_RW( 0x7e980a58 )
2252 #define USB_DTXFSTS10_MASK 0xffffffff
2253 #define USB_DTXFSTS10_WIDTH 32
2254 #define USB_DIEPDMAB10 HW_REGISTER_RW( 0x7e980a58 )
2255 #define USB_DIEPDMAB10_MASK 0xffffffff
2256 #define USB_DIEPDMAB10_WIDTH 32
2257 #define USB_DIEPCTL11 HW_REGISTER_RW( 0x7e980a60 )
2258 #define USB_DIEPCTL11_MASK 0xffffffff
2259 #define USB_DIEPCTL11_WIDTH 32
2260 #define USB_DIEPINT11 HW_REGISTER_RW( 0x7e980a68 )
2261 #define USB_DIEPINT11_MASK 0xffffffff
2262 #define USB_DIEPINT11_WIDTH 32
2263 #define USB_DIEPTSIZ11 HW_REGISTER_RW( 0x7e980a70 )
2264 #define USB_DIEPTSIZ11_MASK 0xffffffff
2265 #define USB_DIEPTSIZ11_WIDTH 32
2266 #define USB_DIEPDMA11 HW_REGISTER_RW( 0x7e980a74 )
2267 #define USB_DIEPDMA11_MASK 0xffffffff
2268 #define USB_DIEPDMA11_WIDTH 32
2269 #define USB_DTXFSTS11 HW_REGISTER_RW( 0x7e980a78 )
2270 #define USB_DTXFSTS11_MASK 0xffffffff
2271 #define USB_DTXFSTS11_WIDTH 32
2272 #define USB_DIEPDMAB11 HW_REGISTER_RW( 0x7e980a78 )
2273 #define USB_DIEPDMAB11_MASK 0xffffffff
2274 #define USB_DIEPDMAB11_WIDTH 32
2275 #define USB_DIEPCTL12 HW_REGISTER_RW( 0x7e980a80 )
2276 #define USB_DIEPCTL12_MASK 0xffffffff
2277 #define USB_DIEPCTL12_WIDTH 32
2278 #define USB_DIEPINT12 HW_REGISTER_RW( 0x7e980a88 )
2279 #define USB_DIEPINT12_MASK 0xffffffff
2280 #define USB_DIEPINT12_WIDTH 32
2281 #define USB_DIEPTSIZ12 HW_REGISTER_RW( 0x7e980a90 )
2282 #define USB_DIEPTSIZ12_MASK 0xffffffff
2283 #define USB_DIEPTSIZ12_WIDTH 32
2284 #define USB_DIEPDMA12 HW_REGISTER_RW( 0x7e980a94 )
2285 #define USB_DIEPDMA12_MASK 0xffffffff
2286 #define USB_DIEPDMA12_WIDTH 32
2287 #define USB_DTXFSTS12 HW_REGISTER_RW( 0x7e980a98 )
2288 #define USB_DTXFSTS12_MASK 0xffffffff
2289 #define USB_DTXFSTS12_WIDTH 32
2290 #define USB_DIEPDMAB12 HW_REGISTER_RW( 0x7e980a98 )
2291 #define USB_DIEPDMAB12_MASK 0xffffffff
2292 #define USB_DIEPDMAB12_WIDTH 32
2293 #define USB_DIEPCTL13 HW_REGISTER_RW( 0x7e980aa0 )
2294 #define USB_DIEPCTL13_MASK 0xffffffff
2295 #define USB_DIEPCTL13_WIDTH 32
2296 #define USB_DIEPINT13 HW_REGISTER_RW( 0x7e980aa8 )
2297 #define USB_DIEPINT13_MASK 0xffffffff
2298 #define USB_DIEPINT13_WIDTH 32
2299 #define USB_DIEPTSIZ13 HW_REGISTER_RW( 0x7e980ab0 )
2300 #define USB_DIEPTSIZ13_MASK 0xffffffff
2301 #define USB_DIEPTSIZ13_WIDTH 32
2302 #define USB_DIEPDMA13 HW_REGISTER_RW( 0x7e980ab4 )
2303 #define USB_DIEPDMA13_MASK 0xffffffff
2304 #define USB_DIEPDMA13_WIDTH 32
2305 #define USB_DTXFSTS13 HW_REGISTER_RW( 0x7e980ab8 )
2306 #define USB_DTXFSTS13_MASK 0xffffffff
2307 #define USB_DTXFSTS13_WIDTH 32
2308 #define USB_DIEPDMAB13 HW_REGISTER_RW( 0x7e980ab8 )
2309 #define USB_DIEPDMAB13_MASK 0xffffffff
2310 #define USB_DIEPDMAB13_WIDTH 32
2311 #define USB_DIEPCTL14 HW_REGISTER_RW( 0x7e980ac0 )
2312 #define USB_DIEPCTL14_MASK 0xffffffff
2313 #define USB_DIEPCTL14_WIDTH 32
2314 #define USB_DIEPINT14 HW_REGISTER_RW( 0x7e980ac8 )
2315 #define USB_DIEPINT14_MASK 0xffffffff
2316 #define USB_DIEPINT14_WIDTH 32
2317 #define USB_DIEPTSIZ14 HW_REGISTER_RW( 0x7e980ad0 )
2318 #define USB_DIEPTSIZ14_MASK 0xffffffff
2319 #define USB_DIEPTSIZ14_WIDTH 32
2320 #define USB_DIEPDMA14 HW_REGISTER_RW( 0x7e980ad4 )
2321 #define USB_DIEPDMA14_MASK 0xffffffff
2322 #define USB_DIEPDMA14_WIDTH 32
2323 #define USB_DTXFSTS14 HW_REGISTER_RW( 0x7e980ad8 )
2324 #define USB_DTXFSTS14_MASK 0xffffffff
2325 #define USB_DTXFSTS14_WIDTH 32
2326 #define USB_DIEPDMAB14 HW_REGISTER_RW( 0x7e980ad8 )
2327 #define USB_DIEPDMAB14_MASK 0xffffffff
2328 #define USB_DIEPDMAB14_WIDTH 32
2329 #define USB_DIEPCTL15 HW_REGISTER_RW( 0x7e980ae0 )
2330 #define USB_DIEPCTL15_MASK 0xffffffff
2331 #define USB_DIEPCTL15_WIDTH 32
2332 #define USB_DIEPINT15 HW_REGISTER_RW( 0x7e980ae8 )
2333 #define USB_DIEPINT15_MASK 0xffffffff
2334 #define USB_DIEPINT15_WIDTH 32
2335 #define USB_DIEPTSIZ15 HW_REGISTER_RW( 0x7e980af0 )
2336 #define USB_DIEPTSIZ15_MASK 0xffffffff
2337 #define USB_DIEPTSIZ15_WIDTH 32
2338 #define USB_DIEPDMA15 HW_REGISTER_RW( 0x7e980af4 )
2339 #define USB_DIEPDMA15_MASK 0xffffffff
2340 #define USB_DIEPDMA15_WIDTH 32
2341 #define USB_DTXFSTS15 HW_REGISTER_RW( 0x7e980af8 )
2342 #define USB_DTXFSTS15_MASK 0xffffffff
2343 #define USB_DTXFSTS15_WIDTH 32
2344 #define USB_DIEPDMAB15 HW_REGISTER_RW( 0x7e980af8 )
2345 #define USB_DIEPDMAB15_MASK 0xffffffff
2346 #define USB_DIEPDMAB15_WIDTH 32
2347 #define USB_DOEPCTL0 HW_REGISTER_RW( 0x7e980b00 )
2348 #define USB_DOEPCTL0_MASK 0xffffffff
2349 #define USB_DOEPCTL0_WIDTH 32
2350 #define USB_DOEPCTL0_ENA_BITS 31:31
2351 #define USB_DOEPCTL0_ENA_SET 0x80000000
2352 #define USB_DOEPCTL0_ENA_CLR 0x7fffffff
2353 #define USB_DOEPCTL0_ENA_MSB 31
2354 #define USB_DOEPCTL0_ENA_LSB 31
2355 #define USB_DOEPCTL0_ENA_RESET 0x0
2356 #define USB_DOEPCTL0_DIS_BITS 30:30
2357 #define USB_DOEPCTL0_DIS_SET 0x40000000
2358 #define USB_DOEPCTL0_DIS_CLR 0xbfffffff
2359 #define USB_DOEPCTL0_DIS_MSB 30
2360 #define USB_DOEPCTL0_DIS_LSB 30
2361 #define USB_DOEPCTL0_DIS_RESET 0x0
2362 #define USB_DOEPCTL0_SET_D1_PID_BITS 29:29
2363 #define USB_DOEPCTL0_SET_D1_PID_SET 0x20000000
2364 #define USB_DOEPCTL0_SET_D1_PID_CLR 0xdfffffff
2365 #define USB_DOEPCTL0_SET_D1_PID_MSB 29
2366 #define USB_DOEPCTL0_SET_D1_PID_LSB 29
2367 #define USB_DOEPCTL0_SET_D1_PID_RESET 0x0
2368 #define USB_DOEPCTL0_SET_ODD_FR_BITS 29:29
2369 #define USB_DOEPCTL0_SET_ODD_FR_SET 0x20000000
2370 #define USB_DOEPCTL0_SET_ODD_FR_CLR 0xdfffffff
2371 #define USB_DOEPCTL0_SET_ODD_FR_MSB 29
2372 #define USB_DOEPCTL0_SET_ODD_FR_LSB 29
2373 #define USB_DOEPCTL0_SET_ODD_FR_RESET 0x0
2374 #define USB_DOEPCTL0_SET_D0_PID_BITS 28:28
2375 #define USB_DOEPCTL0_SET_D0_PID_SET 0x10000000
2376 #define USB_DOEPCTL0_SET_D0_PID_CLR 0xefffffff
2377 #define USB_DOEPCTL0_SET_D0_PID_MSB 28
2378 #define USB_DOEPCTL0_SET_D0_PID_LSB 28
2379 #define USB_DOEPCTL0_SET_D0_PID_RESET 0x0
2380 #define USB_DOEPCTL0_SET_EVEN_FR_BITS 28:28
2381 #define USB_DOEPCTL0_SET_EVEN_FR_SET 0x10000000
2382 #define USB_DOEPCTL0_SET_EVEN_FR_CLR 0xefffffff
2383 #define USB_DOEPCTL0_SET_EVEN_FR_MSB 28
2384 #define USB_DOEPCTL0_SET_EVEN_FR_LSB 28
2385 #define USB_DOEPCTL0_SET_EVEN_FR_RESET 0x0
2386 #define USB_DOEPCTL0_SNAK_BITS 27:27
2387 #define USB_DOEPCTL0_SNAK_SET 0x08000000
2388 #define USB_DOEPCTL0_SNAK_CLR 0xf7ffffff
2389 #define USB_DOEPCTL0_SNAK_MSB 27
2390 #define USB_DOEPCTL0_SNAK_LSB 27
2391 #define USB_DOEPCTL0_SNAK_RESET 0x0
2392 #define USB_DOEPCTL0_CNAK_BITS 26:26
2393 #define USB_DOEPCTL0_CNAK_SET 0x04000000
2394 #define USB_DOEPCTL0_CNAK_CLR 0xfbffffff
2395 #define USB_DOEPCTL0_CNAK_MSB 26
2396 #define USB_DOEPCTL0_CNAK_LSB 26
2397 #define USB_DOEPCTL0_CNAK_RESET 0x0
2398 #define USB_DOEPCTL0_TXF_NUM_BITS 25:22
2399 #define USB_DOEPCTL0_TXF_NUM_SET 0x03c00000
2400 #define USB_DOEPCTL0_TXF_NUM_CLR 0xfc3fffff
2401 #define USB_DOEPCTL0_TXF_NUM_MSB 25
2402 #define USB_DOEPCTL0_TXF_NUM_LSB 22
2403 #define USB_DOEPCTL0_TXF_NUM_RESET 0x0
2404 #define USB_DOEPCTL0_STALL_BITS 21:21
2405 #define USB_DOEPCTL0_STALL_SET 0x00200000
2406 #define USB_DOEPCTL0_STALL_CLR 0xffdfffff
2407 #define USB_DOEPCTL0_STALL_MSB 21
2408 #define USB_DOEPCTL0_STALL_LSB 21
2409 #define USB_DOEPCTL0_STALL_RESET 0x0
2410 #define USB_DOEPCTL0_SNP_BITS 20:20
2411 #define USB_DOEPCTL0_SNP_SET 0x00100000
2412 #define USB_DOEPCTL0_SNP_CLR 0xffefffff
2413 #define USB_DOEPCTL0_SNP_MSB 20
2414 #define USB_DOEPCTL0_SNP_LSB 20
2415 #define USB_DOEPCTL0_SNP_RESET 0x0
2416 #define USB_DOEPCTL0_TYPE_BITS 19:18
2417 #define USB_DOEPCTL0_TYPE_SET 0x000c0000
2418 #define USB_DOEPCTL0_TYPE_CLR 0xfff3ffff
2419 #define USB_DOEPCTL0_TYPE_MSB 19
2420 #define USB_DOEPCTL0_TYPE_LSB 18
2421 #define USB_DOEPCTL0_TYPE_RESET 0x0
2422 #define USB_DOEPCTL0_NAK_STS_BITS 17:17
2423 #define USB_DOEPCTL0_NAK_STS_SET 0x00020000
2424 #define USB_DOEPCTL0_NAK_STS_CLR 0xfffdffff
2425 #define USB_DOEPCTL0_NAK_STS_MSB 17
2426 #define USB_DOEPCTL0_NAK_STS_LSB 17
2427 #define USB_DOEPCTL0_NAK_STS_RESET 0x0
2428 #define USB_DOEPCTL0_DPID_BITS 16:16
2429 #define USB_DOEPCTL0_DPID_SET 0x00010000
2430 #define USB_DOEPCTL0_DPID_CLR 0xfffeffff
2431 #define USB_DOEPCTL0_DPID_MSB 16
2432 #define USB_DOEPCTL0_DPID_LSB 16
2433 #define USB_DOEPCTL0_DPID_RESET 0x0
2434 #define USB_DOEPCTL0_EO_FR_NUM_BITS 16:16
2435 #define USB_DOEPCTL0_EO_FR_NUM_SET 0x00010000
2436 #define USB_DOEPCTL0_EO_FR_NUM_CLR 0xfffeffff
2437 #define USB_DOEPCTL0_EO_FR_NUM_MSB 16
2438 #define USB_DOEPCTL0_EO_FR_NUM_LSB 16
2439 #define USB_DOEPCTL0_EO_FR_NUM_RESET 0x0
2440 #define USB_DOEPCTL0_USB_ACT_EP_BITS 15:15
2441 #define USB_DOEPCTL0_USB_ACT_EP_SET 0x00008000
2442 #define USB_DOEPCTL0_USB_ACT_EP_CLR 0xffff7fff
2443 #define USB_DOEPCTL0_USB_ACT_EP_MSB 15
2444 #define USB_DOEPCTL0_USB_ACT_EP_LSB 15
2445 #define USB_DOEPCTL0_USB_ACT_EP_RESET 0x0
2446 #define USB_DOEPCTL0_NEXT_EP_BITS 14:11
2447 #define USB_DOEPCTL0_NEXT_EP_SET 0x00007800
2448 #define USB_DOEPCTL0_NEXT_EP_CLR 0xffff87ff
2449 #define USB_DOEPCTL0_NEXT_EP_MSB 14
2450 #define USB_DOEPCTL0_NEXT_EP_LSB 11
2451 #define USB_DOEPCTL0_NEXT_EP_RESET 0x0
2452 #define USB_DOEPCTL0_MPS_BITS 10:0
2453 #define USB_DOEPCTL0_MPS_SET 0x000007ff
2454 #define USB_DOEPCTL0_MPS_CLR 0xfffff800
2455 #define USB_DOEPCTL0_MPS_MSB 10
2456 #define USB_DOEPCTL0_MPS_LSB 0
2457 #define USB_DOEPCTL0_MPS_RESET 0x0
2458 #define USB_DOEPINT0 HW_REGISTER_RW( 0x7e980b08 )
2459 #define USB_DOEPINT0_MASK 0xffffffff
2460 #define USB_DOEPINT0_WIDTH 32
2461 #define USB_DOEPINT0_BNA_BITS 9:9
2462 #define USB_DOEPINT0_BNA_SET 0x00000200
2463 #define USB_DOEPINT0_BNA_CLR 0xfffffdff
2464 #define USB_DOEPINT0_BNA_MSB 9
2465 #define USB_DOEPINT0_BNA_LSB 9
2466 #define USB_DOEPINT0_BNA_RESET 0x0
2467 #define USB_DOEPINT0_TX_FIFO_UNDRN_BITS 8:8
2468 #define USB_DOEPINT0_TX_FIFO_UNDRN_SET 0x00000100
2469 #define USB_DOEPINT0_TX_FIFO_UNDRN_CLR 0xfffffeff
2470 #define USB_DOEPINT0_TX_FIFO_UNDRN_MSB 8
2471 #define USB_DOEPINT0_TX_FIFO_UNDRN_LSB 8
2472 #define USB_DOEPINT0_TX_FIFO_UNDRN_RESET 0x0
2473 #define USB_DOEPINT0_OUT_PKT_ERR_BITS 8:8
2474 #define USB_DOEPINT0_OUT_PKT_ERR_SET 0x00000100
2475 #define USB_DOEPINT0_OUT_PKT_ERR_CLR 0xfffffeff
2476 #define USB_DOEPINT0_OUT_PKT_ERR_MSB 8
2477 #define USB_DOEPINT0_OUT_PKT_ERR_LSB 8
2478 #define USB_DOEPINT0_OUT_PKT_ERR_RESET 0x0
2479 #define USB_DOEPINT0_TXF_EMPTY_BITS 7:7
2480 #define USB_DOEPINT0_TXF_EMPTY_SET 0x00000080
2481 #define USB_DOEPINT0_TXF_EMPTY_CLR 0xffffff7f
2482 #define USB_DOEPINT0_TXF_EMPTY_MSB 7
2483 #define USB_DOEPINT0_TXF_EMPTY_LSB 7
2484 #define USB_DOEPINT0_TXF_EMPTY_RESET 0x0
2485 #define USB_DOEPINT0_IN_EP_NAK_EFF_BITS 6:6
2486 #define USB_DOEPINT0_IN_EP_NAK_EFF_SET 0x00000040
2487 #define USB_DOEPINT0_IN_EP_NAK_EFF_CLR 0xffffffbf
2488 #define USB_DOEPINT0_IN_EP_NAK_EFF_MSB 6
2489 #define USB_DOEPINT0_IN_EP_NAK_EFF_LSB 6
2490 #define USB_DOEPINT0_IN_EP_NAK_EFF_RESET 0x0
2491 #define USB_DOEPINT0_BACK2BACK_SETUP_BITS 6:6
2492 #define USB_DOEPINT0_BACK2BACK_SETUP_SET 0x00000040
2493 #define USB_DOEPINT0_BACK2BACK_SETUP_CLR 0xffffffbf
2494 #define USB_DOEPINT0_BACK2BACK_SETUP_MSB 6
2495 #define USB_DOEPINT0_BACK2BACK_SETUP_LSB 6
2496 #define USB_DOEPINT0_BACK2BACK_SETUP_RESET 0x0
2497 #define USB_DOEPINT0_IN_TKN_EP_MIS_BITS 5:5
2498 #define USB_DOEPINT0_IN_TKN_EP_MIS_SET 0x00000020
2499 #define USB_DOEPINT0_IN_TKN_EP_MIS_CLR 0xffffffdf
2500 #define USB_DOEPINT0_IN_TKN_EP_MIS_MSB 5
2501 #define USB_DOEPINT0_IN_TKN_EP_MIS_LSB 5
2502 #define USB_DOEPINT0_IN_TKN_EP_MIS_RESET 0x0
2503 #define USB_DOEPINT0_STS_PHSE_RCVD_BITS 5:5
2504 #define USB_DOEPINT0_STS_PHSE_RCVD_SET 0x00000020
2505 #define USB_DOEPINT0_STS_PHSE_RCVD_CLR 0xffffffdf
2506 #define USB_DOEPINT0_STS_PHSE_RCVD_MSB 5
2507 #define USB_DOEPINT0_STS_PHSE_RCVD_LSB 5
2508 #define USB_DOEPINT0_STS_PHSE_RCVD_RESET 0x0
2509 #define USB_DOEPINT0_IN_TKN_TXFEMP_BITS 4:4
2510 #define USB_DOEPINT0_IN_TKN_TXFEMP_SET 0x00000010
2511 #define USB_DOEPINT0_IN_TKN_TXFEMP_CLR 0xffffffef
2512 #define USB_DOEPINT0_IN_TKN_TXFEMP_MSB 4
2513 #define USB_DOEPINT0_IN_TKN_TXFEMP_LSB 4
2514 #define USB_DOEPINT0_IN_TKN_TXFEMP_RESET 0x0
2515 #define USB_DOEPINT0_OUT_TKN_EP_DIS_BITS 4:4
2516 #define USB_DOEPINT0_OUT_TKN_EP_DIS_SET 0x00000010
2517 #define USB_DOEPINT0_OUT_TKN_EP_DIS_CLR 0xffffffef
2518 #define USB_DOEPINT0_OUT_TKN_EP_DIS_MSB 4
2519 #define USB_DOEPINT0_OUT_TKN_EP_DIS_LSB 4
2520 #define USB_DOEPINT0_OUT_TKN_EP_DIS_RESET 0x0
2521 #define USB_DOEPINT0_TIMEOUT_BITS 3:3
2522 #define USB_DOEPINT0_TIMEOUT_SET 0x00000008
2523 #define USB_DOEPINT0_TIMEOUT_CLR 0xfffffff7
2524 #define USB_DOEPINT0_TIMEOUT_MSB 3
2525 #define USB_DOEPINT0_TIMEOUT_LSB 3
2526 #define USB_DOEPINT0_TIMEOUT_RESET 0x0
2527 #define USB_DOEPINT0_SETUP_BITS 3:3
2528 #define USB_DOEPINT0_SETUP_SET 0x00000008
2529 #define USB_DOEPINT0_SETUP_CLR 0xfffffff7
2530 #define USB_DOEPINT0_SETUP_MSB 3
2531 #define USB_DOEPINT0_SETUP_LSB 3
2532 #define USB_DOEPINT0_SETUP_RESET 0x0
2533 #define USB_DOEPINT0_AHB_ERR_BITS 2:2
2534 #define USB_DOEPINT0_AHB_ERR_SET 0x00000004
2535 #define USB_DOEPINT0_AHB_ERR_CLR 0xfffffffb
2536 #define USB_DOEPINT0_AHB_ERR_MSB 2
2537 #define USB_DOEPINT0_AHB_ERR_LSB 2
2538 #define USB_DOEPINT0_AHB_ERR_RESET 0x0
2539 #define USB_DOEPINT0_EP_DISBLD_BITS 1:1
2540 #define USB_DOEPINT0_EP_DISBLD_SET 0x00000002
2541 #define USB_DOEPINT0_EP_DISBLD_CLR 0xfffffffd
2542 #define USB_DOEPINT0_EP_DISBLD_MSB 1
2543 #define USB_DOEPINT0_EP_DISBLD_LSB 1
2544 #define USB_DOEPINT0_EP_DISBLD_RESET 0x0
2545 #define USB_DOEPINT0_XFER_COMPL_BITS 0:0
2546 #define USB_DOEPINT0_XFER_COMPL_SET 0x00000001
2547 #define USB_DOEPINT0_XFER_COMPL_CLR 0xfffffffe
2548 #define USB_DOEPINT0_XFER_COMPL_MSB 0
2549 #define USB_DOEPINT0_XFER_COMPL_LSB 0
2550 #define USB_DOEPINT0_XFER_COMPL_RESET 0x0
2551 #define USB_DOEPTSIZ0 HW_REGISTER_RW( 0x7e980b10 )
2552 #define USB_DOEPTSIZ0_MASK 0xffffffff
2553 #define USB_DOEPTSIZ0_WIDTH 32
2554 #define USB_DOEPTSIZ0_SUP_CNT_BITS 30:29
2555 #define USB_DOEPTSIZ0_SUP_CNT_SET 0x60000000
2556 #define USB_DOEPTSIZ0_SUP_CNT_CLR 0x9fffffff
2557 #define USB_DOEPTSIZ0_SUP_CNT_MSB 30
2558 #define USB_DOEPTSIZ0_SUP_CNT_LSB 29
2559 #define USB_DOEPTSIZ0_SUP_CNT_RESET 0x0
2560 #define USB_DOEPTSIZ0_RX_DPID_BITS 30:29
2561 #define USB_DOEPTSIZ0_RX_DPID_SET 0x60000000
2562 #define USB_DOEPTSIZ0_RX_DPID_CLR 0x9fffffff
2563 #define USB_DOEPTSIZ0_RX_DPID_MSB 30
2564 #define USB_DOEPTSIZ0_RX_DPID_LSB 29
2565 #define USB_DOEPTSIZ0_RX_DPID_RESET 0x0
2566 #define USB_DOEPTSIZ0_MC_BITS 30:29
2567 #define USB_DOEPTSIZ0_MC_SET 0x60000000
2568 #define USB_DOEPTSIZ0_MC_CLR 0x9fffffff
2569 #define USB_DOEPTSIZ0_MC_MSB 30
2570 #define USB_DOEPTSIZ0_MC_LSB 29
2571 #define USB_DOEPTSIZ0_MC_RESET 0x0
2572 #define USB_DOEPTSIZ0_PKT_CNT_BITS 28:19
2573 #define USB_DOEPTSIZ0_PKT_CNT_SET 0x1ff80000
2574 #define USB_DOEPTSIZ0_PKT_CNT_CLR 0xe007ffff
2575 #define USB_DOEPTSIZ0_PKT_CNT_MSB 28
2576 #define USB_DOEPTSIZ0_PKT_CNT_LSB 19
2577 #define USB_DOEPTSIZ0_PKT_CNT_RESET 0x0
2578 #define USB_DOEPTSIZ0_XFERSIZE_BITS 18:0
2579 #define USB_DOEPTSIZ0_XFERSIZE_SET 0x0007ffff
2580 #define USB_DOEPTSIZ0_XFERSIZE_CLR 0xfff80000
2581 #define USB_DOEPTSIZ0_XFERSIZE_MSB 18
2582 #define USB_DOEPTSIZ0_XFERSIZE_LSB 0
2583 #define USB_DOEPTSIZ0_XFERSIZE_RESET 0x0
2584 #define USB_DOEPDMA0 HW_REGISTER_RW( 0x7e980b14 )
2585 #define USB_DOEPDMA0_MASK 0xffffffff
2586 #define USB_DOEPDMA0_WIDTH 32
2587 #define USB_DOEPDMAB0 HW_REGISTER_RW( 0x7e980b1c )
2588 #define USB_DOEPDMAB0_MASK 0xffffffff
2589 #define USB_DOEPDMAB0_WIDTH 32
2590 #define USB_DOEPCTL1 HW_REGISTER_RW( 0x7e980b20 )
2591 #define USB_DOEPCTL1_MASK 0xffffffff
2592 #define USB_DOEPCTL1_WIDTH 32
2593 #define USB_DOEPINT1 HW_REGISTER_RW( 0x7e980b28 )
2594 #define USB_DOEPINT1_MASK 0xffffffff
2595 #define USB_DOEPINT1_WIDTH 32
2596 #define USB_DOEPTSIZ1 HW_REGISTER_RW( 0x7e980b30 )
2597 #define USB_DOEPTSIZ1_MASK 0xffffffff
2598 #define USB_DOEPTSIZ1_WIDTH 32
2599 #define USB_DOEPDMA1 HW_REGISTER_RW( 0x7e980b34 )
2600 #define USB_DOEPDMA1_MASK 0xffffffff
2601 #define USB_DOEPDMA1_WIDTH 32
2602 #define USB_DOEPDMAB1 HW_REGISTER_RW( 0x7e980b1c )
2603 #define USB_DOEPDMAB1_MASK 0xffffffff
2604 #define USB_DOEPDMAB1_WIDTH 32
2605 #define USB_DOEPCTL2 HW_REGISTER_RW( 0x7e980b40 )
2606 #define USB_DOEPCTL2_MASK 0xffffffff
2607 #define USB_DOEPCTL2_WIDTH 32
2608 #define USB_DOEPINT2 HW_REGISTER_RW( 0x7e980b48 )
2609 #define USB_DOEPINT2_MASK 0xffffffff
2610 #define USB_DOEPINT2_WIDTH 32
2611 #define USB_DOEPTSIZ2 HW_REGISTER_RW( 0x7e980b50 )
2612 #define USB_DOEPTSIZ2_MASK 0xffffffff
2613 #define USB_DOEPTSIZ2_WIDTH 32
2614 #define USB_DOEPDMA2 HW_REGISTER_RW( 0x7e980b54 )
2615 #define USB_DOEPDMA2_MASK 0xffffffff
2616 #define USB_DOEPDMA2_WIDTH 32
2617 #define USB_DOEPDMAB2 HW_REGISTER_RW( 0x7e980b1c )
2618 #define USB_DOEPDMAB2_MASK 0xffffffff
2619 #define USB_DOEPDMAB2_WIDTH 32
2620 #define USB_DOEPCTL3 HW_REGISTER_RW( 0x7e980b60 )
2621 #define USB_DOEPCTL3_MASK 0xffffffff
2622 #define USB_DOEPCTL3_WIDTH 32
2623 #define USB_DOEPINT3 HW_REGISTER_RW( 0x7e980b68 )
2624 #define USB_DOEPINT3_MASK 0xffffffff
2625 #define USB_DOEPINT3_WIDTH 32
2626 #define USB_DOEPTSIZ3 HW_REGISTER_RW( 0x7e980b70 )
2627 #define USB_DOEPTSIZ3_MASK 0xffffffff
2628 #define USB_DOEPTSIZ3_WIDTH 32
2629 #define USB_DOEPDMA3 HW_REGISTER_RW( 0x7e980b74 )
2630 #define USB_DOEPDMA3_MASK 0xffffffff
2631 #define USB_DOEPDMA3_WIDTH 32
2632 #define USB_DOEPDMAB3 HW_REGISTER_RW( 0x7e980b1c )
2633 #define USB_DOEPDMAB3_MASK 0xffffffff
2634 #define USB_DOEPDMAB3_WIDTH 32
2635 #define USB_DOEPCTL4 HW_REGISTER_RW( 0x7e980b80 )
2636 #define USB_DOEPCTL4_MASK 0xffffffff
2637 #define USB_DOEPCTL4_WIDTH 32
2638 #define USB_DOEPINT4 HW_REGISTER_RW( 0x7e980b88 )
2639 #define USB_DOEPINT4_MASK 0xffffffff
2640 #define USB_DOEPINT4_WIDTH 32
2641 #define USB_DOEPTSIZ4 HW_REGISTER_RW( 0x7e980b90 )
2642 #define USB_DOEPTSIZ4_MASK 0xffffffff
2643 #define USB_DOEPTSIZ4_WIDTH 32
2644 #define USB_DOEPDMA4 HW_REGISTER_RW( 0x7e980b94 )
2645 #define USB_DOEPDMA4_MASK 0xffffffff
2646 #define USB_DOEPDMA4_WIDTH 32
2647 #define USB_DOEPDMAB4 HW_REGISTER_RW( 0x7e980b1c )
2648 #define USB_DOEPDMAB4_MASK 0xffffffff
2649 #define USB_DOEPDMAB4_WIDTH 32
2650 #define USB_DOEPCTL5 HW_REGISTER_RW( 0x7e980ba0 )
2651 #define USB_DOEPCTL5_MASK 0xffffffff
2652 #define USB_DOEPCTL5_WIDTH 32
2653 #define USB_DOEPINT5 HW_REGISTER_RW( 0x7e980ba8 )
2654 #define USB_DOEPINT5_MASK 0xffffffff
2655 #define USB_DOEPINT5_WIDTH 32
2656 #define USB_DOEPTSIZ5 HW_REGISTER_RW( 0x7e980bb0 )
2657 #define USB_DOEPTSIZ5_MASK 0xffffffff
2658 #define USB_DOEPTSIZ5_WIDTH 32
2659 #define USB_DOEPDMA5 HW_REGISTER_RW( 0x7e980bb4 )
2660 #define USB_DOEPDMA5_MASK 0xffffffff
2661 #define USB_DOEPDMA5_WIDTH 32
2662 #define USB_DOEPDMAB5 HW_REGISTER_RW( 0x7e980b1c )
2663 #define USB_DOEPDMAB5_MASK 0xffffffff
2664 #define USB_DOEPDMAB5_WIDTH 32
2665 #define USB_DOEPCTL6 HW_REGISTER_RW( 0x7e980bc0 )
2666 #define USB_DOEPCTL6_MASK 0xffffffff
2667 #define USB_DOEPCTL6_WIDTH 32
2668 #define USB_DOEPINT6 HW_REGISTER_RW( 0x7e980bc8 )
2669 #define USB_DOEPINT6_MASK 0xffffffff
2670 #define USB_DOEPINT6_WIDTH 32
2671 #define USB_DOEPTSIZ6 HW_REGISTER_RW( 0x7e980bd0 )
2672 #define USB_DOEPTSIZ6_MASK 0xffffffff
2673 #define USB_DOEPTSIZ6_WIDTH 32
2674 #define USB_DOEPDMA6 HW_REGISTER_RW( 0x7e980bd4 )
2675 #define USB_DOEPDMA6_MASK 0xffffffff
2676 #define USB_DOEPDMA6_WIDTH 32
2677 #define USB_DOEPDMAB6 HW_REGISTER_RW( 0x7e980b1c )
2678 #define USB_DOEPDMAB6_MASK 0xffffffff
2679 #define USB_DOEPDMAB6_WIDTH 32
2680 #define USB_DOEPCTL7 HW_REGISTER_RW( 0x7e980be0 )
2681 #define USB_DOEPCTL7_MASK 0xffffffff
2682 #define USB_DOEPCTL7_WIDTH 32
2683 #define USB_DOEPINT7 HW_REGISTER_RW( 0x7e980be8 )
2684 #define USB_DOEPINT7_MASK 0xffffffff
2685 #define USB_DOEPINT7_WIDTH 32
2686 #define USB_DOEPTSIZ7 HW_REGISTER_RW( 0x7e980bf0 )
2687 #define USB_DOEPTSIZ7_MASK 0xffffffff
2688 #define USB_DOEPTSIZ7_WIDTH 32
2689 #define USB_DOEPDMA7 HW_REGISTER_RW( 0x7e980bf4 )
2690 #define USB_DOEPDMA7_MASK 0xffffffff
2691 #define USB_DOEPDMA7_WIDTH 32
2692 #define USB_DOEPDMAB7 HW_REGISTER_RW( 0x7e980b1c )
2693 #define USB_DOEPDMAB7_MASK 0xffffffff
2694 #define USB_DOEPDMAB7_WIDTH 32
2695 #define USB_DOEPCTL8 HW_REGISTER_RW( 0x7e980c00 )
2696 #define USB_DOEPCTL8_MASK 0xffffffff
2697 #define USB_DOEPCTL8_WIDTH 32
2698 #define USB_DOEPINT8 HW_REGISTER_RW( 0x7e980c08 )
2699 #define USB_DOEPINT8_MASK 0xffffffff
2700 #define USB_DOEPINT8_WIDTH 32
2701 #define USB_DOEPTSIZ8 HW_REGISTER_RW( 0x7e980c10 )
2702 #define USB_DOEPTSIZ8_MASK 0xffffffff
2703 #define USB_DOEPTSIZ8_WIDTH 32
2704 #define USB_DOEPDMA8 HW_REGISTER_RW( 0x7e980c14 )
2705 #define USB_DOEPDMA8_MASK 0xffffffff
2706 #define USB_DOEPDMA8_WIDTH 32
2707 #define USB_DOEPDMAB8 HW_REGISTER_RW( 0x7e980b1c )
2708 #define USB_DOEPDMAB8_MASK 0xffffffff
2709 #define USB_DOEPDMAB8_WIDTH 32
2710 #define USB_DOEPCTL9 HW_REGISTER_RW( 0x7e980c20 )
2711 #define USB_DOEPCTL9_MASK 0xffffffff
2712 #define USB_DOEPCTL9_WIDTH 32
2713 #define USB_DOEPINT9 HW_REGISTER_RW( 0x7e980c28 )
2714 #define USB_DOEPINT9_MASK 0xffffffff
2715 #define USB_DOEPINT9_WIDTH 32
2716 #define USB_DOEPTSIZ9 HW_REGISTER_RW( 0x7e980c30 )
2717 #define USB_DOEPTSIZ9_MASK 0xffffffff
2718 #define USB_DOEPTSIZ9_WIDTH 32
2719 #define USB_DOEPDMA9 HW_REGISTER_RW( 0x7e980c34 )
2720 #define USB_DOEPDMA9_MASK 0xffffffff
2721 #define USB_DOEPDMA9_WIDTH 32
2722 #define USB_DOEPDMAB9 HW_REGISTER_RW( 0x7e980b1c )
2723 #define USB_DOEPDMAB9_MASK 0xffffffff
2724 #define USB_DOEPDMAB9_WIDTH 32
2725 #define USB_DOEPCTL10 HW_REGISTER_RW( 0x7e980c40 )
2726 #define USB_DOEPCTL10_MASK 0xffffffff
2727 #define USB_DOEPCTL10_WIDTH 32
2728 #define USB_DOEPINT10 HW_REGISTER_RW( 0x7e980c48 )
2729 #define USB_DOEPINT10_MASK 0xffffffff
2730 #define USB_DOEPINT10_WIDTH 32
2731 #define USB_DOEPTSIZ10 HW_REGISTER_RW( 0x7e980c50 )
2732 #define USB_DOEPTSIZ10_MASK 0xffffffff
2733 #define USB_DOEPTSIZ10_WIDTH 32
2734 #define USB_DOEPDMA10 HW_REGISTER_RW( 0x7e980c54 )
2735 #define USB_DOEPDMA10_MASK 0xffffffff
2736 #define USB_DOEPDMA10_WIDTH 32
2737 #define USB_DOEPDMAB10 HW_REGISTER_RW( 0x7e980b1c )
2738 #define USB_DOEPDMAB10_MASK 0xffffffff
2739 #define USB_DOEPDMAB10_WIDTH 32
2740 #define USB_DOEPCTL11 HW_REGISTER_RW( 0x7e980c60 )
2741 #define USB_DOEPCTL11_MASK 0xffffffff
2742 #define USB_DOEPCTL11_WIDTH 32
2743 #define USB_DOEPINT11 HW_REGISTER_RW( 0x7e980c68 )
2744 #define USB_DOEPINT11_MASK 0xffffffff
2745 #define USB_DOEPINT11_WIDTH 32
2746 #define USB_DOEPTSIZ11 HW_REGISTER_RW( 0x7e980c70 )
2747 #define USB_DOEPTSIZ11_MASK 0xffffffff
2748 #define USB_DOEPTSIZ11_WIDTH 32
2749 #define USB_DOEPDMA11 HW_REGISTER_RW( 0x7e980c74 )
2750 #define USB_DOEPDMA11_MASK 0xffffffff
2751 #define USB_DOEPDMA11_WIDTH 32
2752 #define USB_DOEPDMAB11 HW_REGISTER_RW( 0x7e980b1c )
2753 #define USB_DOEPDMAB11_MASK 0xffffffff
2754 #define USB_DOEPDMAB11_WIDTH 32
2755 #define USB_DOEPCTL12 HW_REGISTER_RW( 0x7e980c80 )
2756 #define USB_DOEPCTL12_MASK 0xffffffff
2757 #define USB_DOEPCTL12_WIDTH 32
2758 #define USB_DOEPINT12 HW_REGISTER_RW( 0x7e980c88 )
2759 #define USB_DOEPINT12_MASK 0xffffffff
2760 #define USB_DOEPINT12_WIDTH 32
2761 #define USB_DOEPTSIZ12 HW_REGISTER_RW( 0x7e980c90 )
2762 #define USB_DOEPTSIZ12_MASK 0xffffffff
2763 #define USB_DOEPTSIZ12_WIDTH 32
2764 #define USB_DOEPDMA12 HW_REGISTER_RW( 0x7e980c94 )
2765 #define USB_DOEPDMA12_MASK 0xffffffff
2766 #define USB_DOEPDMA12_WIDTH 32
2767 #define USB_DOEPDMAB12 HW_REGISTER_RW( 0x7e980b1c )
2768 #define USB_DOEPDMAB12_MASK 0xffffffff
2769 #define USB_DOEPDMAB12_WIDTH 32
2770 #define USB_DOEPCTL13 HW_REGISTER_RW( 0x7e980ca0 )
2771 #define USB_DOEPCTL13_MASK 0xffffffff
2772 #define USB_DOEPCTL13_WIDTH 32
2773 #define USB_DOEPINT13 HW_REGISTER_RW( 0x7e980ca8 )
2774 #define USB_DOEPINT13_MASK 0xffffffff
2775 #define USB_DOEPINT13_WIDTH 32
2776 #define USB_DOEPTSIZ13 HW_REGISTER_RW( 0x7e980cb0 )
2777 #define USB_DOEPTSIZ13_MASK 0xffffffff
2778 #define USB_DOEPTSIZ13_WIDTH 32
2779 #define USB_DOEPDMA13 HW_REGISTER_RW( 0x7e980cb4 )
2780 #define USB_DOEPDMA13_MASK 0xffffffff
2781 #define USB_DOEPDMA13_WIDTH 32
2782 #define USB_DOEPDMAB13 HW_REGISTER_RW( 0x7e980b1c )
2783 #define USB_DOEPDMAB13_MASK 0xffffffff
2784 #define USB_DOEPDMAB13_WIDTH 32
2785 #define USB_DOEPCTL14 HW_REGISTER_RW( 0x7e980cc0 )
2786 #define USB_DOEPCTL14_MASK 0xffffffff
2787 #define USB_DOEPCTL14_WIDTH 32
2788 #define USB_DOEPINT14 HW_REGISTER_RW( 0x7e980cc8 )
2789 #define USB_DOEPINT14_MASK 0xffffffff
2790 #define USB_DOEPINT14_WIDTH 32
2791 #define USB_DOEPTSIZ14 HW_REGISTER_RW( 0x7e980cd0 )
2792 #define USB_DOEPTSIZ14_MASK 0xffffffff
2793 #define USB_DOEPTSIZ14_WIDTH 32
2794 #define USB_DOEPDMA14 HW_REGISTER_RW( 0x7e980cd4 )
2795 #define USB_DOEPDMA14_MASK 0xffffffff
2796 #define USB_DOEPDMA14_WIDTH 32
2797 #define USB_DOEPDMAB14 HW_REGISTER_RW( 0x7e980b1c )
2798 #define USB_DOEPDMAB14_MASK 0xffffffff
2799 #define USB_DOEPDMAB14_WIDTH 32
2800 #define USB_DOEPCTL15 HW_REGISTER_RW( 0x7e980ce0 )
2801 #define USB_DOEPCTL15_MASK 0xffffffff
2802 #define USB_DOEPCTL15_WIDTH 32
2803 #define USB_DOEPINT15 HW_REGISTER_RW( 0x7e980ce8 )
2804 #define USB_DOEPINT15_MASK 0xffffffff
2805 #define USB_DOEPINT15_WIDTH 32
2806 #define USB_DOEPTSIZ15 HW_REGISTER_RW( 0x7e980cf0 )
2807 #define USB_DOEPTSIZ15_MASK 0xffffffff
2808 #define USB_DOEPTSIZ15_WIDTH 32
2809 #define USB_DOEPDMA15 HW_REGISTER_RW( 0x7e980cf4 )
2810 #define USB_DOEPDMA15_MASK 0xffffffff
2811 #define USB_DOEPDMA15_WIDTH 32
2812 #define USB_DOEPDMAB15 HW_REGISTER_RW( 0x7e980b1c )
2813 #define USB_DOEPDMAB15_MASK 0xffffffff
2814 #define USB_DOEPDMAB15_WIDTH 32
2815 #define USB_PCGCR HW_REGISTER_RW( 0x7e980e00 )
2816 #define USB_PCGCR_MASK 0x0000000f
2817 #define USB_PCGCR_WIDTH 4
2818 #define USB_PCGCR_RST_PDWN_MODULE_BITS 3:3
2819 #define USB_PCGCR_RST_PDWN_MODULE_SET 0x00000008
2820 #define USB_PCGCR_RST_PDWN_MODULE_CLR 0xfffffff7
2821 #define USB_PCGCR_RST_PDWN_MODULE_MSB 3
2822 #define USB_PCGCR_RST_PDWN_MODULE_LSB 3
2823 #define USB_PCGCR_RST_PDWN_MODULE_RESET 0x0
2824 #define USB_PCGCR_PWR_CLMP_BITS 2:2
2825 #define USB_PCGCR_PWR_CLMP_SET 0x00000004
2826 #define USB_PCGCR_PWR_CLMP_CLR 0xfffffffb
2827 #define USB_PCGCR_PWR_CLMP_MSB 2
2828 #define USB_PCGCR_PWR_CLMP_LSB 2
2829 #define USB_PCGCR_PWR_CLMP_RESET 0x0
2830 #define USB_PCGCR_GATE_HCLK_BITS 1:1
2831 #define USB_PCGCR_GATE_HCLK_SET 0x00000002
2832 #define USB_PCGCR_GATE_HCLK_CLR 0xfffffffd
2833 #define USB_PCGCR_GATE_HCLK_MSB 1
2834 #define USB_PCGCR_GATE_HCLK_LSB 1
2835 #define USB_PCGCR_GATE_HCLK_RESET 0x0
2836 #define USB_PCGCR_STOP_PCLK_BITS 0:0
2837 #define USB_PCGCR_STOP_PCLK_SET 0x00000001
2838 #define USB_PCGCR_STOP_PCLK_CLR 0xfffffffe
2839 #define USB_PCGCR_STOP_PCLK_MSB 0
2840 #define USB_PCGCR_STOP_PCLK_LSB 0
2841 #define USB_PCGCR_STOP_PCLK_RESET 0x0
2842 #define USB_DFIFO0 HW_REGISTER_RW( 0x7e981000 )
2843 #define USB_DFIFO0_MASK 0xffffffff
2844 #define USB_DFIFO0_WIDTH 32
2845 #define USB_DFIFO1 HW_REGISTER_RW( 0x7e982000 )
2846 #define USB_DFIFO1_MASK 0xffffffff
2847 #define USB_DFIFO1_WIDTH 32
2848 #define USB_DFIFO2 HW_REGISTER_RW( 0x7e983000 )
2849 #define USB_DFIFO2_MASK 0xffffffff
2850 #define USB_DFIFO2_WIDTH 32
2851 #define USB_DFIFO3 HW_REGISTER_RW( 0x7e984000 )
2852 #define USB_DFIFO3_MASK 0xffffffff
2853 #define USB_DFIFO3_WIDTH 32
2854 #define USB_DFIFO4 HW_REGISTER_RW( 0x7e985000 )
2855 #define USB_DFIFO4_MASK 0xffffffff
2856 #define USB_DFIFO4_WIDTH 32
2857 #define USB_DFIFO5 HW_REGISTER_RW( 0x7e986000 )
2858 #define USB_DFIFO5_MASK 0xffffffff
2859 #define USB_DFIFO5_WIDTH 32
2860 #define USB_DFIFO6 HW_REGISTER_RW( 0x7e987000 )
2861 #define USB_DFIFO6_MASK 0xffffffff
2862 #define USB_DFIFO6_WIDTH 32
2863 #define USB_DFIFO7 HW_REGISTER_RW( 0x7e988000 )
2864 #define USB_DFIFO7_MASK 0xffffffff
2865 #define USB_DFIFO7_WIDTH 32
2866 #define USB_DFIFO8 HW_REGISTER_RW( 0x7e989000 )
2867 #define USB_DFIFO8_MASK 0xffffffff
2868 #define USB_DFIFO8_WIDTH 32
2869 #define USB_DFIFO9 HW_REGISTER_RW( 0x7e98a000 )
2870 #define USB_DFIFO9_MASK 0xffffffff
2871 #define USB_DFIFO9_WIDTH 32
2872 #define USB_DFIFO10 HW_REGISTER_RW( 0x7e98b000 )
2873 #define USB_DFIFO10_MASK 0xffffffff
2874 #define USB_DFIFO10_WIDTH 32
2875 #define USB_DFIFO11 HW_REGISTER_RW( 0x7e98c000 )
2876 #define USB_DFIFO11_MASK 0xffffffff
2877 #define USB_DFIFO11_WIDTH 32
2878 #define USB_DFIFO12 HW_REGISTER_RW( 0x7e98d000 )
2879 #define USB_DFIFO12_MASK 0xffffffff
2880 #define USB_DFIFO12_WIDTH 32
2881 #define USB_DFIFO13 HW_REGISTER_RW( 0x7e98e000 )
2882 #define USB_DFIFO13_MASK 0xffffffff
2883 #define USB_DFIFO13_WIDTH 32
2884 #define USB_DFIFO14 HW_REGISTER_RW( 0x7e98f000 )
2885 #define USB_DFIFO14_MASK 0xffffffff
2886 #define USB_DFIFO14_WIDTH 32
2887 #define USB_DFIFO15 HW_REGISTER_RW( 0x7e990000 )
2888 #define USB_DFIFO15_MASK 0xffffffff
2889 #define USB_DFIFO15_WIDTH 32
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