2ee79a97d62ad86285dc65c41978988a5f048001
[rpi-open-firmware.git] / bcm2708_chip / v3d.h
1 // This file was generated by the create_regs script
2 #ifdef ANDROID
3 extern void *regbase;
4 #define V3D_BASE ((unsigned long)regbase)
5 #else // ANDROID
6 #if defined(__CC_ARM) && defined(V3D_INCLUDED)
7 #if defined(_HERA_) || defined(_RHEA_) || defined(_SAMOA_)
8 #define V3D_BASE 0x3c00b000 /* for Hera V3D */
9 #elif defined(_ATHENA_)
10 #define V3D_BASE 0x08950000
11 #else
12 #error "WRONG BASEBAND CHIP!!!"
13 #endif
14 #else
15 #define V3D_BASE 0x7ec00000 /* for VC4 V3D */
16 #endif
17 #endif // ANDROID
18
19 #define V3D_IDENT0 HW_REGISTER_RW( V3D_BASE+0x0000 )
20 #define V3D_IDENT0_MASK 0xffffffff
21 #define V3D_IDENT0_WIDTH 32
22 #define V3D_IDENT1 HW_REGISTER_RW( V3D_BASE+0x0004 )
23 #define V3D_IDENT1_MASK 0xffffffff
24 #define V3D_IDENT1_WIDTH 32
25 #define V3D_IDENT2 HW_REGISTER_RW( V3D_BASE+0x0008 )
26 #define V3D_IDENT2_MASK 0xffffffff
27 #define V3D_IDENT2_WIDTH 32
28 #define V3D_IDENT3 HW_REGISTER_RW( V3D_BASE+0x000c )
29 #define V3D_IDENT3_MASK 0xffffffff
30 #define V3D_IDENT3_WIDTH 32
31 #define V3D_SCRATCH HW_REGISTER_RW( V3D_BASE+0x0010 )
32 #define V3D_SCRATCH_MASK 0xffffffff
33 #define V3D_SCRATCH_WIDTH 32
34 #define V3D_L2CACTL HW_REGISTER_RW( V3D_BASE+0x0020 )
35 #define V3D_L2CACTL_MASK 0xffffffff
36 #define V3D_L2CACTL_WIDTH 32
37 #define V3D_SLCACTL HW_REGISTER_RW( V3D_BASE+0x0024 )
38 #define V3D_SLCACTL_MASK 0xffffffff
39 #define V3D_SLCACTL_WIDTH 32
40 #define V3D_INTCTL HW_REGISTER_RW( V3D_BASE+0x0030 )
41 #define V3D_INTCTL_MASK 0xffffffff
42 #define V3D_INTCTL_WIDTH 32
43 #define V3D_INTENA HW_REGISTER_RW( V3D_BASE+0x0034 )
44 #define V3D_INTENA_MASK 0xffffffff
45 #define V3D_INTENA_WIDTH 32
46 #define V3D_INTDIS HW_REGISTER_RW( V3D_BASE+0x0038 )
47 #define V3D_INTDIS_MASK 0xffffffff
48 #define V3D_INTDIS_WIDTH 32
49 #define V3D_CT0CS HW_REGISTER_RW( V3D_BASE+0x0100 )
50 #define V3D_CT0CS_MASK 0xffffffff
51 #define V3D_CT0CS_WIDTH 32
52 #define V3D_CT1CS HW_REGISTER_RW( V3D_BASE+0x0104 )
53 #define V3D_CT1CS_MASK 0xffffffff
54 #define V3D_CT1CS_WIDTH 32
55 #define V3D_CT0EA HW_REGISTER_RW( V3D_BASE+0x0108 )
56 #define V3D_CT0EA_MASK 0xffffffff
57 #define V3D_CT0EA_WIDTH 32
58 #define V3D_CT1EA HW_REGISTER_RW( V3D_BASE+0x010c )
59 #define V3D_CT1EA_MASK 0xffffffff
60 #define V3D_CT1EA_WIDTH 32
61 #define V3D_CT0CA HW_REGISTER_RW( V3D_BASE+0x0110 )
62 #define V3D_CT0CA_MASK 0xffffffff
63 #define V3D_CT0CA_WIDTH 32
64 #define V3D_CT1CA HW_REGISTER_RW( V3D_BASE+0x0114 )
65 #define V3D_CT1CA_MASK 0xffffffff
66 #define V3D_CT1CA_WIDTH 32
67 #define V3D_CT00RA0 HW_REGISTER_RW( V3D_BASE+0x0118 )
68 #define V3D_CT00RA0_MASK 0xffffffff
69 #define V3D_CT00RA0_WIDTH 32
70 #define V3D_CT01RA0 HW_REGISTER_RW( V3D_BASE+0x011c )
71 #define V3D_CT01RA0_MASK 0xffffffff
72 #define V3D_CT01RA0_WIDTH 32
73 #define V3D_CT0LC HW_REGISTER_RW( V3D_BASE+0x0120 )
74 #define V3D_CT0LC_MASK 0xffffffff
75 #define V3D_CT0LC_WIDTH 32
76 #define V3D_CT1LC HW_REGISTER_RW( V3D_BASE+0x0124 )
77 #define V3D_CT1LC_MASK 0xffffffff
78 #define V3D_CT1LC_WIDTH 32
79 #define V3D_CT0PC HW_REGISTER_RW( V3D_BASE+0x0128 )
80 #define V3D_CT0PC_MASK 0xffffffff
81 #define V3D_CT0PC_WIDTH 32
82 #define V3D_CT1PC HW_REGISTER_RW( V3D_BASE+0x012c )
83 #define V3D_CT1PC_MASK 0xffffffff
84 #define V3D_CT1PC_WIDTH 32
85 #define V3D_PCS HW_REGISTER_RW( V3D_BASE+0x0130 )
86 #define V3D_PCS_MASK 0x0000013f
87 #define V3D_PCS_WIDTH 9
88 #define V3D_BFC HW_REGISTER_RW( V3D_BASE+0x0134 )
89 #define V3D_BFC_MASK 0x000000ff
90 #define V3D_BFC_WIDTH 8
91 #define V3D_RFC HW_REGISTER_RW( V3D_BASE+0x0138 )
92 #define V3D_RFC_MASK 0x000000ff
93 #define V3D_RFC_WIDTH 8
94 #define V3D_BPCA HW_REGISTER_RW( V3D_BASE+0x0300 )
95 #define V3D_BPCA_MASK 0xffffffff
96 #define V3D_BPCA_WIDTH 32
97 #define V3D_BPCS HW_REGISTER_RW( V3D_BASE+0x0304 )
98 #define V3D_BPCS_MASK 0xffffffff
99 #define V3D_BPCS_WIDTH 32
100 #define V3D_BPOA HW_REGISTER_RW( V3D_BASE+0x0308 )
101 #define V3D_BPOA_MASK 0xffffffff
102 #define V3D_BPOA_WIDTH 32
103 #define V3D_BPOS HW_REGISTER_RW( V3D_BASE+0x030c )
104 #define V3D_BPOS_MASK 0xffffffff
105 #define V3D_BPOS_WIDTH 32
106 #define V3D_BXCF HW_REGISTER_RW( V3D_BASE+0x0310 )
107 #define V3D_BXCF_MASK 0x00000003
108 #define V3D_BXCF_WIDTH 2
109 #define V3D_SQRSV0 HW_REGISTER_RW( V3D_BASE+0x0410 )
110 #define V3D_SQRSV0_MASK 0xffffffff
111 #define V3D_SQRSV0_WIDTH 32
112 #define V3D_SQRSV1 HW_REGISTER_RW( V3D_BASE+0x0414 )
113 #define V3D_SQRSV1_MASK 0xffffffff
114 #define V3D_SQRSV1_WIDTH 32
115 #define V3D_SQCNTL HW_REGISTER_RW( V3D_BASE+0x0418 )
116 #define V3D_SQCNTL_MASK 0x0000000f
117 #define V3D_SQCNTL_WIDTH 4
118 #define V3D_SQCSTAT HW_REGISTER_RW( V3D_BASE+0x041c )
119 #define V3D_SQCSTAT_MASK 0xffffffff
120 #define V3D_SQCSTAT_WIDTH 32
121 #define V3D_SRQPC HW_REGISTER_RW( V3D_BASE+0x0430 )
122 #define V3D_SRQPC_MASK 0xffffffff
123 #define V3D_SRQPC_WIDTH 32
124 #define V3D_SRQUA HW_REGISTER_RW( V3D_BASE+0x0434 )
125 #define V3D_SRQUA_MASK 0xffffffff
126 #define V3D_SRQUA_WIDTH 32
127 #define V3D_SRQUL HW_REGISTER_RW( V3D_BASE+0x0438 )
128 #define V3D_SRQUL_MASK 0x00000fff
129 #define V3D_SRQUL_WIDTH 12
130 #define V3D_SRQCS HW_REGISTER_RW( V3D_BASE+0x043c )
131 #define V3D_SRQCS_MASK 0x00ffffbf
132 #define V3D_SRQCS_WIDTH 24
133 #define V3D_VPACNTL HW_REGISTER_RW( V3D_BASE+0x0500 )
134 #define V3D_VPACNTL_MASK 0xffffffff
135 #define V3D_VPACNTL_WIDTH 32
136 #define V3D_VPMBASE HW_REGISTER_RW( V3D_BASE+0x0504 )
137 #define V3D_VPMBASE_MASK 0xffffffff
138 #define V3D_VPMBASE_WIDTH 32
139 #define V3D_PCTRC HW_REGISTER_RW( 0x7ec00670 )
140 #define V3D_PCTRC_MASK 0x0000ffff
141 #define V3D_PCTRC_WIDTH 16
142 #define V3D_PCTRE HW_REGISTER_RW( 0x7ec00674 )
143 #define V3D_PCTRE_MASK 0x8000ffff
144 #define V3D_PCTRE_WIDTH 32
145 #define V3D_PCTR0 HW_REGISTER_RW( 0x7ec00680 )
146 #define V3D_PCTR0_MASK 0xffffffff
147 #define V3D_PCTR0_WIDTH 32
148 #define V3D_PCTRS0 HW_REGISTER_RW( 0x7ec00684 )
149 #define V3D_PCTRS0_MASK 0x0000001f
150 #define V3D_PCTRS0_WIDTH 5
151 #define V3D_PCTR1 HW_REGISTER_RW( 0x7ec00688 )
152 #define V3D_PCTR1_MASK 0xffffffff
153 #define V3D_PCTR1_WIDTH 32
154 #define V3D_PCTRS1 HW_REGISTER_RW( 0x7ec0068c )
155 #define V3D_PCTRS1_MASK 0x0000001f
156 #define V3D_PCTRS1_WIDTH 5
157 #define V3D_PCTR2 HW_REGISTER_RW( 0x7ec00690 )
158 #define V3D_PCTR2_MASK 0xffffffff
159 #define V3D_PCTR2_WIDTH 32
160 #define V3D_PCTRS2 HW_REGISTER_RW( 0x7ec00694 )
161 #define V3D_PCTRS2_MASK 0x0000001f
162 #define V3D_PCTRS2_WIDTH 5
163 #define V3D_PCTR3 HW_REGISTER_RW( 0x7ec00698 )
164 #define V3D_PCTR3_MASK 0xffffffff
165 #define V3D_PCTR3_WIDTH 32
166 #define V3D_PCTRS3 HW_REGISTER_RW( 0x7ec0069c )
167 #define V3D_PCTRS3_MASK 0x0000001f
168 #define V3D_PCTRS3_WIDTH 5
169 #define V3D_PCTR4 HW_REGISTER_RW( 0x7ec006a0 )
170 #define V3D_PCTR4_MASK 0xffffffff
171 #define V3D_PCTR4_WIDTH 32
172 #define V3D_PCTRS4 HW_REGISTER_RW( 0x7ec006a4 )
173 #define V3D_PCTRS4_MASK 0x0000001f
174 #define V3D_PCTRS4_WIDTH 5
175 #define V3D_PCTR5 HW_REGISTER_RW( 0x7ec006a8 )
176 #define V3D_PCTR5_MASK 0xffffffff
177 #define V3D_PCTR5_WIDTH 32
178 #define V3D_PCTRS5 HW_REGISTER_RW( 0x7ec006ac )
179 #define V3D_PCTRS5_MASK 0x0000001f
180 #define V3D_PCTRS5_WIDTH 5
181 #define V3D_PCTR6 HW_REGISTER_RW( 0x7ec006b0 )
182 #define V3D_PCTR6_MASK 0xffffffff
183 #define V3D_PCTR6_WIDTH 32
184 #define V3D_PCTRS6 HW_REGISTER_RW( 0x7ec006b4 )
185 #define V3D_PCTRS6_MASK 0x0000001f
186 #define V3D_PCTRS6_WIDTH 5
187 #define V3D_PCTR7 HW_REGISTER_RW( 0x7ec006b8 )
188 #define V3D_PCTR7_MASK 0xffffffff
189 #define V3D_PCTR7_WIDTH 32
190 #define V3D_PCTRS7 HW_REGISTER_RW( 0x7ec006bc )
191 #define V3D_PCTRS7_MASK 0x0000001f
192 #define V3D_PCTRS7_WIDTH 5
193 #define V3D_PCTR8 HW_REGISTER_RW( 0x7ec006c0 )
194 #define V3D_PCTR8_MASK 0xffffffff
195 #define V3D_PCTR8_WIDTH 32
196 #define V3D_PCTRS8 HW_REGISTER_RW( 0x7ec006c4 )
197 #define V3D_PCTRS8_MASK 0x0000001f
198 #define V3D_PCTRS8_WIDTH 5
199 #define V3D_PCTR9 HW_REGISTER_RW( 0x7ec006c8 )
200 #define V3D_PCTR9_MASK 0xffffffff
201 #define V3D_PCTR9_WIDTH 32
202 #define V3D_PCTRS9 HW_REGISTER_RW( 0x7ec006cc )
203 #define V3D_PCTRS9_MASK 0x0000001f
204 #define V3D_PCTRS9_WIDTH 5
205 #define V3D_PCTR10 HW_REGISTER_RW( 0x7ec006d0 )
206 #define V3D_PCTR10_MASK 0xffffffff
207 #define V3D_PCTR10_WIDTH 32
208 #define V3D_PCTRS10 HW_REGISTER_RW( 0x7ec006d4 )
209 #define V3D_PCTRS10_MASK 0x0000001f
210 #define V3D_PCTRS10_WIDTH 5
211 #define V3D_PCTR11 HW_REGISTER_RW( 0x7ec006d8 )
212 #define V3D_PCTR11_MASK 0xffffffff
213 #define V3D_PCTR11_WIDTH 32
214 #define V3D_PCTRS11 HW_REGISTER_RW( 0x7ec006dc )
215 #define V3D_PCTRS11_MASK 0x0000001f
216 #define V3D_PCTRS11_WIDTH 5
217 #define V3D_PCTR12 HW_REGISTER_RW( 0x7ec006e0 )
218 #define V3D_PCTR12_MASK 0xffffffff
219 #define V3D_PCTR12_WIDTH 32
220 #define V3D_PCTRS12 HW_REGISTER_RW( 0x7ec006e4 )
221 #define V3D_PCTRS12_MASK 0x0000001f
222 #define V3D_PCTRS12_WIDTH 5
223 #define V3D_PCTR13 HW_REGISTER_RW( 0x7ec006e8 )
224 #define V3D_PCTR13_MASK 0xffffffff
225 #define V3D_PCTR13_WIDTH 32
226 #define V3D_PCTRS13 HW_REGISTER_RW( 0x7ec006ec )
227 #define V3D_PCTRS13_MASK 0x0000001f
228 #define V3D_PCTRS13_WIDTH 5
229 #define V3D_PCTR14 HW_REGISTER_RW( 0x7ec006f0 )
230 #define V3D_PCTR14_MASK 0xffffffff
231 #define V3D_PCTR14_WIDTH 32
232 #define V3D_PCTRS14 HW_REGISTER_RW( 0x7ec006f4 )
233 #define V3D_PCTRS14_MASK 0x0000001f
234 #define V3D_PCTRS14_WIDTH 5
235 #define V3D_PCTR15 HW_REGISTER_RW( 0x7ec006f8 )
236 #define V3D_PCTR15_MASK 0xffffffff
237 #define V3D_PCTR15_WIDTH 32
238 #define V3D_PCTRS15 HW_REGISTER_RW( 0x7ec006fc )
239 #define V3D_PCTRS15_MASK 0x0000001f
240 #define V3D_PCTRS15_WIDTH 5
241 #define V3D_DBCFG HW_REGISTER_RW( V3D_BASE+0x0e00 )
242 #define V3D_DBCFG_MASK 0xffffffff
243 #define V3D_DBCFG_WIDTH 32
244 #define V3D_DBSCS HW_REGISTER_RW( V3D_BASE+0x0e04 )
245 #define V3D_DBSCS_MASK 0xffffffff
246 #define V3D_DBSCS_WIDTH 32
247 #define V3D_DBSCFG HW_REGISTER_RW( V3D_BASE+0x0e08 )
248 #define V3D_DBSCFG_MASK 0xffffffff
249 #define V3D_DBSCFG_WIDTH 32
250 #define V3D_DBSSR HW_REGISTER_RW( V3D_BASE+0x0e0c )
251 #define V3D_DBSSR_MASK 0xffffffff
252 #define V3D_DBSSR_WIDTH 32
253 #define V3D_DBSDR0 HW_REGISTER_RW( V3D_BASE+0x0e10 )
254 #define V3D_DBSDR0_MASK 0xffffffff
255 #define V3D_DBSDR0_WIDTH 32
256 #define V3D_DBSDR1 HW_REGISTER_RW( V3D_BASE+0x0e14 )
257 #define V3D_DBSDR1_MASK 0xffffffff
258 #define V3D_DBSDR1_WIDTH 32
259 #define V3D_DBSDR2 HW_REGISTER_RW( V3D_BASE+0x0e18 )
260 #define V3D_DBSDR2_MASK 0xffffffff
261 #define V3D_DBSDR2_WIDTH 32
262 #define V3D_DBSDR3 HW_REGISTER_RW( V3D_BASE+0x0e1c )
263 #define V3D_DBSDR3_MASK 0xffffffff
264 #define V3D_DBSDR3_WIDTH 32
265 #define V3D_DBQRUN HW_REGISTER_RW( V3D_BASE+0x0e20 )
266 #define V3D_DBQRUN_MASK 0xffffffff
267 #define V3D_DBQRUN_WIDTH 32
268 #define V3D_DBQHLT HW_REGISTER_RW( V3D_BASE+0x0e24 )
269 #define V3D_DBQHLT_MASK 0xffffffff
270 #define V3D_DBQHLT_WIDTH 32
271 #define V3D_DBQSTP HW_REGISTER_RW( V3D_BASE+0x0e28 )
272 #define V3D_DBQSTP_MASK 0xffffffff
273 #define V3D_DBQSTP_WIDTH 32
274 #define V3D_DBQITE HW_REGISTER_RW( V3D_BASE+0x0e2c )
275 #define V3D_DBQITE_MASK 0xffffffff
276 #define V3D_DBQITE_WIDTH 32
277 #define V3D_DBQITC HW_REGISTER_RW( V3D_BASE+0x0e30 )
278 #define V3D_DBQITC_MASK 0xffffffff
279 #define V3D_DBQITC_WIDTH 32
280 #define V3D_DBQGHC HW_REGISTER_RW( V3D_BASE+0x0e34 )
281 #define V3D_DBQGHC_MASK 0xffffffff
282 #define V3D_DBQGHC_WIDTH 32
283 #define V3D_DBQGHG HW_REGISTER_RW( V3D_BASE+0x0e38 )
284 #define V3D_DBQGHG_MASK 0xffffffff
285 #define V3D_DBQGHG_WIDTH 32
286 #define V3D_DBQGHH HW_REGISTER_RW( V3D_BASE+0x0e3c )
287 #define V3D_DBQGHH_MASK 0xffffffff
288 #define V3D_DBQGHH_WIDTH 32
289 #define V3D_DBGE HW_REGISTER_RW( V3D_BASE+0x0f00 )
290 #define V3D_DBGE_MASK 0xffffffff
291 #define V3D_DBGE_WIDTH 32
292 #define V3D_FDBG0 HW_REGISTER_RW( V3D_BASE+0x0f04 )
293 #define V3D_FDBG0_MASK 0xffffffff
294 #define V3D_FDBG0_WIDTH 32
295 #define V3D_FDBGB HW_REGISTER_RW( V3D_BASE+0x0f08 )
296 #define V3D_FDBGB_MASK 0xffffffff
297 #define V3D_FDBGB_WIDTH 32
298 #define V3D_FDBGR HW_REGISTER_RW( V3D_BASE+0x0f0c )
299 #define V3D_FDBGR_MASK 0xffffffff
300 #define V3D_FDBGR_WIDTH 32
301 #define V3D_FDBGS HW_REGISTER_RW( V3D_BASE+0x0f10 )
302 #define V3D_FDBGS_MASK 0xffffffff
303 #define V3D_FDBGS_WIDTH 32
304 #define V3D_ERRSTAT HW_REGISTER_RW( V3D_BASE+0x0f20 )
305 #define V3D_ERRSTAT_MASK 0xffffffff
306 #define V3D_ERRSTAT_WIDTH 32
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