ba9dc50588b7b11a19a58f6382aef1d3a49a57f5
[rpi-open-firmware.git] / bcm2708_chip / vcodec.h
1 /*=============================================================================
2 Copyright (c) 2006 Broadcom Europe Limited.
3 All rights reserved.
4
5 Project : VideoCore III
6 Module : Video codec specific header (vcodec)
7 File : $RCSfile: vcodec.h,v $
8 Revision : $Revision: 1.14 $
9
10 FILE DESCRIPTION
11 Chip I/O for the video codec.
12 =============================================================================*/
13
14 #ifndef __VCODEC_H__
15 #define __VCODEC_H__
16
17 #define VCODEC_IO_BASE 0x7f000000
18
19
20 typedef enum
21 {
22 WIDTH_MASK0 = 0,
23 WIDTH_MASK1 = 0x00000001,
24 WIDTH_MASK2 = 0x00000003,
25 WIDTH_MASK3 = 0x00000007,
26 WIDTH_MASK4 = 0x0000000f,
27 WIDTH_MASK5 = 0x0000001f,
28 WIDTH_MASK6 = 0x0000003f,
29 WIDTH_MASK7 = 0x0000007f,
30 WIDTH_MASK8 = 0x000000ff,
31 WIDTH_MASK9 = 0x000001ff,
32 WIDTH_MASK10 = 0x000003ff,
33 WIDTH_MASK11 = 0x000007ff,
34 WIDTH_MASK12 = 0x00000fff,
35 WIDTH_MASK13 = 0x00001fff,
36 WIDTH_MASK14 = 0x00003fff,
37 WIDTH_MASK15 = 0x00007fff,
38 WIDTH_MASK16 = 0x0000ffff,
39 WIDTH_MASK17 = 0x0001ffff,
40 WIDTH_MASK18 = 0x0003ffff,
41 WIDTH_MASK19 = 0x0007ffff,
42 WIDTH_MASK20 = 0x000fffff,
43 WIDTH_MASK21 = 0x001fffff,
44 WIDTH_MASK22 = 0x003fffff,
45 WIDTH_MASK23 = 0x007fffff,
46 WIDTH_MASK24 = 0x00ffffff,
47 WIDTH_MASK25 = 0x01ffffff,
48 WIDTH_MASK26 = 0x03ffffff,
49 WIDTH_MASK27 = 0x07ffffff,
50 WIDTH_MASK28 = 0x0fffffff,
51 WIDTH_MASK29 = 0x1fffffff,
52 WIDTH_MASK30 = 0x3fffffff,
53 WIDTH_MASK31 = 0x7fffffff,
54 WIDTH_MASK32 = 0xffffffff
55 } WIDTH_MASKS;
56
57
58 /* Pull the register addresses from 'RegFld.h' and create an enum;
59 * this gives us a set of constants that we can use to access the
60 * registers in IO statements.
61 */
62 #define CHIP "sv_chip_regmap.h"
63 #define CHIP2 "sv_enc_chip_regmap.h"
64
65 enum
66 {
67 #define RegAreaFunc(a,b,c) a = b, a##End = c, a##Max = c-b,
68 #define RegFunc(mod, modbase, regname, offset, name, addr) name = addr,
69 #define FldFunc(a,b,c,d)
70
71 #include CHIP
72 //#include CHIP2
73
74 #undef FldFunc
75 #undef RegFunc
76 #undef RegAreaFunc
77 };
78
79 // Enum of FIELD_Reg
80 typedef enum {
81 #define FldFunc(reg, field, lsb, width) FIELD_ ##reg ##_ ##field = (WIDTH_MASK ##width << lsb),
82 #include CHIP
83 //#include CHIP2
84 }RegAddrField;
85 #undef FldFunc
86
87 // Enum of POS_Reg
88 typedef enum {
89 #define FldFunc(reg, field, lsb, width) POS_ ##reg ##_ ##field = lsb,
90 #include CHIP
91 //#include CHIP2
92 }RegAddrPos;
93 #undef FldFunc
94
95
96
97 /* Don't use _VCODEC_IO directly - prefer Reg{Rd|Wt} below */
98 #define _VCODEC_IO(x) (* (volatile unsigned long *) (VCODEC_IO_BASE | (x)))
99
100 /* Use these rather than _IO() directly so that it's easy to replace the macros with simulation functions */
101 #define RegWt( addr, value ) _VCODEC_IO( addr ) = ( value )
102 #define RegRd( addr ) _VCODEC_IO( addr )
103
104
105
106 #define RegValFieldGet(RegVal, Reg, Field) ((RegVal & FIELD_ ##Reg ##_ ##Field) >> POS_ ##Reg ##_ ##Field)
107 #define RegValFieldSetTo(RegVal, Reg, Field, To) ( (RegVal) += -((RegVal)&FIELD_ ##Reg ##_ ##Field) + (To<<POS_ ##Reg ##_ ##Field))
108
109 // Allows video codec to access memory
110 #define VCODECCTL 0x10000c40
111 #define VCODECDQNT8X8BASE 0x500
112
113
114 // Taken from mpeg_symdec.h
115 /* GetSymbol Register (WO) ----------------------------------------------------
116 ---------------------------------------------------------------------------------
117 Write this register to specify the next symbol to be extracted from the stream.
118 The symbol value is also read from the GetSymbol register.
119 The codestream pointer is advanced by the size of the symbol.
120
121 Register Fields:
122 31:11 Reserved
123 15:12 Type
124 11:08 SubType
125 07:00 N
126 */
127
128 /* 15:12 Type for */
129 typedef enum
130 {
131 GET_N_BITS,
132 GET_EXP_GOL,
133 GET_MP2_INFO,
134 GET_MP2_COEF,
135 GET_264_INFO,
136 GET_264_COEF,
137 GET_4X4_SPACE_PRED_MODE
138 } GS_TYPE;
139
140 /* 11:08 SubType GET_MP2_INFO */
141 typedef enum
142 {
143 MB_TYPE_I,
144 MB_TYPE_P,
145 MB_TYPE_B,
146 MB_ADDRESS,
147 CBP,
148 MOTION_CODE,
149 DM_VECTOR
150 } GS_SUBTYPE_MP2_INFO;
151
152 /* 11:08 SubType GET_MP2_COEF */
153 typedef enum
154 {
155 DCT_COEF0_DC,
156 DCT_COEF0_AC,
157 DCT_COEF1_AC,
158 DCT_COEF1_DC,
159 DC_SIZE_LUM,
160 DC_SIZE_CHR
161 } GS_SUBTYPE_MP2_COEF;
162
163
164
165 // From sv_symb_int.vh
166
167 /*
168 // Syntax element decoder function selection
169 parameter DCD_TYPE_N_BITS = 'd0,
170 DCD_TYPE_EXPGOL = 'd1,
171 DCD_TYPE_MPEG_INFO = 'd2,
172 DCD_TYPE_MPEG_COEF = 'd3,
173 DCD_TYPE_H264_INFO = 'd4,
174 DCD_TYPE_H264_COEF = 'd5,
175 DCD_TYPE_SPAT_PRED = 'd6,
176 DCD_TYPE_VC1 = 'd7;
177
178
179 // Table identification
180
181
182 // MPEG "Info" tables
183 */
184 enum
185 {
186 MINFO_MBTYPE_I_TABLE = 0,
187 MINFO_MBTYPE_P_TABLE = 1,
188 MINFO_MBTYPE_B_TABLE = 2,
189 MINFO_MBADDR_TABLE = 3,
190 MINFO_CBP_TABLE = 4,
191 MINFO_MOTION_TABLE = 5,
192 MINFO_DM_VECTOR_TABLE = 6,
193 MINFO_261_MTYPE = 7,
194 MINFO_263_MCBPC = 8,
195 MINFO_263_CBPY = 9};
196
197 // MPEG "Coef" tables
198 enum
199 {
200 MCOEF_DCT_COEF0_DC = 0,
201 MCOEF_DCT_COEF0_AC = 1,
202 MCOEF_DCT_COEF1_DC = 2,
203 MCOEF_DCT_COEF1_AC = 3,
204 MCOEF_DC_SIZE_LUMA = 4,
205 MCOEF_DC_SIZE_CHROMA = 5,
206 MCOEF_261_COEF0 = 6,
207 MCOEF_261_COEF1 = 7,
208 MCOEF_263 = 8
209 };
210 /*
211 // H264 Info tables
212 parameter HINFO_MBTYPE_I = 'd0,
213 HINFO_MBTYPE_P = 'd1,
214 HINFO_MBTYPE_B = 'd2,
215 HINFO_SUBMBTYPE_P = 'd3,
216 HINFO_SUBMBTYPE_B = 'd4,
217 HINFO_MVD = 'd5,
218 HINFO_TU = 'd6,
219 HINFO_CBP = 'd7,
220 HINFO_TE = 'd8,
221 HINFO_SU = 'd9;
222
223 // H264 coef
224 parameter HCOEF_CAVLC_TOKEN = 'd0,
225 HCOEF_CAVLC_TOT_ZERO = 'd1,
226 HCOEF_CAVLC_TOT_ZERO_CR = 'd2,
227 HCOEF_CAVLC_RUN_BEFORE = 'd3,
228 HCOEF_CAVLC_LEVEL = 'd4,
229 HCOEF_CABAC_LEVEL = 'd5,
230 HCOEF_CABAC_SIGMAP = 'd6;
231
232 // VC-1
233 parameter VC1_CBPCY = 'd0,
234 VC1_MBMODE = 'd1,
235 VC1_MVEC = 'd2,
236 VC1_MVBP = 'd3,
237 VC1_TTMB = 'd4,
238 VC1_SUBTYPE = 'd5,
239 VC1_TTBLK = 'd6,
240 VC1_DCDIFF = 'd7,
241 VC1_BMVTYPE = 'd8;
242
243 parameter VC1_LEVEL_SIZE = 'd11; // Unsigned
244 parameter VC1_RUN_SIZE = 'd6;
245 parameter VC1_COEF_MSB = VC1_LEVEL_SIZE + 1 + VC1_RUN_SIZE - 1; // Run, level, sign
246
247
248 // Constructed symbol types
249 parameter CONSTR_UE = 'd0,
250 CONSTR_SE = 'd1,
251 CONSTR_UEG0 = 'd2,
252 CONSTR_UEG3 = 'd3,
253 CONSTR_CAVLC = 'd4,
254 CONSTR_SU = 'd5;
255
256
257 // Xfer symb types
258 parameter XFER_MVD = 'd0,
259 XFER_REFID = 'd1,
260 XFER_SMODE = 'd2,
261 XFER_XFORM8X8 = 'd3,
262 XFER_MVD_HW = 'd4,
263 XFER_SUBTYPE = 'd5;
264
265
266
267
268 // Coef generator
269 parameter CG_MPEG_TYPE = 'd0,
270 CG_CAVLC_TYPE = 'd1,
271 CG_CABAC_TYPE = 'd2,
272 CG_VC1_TYPE = 'd3,
273 CG_PCM_TYPE = 'd4;
274
275 parameter FAST_DCD_MPEG = 'd0,
276 FAST_DCD_CAVLC = 'd1,
277 FAST_DCD_CABAC = 'd2,
278 FAST_DCD_VC1 = 'd3;
279
280 parameter CG_SUBTYPE_MPEG2 = 'd0,
281 CG_SUBTYPE_H261 = 'd1,
282 CG_SUBTYPE_H263 = 'd2,
283 CG_SUBTYPE_MPEG1 = 'd3;
284
285 parameter CG_IXFM_TYPE_4X4 = 'd0,
286 CG_IXFM_TYPE_16X16 = 'd1,
287 CG_IXFM_TYPE_8X8 = 'd2,
288 CG_IXFM_TYPE_PCM = 'd3;
289
290 // MPEG coefficient escape code is a fixed-length representation
291 // of run & level., preceeded by an 'escape' code
292 */
293 #define MPEG_ESC_CODE 1
294 #define MPEG_ESC_CODE_SIZE 6
295 #define MPEG_LEVEL_SIZE 11
296 #define MPEG_RUN_SIZE 6
297 #define MPEG_ESC_SIZE (MPEG_ESC_CODE_SIZE + MPEG_LEVEL_SIZE + MPEG_RUN_SIZE + 1)
298 #define MPEG_RUN_SHIFT (MPEG_LEVEL_SIZE + 1)
299 #define MPEG_ESC_SHIFT (MPEG_RUN_SHIFT + MPEG_RUN_SIZE)
300 #define H263_LAST_SHIFT (MPEG_ESC_SHIFT + 1)
301
302 // Escape code - same as MPEG
303 #define H261_LEVEL_SIZE 7
304 #define H261_RUN_SIZE 6
305 #define H261_ESC_SIZE (MPEG_ESC_CODE_SIZE + H261_LEVEL_SIZE + H261_RUN_SIZE + 1)
306
307 #define H263_ESC_CODE 3
308 #define H263_ESC_CODE_SIZE 7
309 #define H263_LEVEL_SIZE 7
310 #define H263_RUN_SIZE 6
311 #define H263_ESC_SIZE (H263_ESC_CODE_SIZE + 1 + 1 + H263_LEVEL_SIZE + H263_RUN_SIZE)
312
313 // MPEG escape: [Run],[Sign],[Level]
314 #define MPEG_ESC_RUN_START MPEG_ESC_CODE_SIZE
315 #define MPEG_ESC_RUN_END (MPEG_ESC_RUN_START + MPEG_RUN_SIZE - 1)
316 #define MPEG_ESC_SIGN_BIT (MPEG_ESC_RUN_END + 1)
317 #define MPEG_ESC_LEVEL_START (MPEG_ESC_SIGN_BIT + 1)
318 #define MPEG_ESC_LEVEL_END (MPEG_ESC_LEVEL_START + MPEG_LEVEL_SIZE - 1)
319
320
321 #define MPEG_LEVEL_MSB (MPEG_LEVEL_SIZE - 1)
322 #define MPEG_COEF_MSB (MPEG_LEVEL_MSB + 1)
323 #define MPEG_RUN_MSB (MPEG_RUN_SIZE - 1)
324
325 // H261 escape: [Run],[Sign],[Level]
326 #define H261_ESC_RUN_START (MPEG_ESC_CODE_SIZE)
327 #define H261_ESC_RUN_END (H261_ESC_RUN_START + H261_RUN_SIZE - 1)
328 #define H261_ESC_SIGN_BIT (H261_ESC_RUN_END + 1)
329 #define H261_ESC_LEVEL_START (H261_ESC_SIGN_BIT + 1)
330 #define H261_ESC_LEVEL_END (H261_ESC_LEVEL_START + H261_LEVEL_SIZE - 1)
331
332 // H263 escape: [Last],[Run],[Sign],[Level]
333 #define H263_ESC_LAST_BIT (H263_ESC_CODE_SIZE)
334 #define H263_ESC_RUN_START (H263_ESC_CODE_SIZE + 1)
335 #define H263_ESC_RUN_END (H263_ESC_RUN_START + H263_RUN_SIZE - 1)
336 #define H263_ESC_SIGN_BIT (H263_ESC_RUN_END + 1)
337 #define H263_ESC_LEVEL_START (H263_ESC_SIGN_BIT + 1)
338 #define H263_ESC_LEVEL_END (H263_ESC_LEVEL_START + H263_LEVEL_SIZE - 1)
339
340 #define H264_LEVEL_SIZE 15; // Unsigned
341 #define H264_LEVEL_MSB (H264_LEVEL_SIZE - 1)
342 /*
343 // MPEG 1 escape. Basically the same as H261, except has a 'double' escape if the
344 // level in the regular escape = 0
345 parameter MPEG1_ESC_DBL_START = H261_ESC_LEVEL_END + 1;
346 parameter MPEG1_ESC_DBL_END = MPEG1_ESC_DBL_START + 8 - 1;
347 parameter MPEG1_ESC_DBL_SIZE = H261_ESC_SIZE + 8;
348
349
350 // VC1 defines
351 parameter VC1_PTYPE_I = 0,
352 VC1_PTYPE_P = 1,
353 VC1_PTYPE_B = 2;
354
355 parameter VC1_FCM_PROG = 0,
356 VC1_FCM_INTL_FRM = 1,
357 VC1_FCM_INTL_FLD = 2;
358
359 // Paramters for coef. generator buffer
360 parameter BUF_COEF_SIZE = 'd15;
361 parameter BUF_RUN_SIZE = 'd6; // For MPEG
362
363
364 // H264 vector types
365 parameter H264_P_L0_16X16 = 'd0,
366 H264_P_L0_L0_16X8 = 'd1,
367 H264_P_L0_L0_8X16 = 'd2,
368 H264_P_8X8 = 'd3,
369 H264_P_8X8REF0 = 'd4;
370
371 parameter H264_B_DIRECT_16X16 = 'd0,
372 H264_B_8X8 = 'd22;
373
374
375
376 // VC-1 Inverse coef block sizes
377 parameter VC1_IX_BLK_8X8 = 0,
378 VC1_IX_BLK_8X4 = 1,
379 VC1_IX_BLK_4X8 = 2,
380 VC1_IX_BLK_4X4 = 3;
381
382
383 // Constants used in vector generation
384 parameter VEC_TYPE_16X16 = 'd0,
385 VEC_TYPE_16X8 = 'd1,
386 VEC_TYPE_8X16 = 'd2,
387 VEC_TYPE_8X8 = 'd3;
388
389 parameter VEC_SUBTYPE_8X8 = 'd0,
390 VEC_SUBTYPE_8X4 = 'd1,
391 VEC_SUBTYPE_4X8 = 'd2,
392 VEC_SUBTYPE_4X4 = 'd3;
393
394 parameter VEC_COMPUTE = 'd0,
395 VEC_COPY_LEFT = 'd1,
396 VEC_COPY_TOP = 'd2;
397
398 parameter VEC_SEL_A = 'd0,
399 VEC_SEL_B = 'd1,
400 VEC_SEL_C = 'd2,
401 VEC_SEL_D = 'd3;
402
403 parameter VEC_VC1_1MV = 'd0,
404 VEC_VC1_2MV = 'd1,
405 VEC_VC1_4MV = 'd3;
406
407
408 // Vector generator ALU
409 parameter ALU_IN_SEL_A = VEC_SEL_A,
410 ALU_IN_SEL_B = VEC_SEL_B,
411 ALU_IN_SEL_C = VEC_SEL_C,
412 ALU_IN_SEL_CONST = 'd3;
413
414 parameter ALU_LDSEL_A = 'd0,
415 ALU_LDSEL_B = 'd1,
416 ALU_LDSEL_C = 'd2;
417
418 parameter ALU_OUT_DIFF = 'd0,
419 ALU_OUT_SUM = 'd1,
420 ALU_OUT_C = 'd2,
421 ALU_OUT_ENC_DIFF = 'd3;
422
423 parameter ALU_LDSRC_MEM = 'd0,
424 ALU_LDSRC_ALU = 'd1;
425
426 // Conditional load
427 parameter ALU_CLD_LT_M32 = 'd0,
428 ALU_CLD_GE_M32 = 'd1,
429 ALU_CLD_LT_0 = 'd2,
430 ALU_CLD_GE_0 = 'd3;
431 */
432
433 #define REG_STATUS 0x00000110
434
435 #define STATUS_MOCOMP_RDY (1 << 2)
436 #define STATUS_MOCOMP_DONE (1 << 3)
437 #define STATUS_SPAT_RDY (1 << 4)
438 #define STATUS_SPAT_DONE (1 << 5)
439 #define STATUS_XFM_RDY (1 << 6)
440 #define STATUS_XFM_DONE (1 << 7)
441 #define STATUS_RECON_RDY (1 << 8)
442 #define STATUS_RECON_DONE (1 << 9)
443 #define STATUS_DBLK_RDY (1 << 10)
444 #define STATUS_DBLK_DONE (1 << 11)
445
446 // Updated bits for new status register...
447 #define STATUS_FLUSHCTX (1<<17)
448 #define STATUS_RESET (1<<16)
449 #define STATUS_CTXDMAACT (1<<11)
450
451 #define STATUS_ALL_RDY (STATUS_MOCOMP_RDY | STATUS_SPAT_RDY | \
452 STATUS_XFM_RDY | STATUS_RECON_RDY | \
453 STATUS_DBLK_RDY)
454
455 #define STATUS_ALL_DONE (STATUS_MOCOMP_DONE | STATUS_SPAT_DONE | \
456 STATUS_XFM_DONE | STATUS_RECON_DONE | \
457 STATUS_DBLK_DONE)
458
459 #define STATUS_ALL_RDY_DONE (STATUS_ALL_DONE | STATUS_ALL_RDY)
460
461 #define REG_SINT_STRM_POS 0x00000c10
462
463 // Use base and offsets for symbol interpreter registers.
464 #define REGBASE_SINT 0x00000c00
465 #define REGOFF_SINT_DMA_ADDR 0x00
466 #define REGOFF_SINT_DMA_LEN 0x04
467 #define REGOFF_SINT_STRM_POS 0x10
468 #define REGOFF_SINT_STRM_STAT 0x14
469 #define REGOFF_SINT_STRM_BITS 0x1c
470 #define REGOFF_SINT_GET_SYMB 0x20
471 #define SINT_STRM_STAT_DCD_ERR (1 << 9)
472 #define SINT_STRM_STAT_STRM_ERR (1 << 8)
473 #define SINT_STRM_STAT_VALID (1 << 0)
474 #define REGOFF_SINT_DO_RESID 0x28
475 #define DO_RESID_INTRA16 (1 << 6)
476 #define RESID_WR_XNZERO (1 << 10)
477 #define DO_RESID_AFETCH (1 << 16)
478 #define DO_RESID_INTRA (1 << 17)
479 #define DO_RESID_SKIP (1 << 18)
480 #define REGOFF_VEC_MBTYPE 0x30
481 #define REGOFF_SINT_VEC_DMODE 0x38
482 #define REGOFF_SINT_VEC_TOP_LD 0x3c
483 #define REGOFF_SINT_SMODE_DATA 0xa0
484 #define REGOFF_SINT_SMODE_LEFT 0xa4
485 #define REGOFF_SINT_SMODE_TOP 0xa8
486 #define REGOFF_SINT_SMODE_VALID 0xac
487
488 #define REGOFF_TOPCTX_WRADDR 0x90
489 #define REGOFF_DIRCTX_WRADDR 0x94
490 #define REGOFF_TOPCTX_WRDAT 0x98
491 #define REGOFF_XFER_SYMB 0x9c
492
493 #define REGOFF_VEC_DO_CONST 0x40
494 #define REGOFF_VEC_REFIDX 0x48
495
496 #define REGOFF_SINT_VEC_COLTYPE 0x54
497 #define REGOFF_SINT_VEC_COLREFID 0x58
498 #define REGOFF_SINT_CTL 0x80
499 #define REGOFF_SINT_VLC_TOP_CTX 0x84
500 #define REGOFF_SINT_QP 0x8c
501
502 #define STRM_STAT_CG_ACTIVE (1 << 1)
503 #define STRM_STAT_VG_ACTIVE (1 << 4)
504 #define STRM_STAT_CG_PARSE (1 << 7)
505 #define STRM_STAT_STRM_ERR (1 << 8)
506 #define STRM_STAT_DCD_ERR (1 << 9)
507 #define STRM_STAT_CTX_BUSY (1 << 11)
508 #define STRM_STAT_FLUSH_CTX (1 << 17)
509
510 #define REG_MCOM_CTL 0x00000300
511 #define SHIFT_REG_MCOM_CTL_BREF 24
512 #define SHIFT_REG_MCOM_CTL_AREF 16
513 #define SHIFT_REG_MCOM_CTL_SUBBLOCK 12
514 #define SHIFT_REG_MCOM_CTL_YSIZE 6
515 #define SHIFT_REG_MCOM_CTL_XSIZE 4
516 #define SHIFT_REG_MCOM_CTL_BFLD 3
517 #define SHIFT_REG_MCOM_CTL_AFLD 2
518 #define SHIFT_REG_MCOM_CTL_MODE 0
519
520 #define REG_MCOM_SRCA 0x00000304
521 #define SHIFT_REG_MCOM_SRCA_Y 16
522 #define REG_MCOM_SRCB 0x00000308
523 #define SHIFT_REG_MCOM_SRCB_Y 16
524
525 #define REG_SPRE_CTL 0x00000320
526 #define SPRE_CTL_CNST_INTRA (1 << 4)
527 #define REG_SPRE_MODE 0x00000324
528
529 #define REG_DEQUANT_MAP1 0x400
530 #define REG_DEQUANT_MAP2 0x500
531
532 #define REG_IXFM_CTL 0x00000700
533 #define IXFM_XFM_I16 (1 << 30)
534 #define IXFM_XFM_8X8 (2 << 30)
535 #define IXFM_FIELD_SCAN (1 << 29)
536 #define IXFM_QS_TABLE (1 << 28)
537 #define IXFM_8X8_SUB_ORD (1 << 27)
538 #define IXFM_INTRA (1 << 24)
539
540 #define REG_IXFM_COEF 0x00000704
541 #define REG_IXFM_PCM 0x0000070C
542
543 #define REG_DBLK_CTL 0x00000720
544 #define DBLK_CTL_8X8 (1 << 7)
545 #define DBLK_CTL_MONO (1 << 6)
546 #define DBLK_CTL_ISINTRA (1 << 4)
547 #define DBLK_CTL_FLEFT (1 << 3)
548 #define DBLK_CTL_FTOP (1 << 2)
549 #define DBLK_CTL_FINT (1 << 1)
550 #define DBLK_ALL_AVAIL (DBLK_CTL_FINT | \
551 DBLK_CTL_FTOP | DBLK_CTL_FLEFT)
552 #define DBLK_NO_TOP_LEFT (DBLK_CTL_FINT)
553 #define DBLK_NO_TOP (DBLK_CTL_FINT | DBLK_CTL_FLEFT)
554 #define DBLK_NO_LEFT (DBLK_CTL_FINT | DBLK_CTL_FTOP)
555
556 #define REG_DBLK_OUT 0x00000724
557 #define REG_DBLK_EDGE 0x00000728
558 #define REG_DBLK_QNT 0x0000072C
559 #define REG_DBLK_OFFSET 0x00000730
560 #define REG_DBLK_TOP_CTX 0x00000734
561 #define REG_DBLK_TOP_INTRA (1 << 0)
562 #define REG_DBLK_TOP_FIELD (1 << 1)
563 #define SHIFT_REG_DBLK_TOP_CTX_ISINTRA 0
564 #define SHIFT_REG_DBLK_TOP_CTX_ISFIELD 1
565 #define SHIFT_REG_DBLK_TOP_CTX_B10 2
566 #define SHIFT_REG_DBLK_TOP_CTX_B11 3
567 #define SHIFT_REG_DBLK_TOP_CTX_B14 4
568 #define SHIFT_REG_DBLK_TOP_CTX_B15 5
569 #define REG_DBLK_XZERO 0x00000738
570 #define REG_DBLK_MVDIFF 0x0000073C
571
572 #define REG_MB_CTL 0x00000740
573 #define SHIFT_REG_MB_CTL_TOP_FIELD 17
574 #define SHIFT_REG_MB_CTL_FIELD_MODE 16
575
576 #define SYMB_GET_NBITS (0)
577 #define SYMB_GET_UE (1 << 12)
578 #define SYMB_GET_SE ((1 << 12) | (1 << 8))
579 #define SYMB_GET_H264_INFO (4 << 12)
580 #define SYMB_GET_SPATIAL (6 << 12)
581
582 #define SYMB_H264_INFO_I_MBTYPE (0 << 8)
583 #define SYMB_H264_INFO_P_MBTYPE (1 << 8)
584 #define SYMB_H264_INFO_B_MBTYPE (2 << 8)
585 #define SYMB_H264_INFO_SUB_P_SLICE (3 << 8)
586 #define SYMB_H264_INFO_SUB_B_SLICE (4 << 8)
587 #define SYMB_H264_INFO_MVD (5 << 8)
588 #define SYMB_H264_INFO_TU (6 << 8)
589 #define SYMB_H264_INFO_CBP (7 << 8)
590 #define SYMB_H264_INFO_TE (8 << 8)
591 #define SYMB_H264_INFO_SU (9 << 8)
592
593 #define SYMB_GET_TE (SYMB_GET_H264_INFO | SYMB_H264_INFO_TE)
594
595
596 #define REG_RVC_CTL 0xe00
597 #define REG_RVC_PUT 0xe04
598 #define REG_RVC_GET 0xe08
599 #define REG_RVC_BASE 0xe0c
600 #define REG_RVC_END 0xe10
601
602 #define REG_HST2CPU_MBX 0xf00
603 #define REG_CPU2HST_MBX 0xf04
604 #define REG_MBX_STAT 0xf08
605
606 #define REG_VEC_MBTYPE 0x0C30
607 #define VEC_MBTYPE_IS_B (1 << 0)
608
609 #define REG_VEC_RESID 0x0C34
610
611 #define REG_VEC_DO_CONST 0x0C40
612 #define SHIFT_REG_VEC_DO_CONST_ULFT_MBAFF_FIELD 6
613 #define REG_VEC_DO_CONST_INTRA (1 << 4)
614 #define REG_VEC_DO_CONST_PSKIP (1 << 5)
615 #define REG_VEC_DO_CONST_ULFT_MBAFF_FIELD (1 << 6)
616 #define REG_VEC_DO_CONST_LEFTCOPY (1 << 7)
617 #define REG_VEC_REF0_LTERM (1 << 8)
618 #define REG_VEC_DO_CONST_MVDIFF (1 << 9)
619
620 #define REG_VEC_DIFF 0x0C44
621 #define REG_SINT_XNZERO 0x0C2C
622 #define SHIFT_REG_SINT_XNZERO_B10 10
623 #define REG_SINT_XNZERO_B10 (1 << 10)
624 #define REG_SINT_XNZERO_B11 (1 << 11)
625 #define REG_SINT_XNZERO_B14 (1 << 14)
626 #define SHIFT_REG_SINT_XNZERO_B14 14
627 #define REG_SINT_XNZERO_B15 (1 << 15)
628
629 #define REG_VEC_REFIDX 0x0C48
630 #define SHIFT_REG_VEC_REFIDX0 0
631 #define SHIFT_REG_VEC_REFIDX1 8
632 #define SHIFT_REG_VEC_REFIDX2 16
633 #define SHIFT_REG_VEC_REFIDX3 24
634 #define SHIFT_REG_VEC_REFIDX_DELTA SHIFT_REG_VEC_REFIDX1
635
636 #define REG_VEC_TOPREF 0x0C4C
637 #define SHIFT_REG_VEC_TOPREFL0_B0 0
638 #define SHIFT_REG_VEC_TOPREFL0_B1 5
639 #define SHIFT_REG_VEC_TOPREFL0_C 10
640 #define SHIFT_REG_VEC_TOPREFL1_B0 16
641 #define SHIFT_REG_VEC_TOPREFL1_B1 21
642 #define SHIFT_REG_VEC_TOPREFL1_C 26
643 #define SHIFT_REG_VEC_TOPREF_DELTA SHIFT_REG_VEC_TOPREFL0_B1
644
645 #define REG_VEC_TOPTOPREF 0x0C50
646
647 #define REG_VEC_COLTYPE 0x0C54
648 #define MASK_REG_VEC_COLTYPE_TYPE 0x3
649 #define MASK_REG_VEC_COLTYPE_SLICE_ID 0xfff
650 #define SHIFT_REG_VEC_COLTYPE_TYPE 0
651 #define SHIFT_REG_VEC_COLTYPE_SUBTYPE0 2
652 #define SHIFT_REG_VEC_COLTYPE_SUBTYPE1 4
653 #define SHIFT_REG_VEC_COLTYPE_SUBTYPE2 6
654 #define SHIFT_REG_VEC_COLTYPE_SUBTYPE3 8
655 #define SHIFT_REG_VEC_COLTYPE_SLICE_ID 16
656 #define SHIFT_REG_VEC_COLTYPE_IS_FIELD 29
657 #define SHIFT_REG_VEC_COLTYPE_TOP_FIELD 30
658 #define SHIFT_REG_VEC_COLTYPE_MBAFF 31
659
660 #define COLTYPE_FLD_TOP (1<<SHIFT_REG_VEC_COLTYPE_IS_FIELD) | (1<<SHIFT_REG_VEC_COLTYPE_TOP_FIELD)
661 #define COLTYPE_AFF_FLD (1<<SHIFT_REG_VEC_COLTYPE_MBAFF) | (1<<SHIFT_REG_VEC_COLTYPE_IS_FIELD)
662 #define COLTYPE_FLD (1<<SHIFT_REG_VEC_COLTYPE_IS_FIELD)
663
664 #define REG_VEC_COLREFID 0x0C58
665 #define SHIFT_REG_VEC_COLREFID0 0
666 #define SHIFT_REG_VEC_COLREFID1 8
667 #define SHIFT_REG_VEC_COLREFID2 16
668 #define SHIFT_REG_VEC_COLREFID3 24
669 #define SHIFT_REG_VEC_COLREFID_DELTA SHIFT_REG_VEC_COLREFID1
670 #define MASK_REG_VEC_COLREFID 0x7
671
672 #define REG_VEC_TOPPIC 0x0c5c
673
674 #define REG_VEC_OUTPIC_MAP 0x0cc0
675 #define REGIO_VEC_OUTPIC_MAP (REG_VEC_OUTPIC_MAP | IO_BASE)
676
677 #define REG_VEC_MEM_BASE 0x0d00
678 #define REG_VEC_MEM_END 0x0e00
679
680 #define REG_VEC_MEM_MBAFF_L0_D 0x0d7c
681 #define REG_VEC_MEM_MBAFF_L1_D 0x0dfc
682
683 #define REG_VEC_MEM_SIZE (REG_VEC_MEM_END - REG_VEC_MEM_BASE)
684
685
686 #define REG_DMA0_SD_ADDR 0x1800
687 #define REG_DMA0_LCL_ADDR 0x1804
688 #define REG_DMA0_LENGTH 0x1808
689 #define REG_DMA1_SD_ADDR 0x1810
690 #define REG_DMA1_LCL_ADDR 0x1814
691 #define REG_DMA1_LENGTH 0x1818
692 #define REG_DMA2_SD_ADDR 0x1820
693 #define REG_DMA2_LCL_ADDR 0x1824
694 #define REG_DMA2_LENGTH 0x1828
695 #define REG_DMA3_SD_ADDR 0x1830
696 #define REG_DMA3_LCL_ADDR 0x1834
697 #define REG_DMA3_LENGTH 0x1838
698 #define REG_DMA_STATUS 0x1840
699 #define REG_DMA0_ACTIVE (1 << 0)
700 #define REG_DMA1_ACTIVE (1 << 1)
701 #define REG_DMA2_ACTIVE (1 << 2)
702 #define REG_DMA3_ACTIVE (1 << 3)
703
704 #define REG_DMA_ALL_ACTIVE REG_DMA0_ACTIVE | REG_DMA1_ACTIVE | \
705 REG_DMA2_ACTIVE | REG_DMA3_ACTIVE
706
707 #define DMA_MEM_BASE 0x1A00
708 #define DMA_MEM_SIZE 0x200
709 //; In bytes
710 #define MASK_DMA0_STATUS (1<<0)
711 #define MASK_DMA1_STATUS (1<<1)
712 #define MASK_DMA2_STATUS (1<<2)
713 #define MASK_DMA3_STATUS (1<<3)
714
715 #define DEBUG_LED 0x910
716
717
718 // Offsets to MVDATA
719 #define MVDATA_A 0x0
720 #define MVDATA_B 0xC
721 #define MVDATA_C 0x30
722 #define MVDATA_D 0x3C
723 #define MVDATA_LD_A 0x0
724 #define MVDATA_LD_B 0x8
725 #define MVDATA_LD_C 0x20
726 #define MVDATA_LD_D 0x28
727
728 #define MASK_MVDATA_X 0xFFFF
729 #define MASK_MVDATA_Y 0x7FFF0000
730 #define SHIFT_MVDATA_Y 16
731 #define MASK_MVDATA_VALID 0x80000000
732
733 #define REGIO_SINT_VEC_TOPPIC (REG_VEC_TOPPIC | IO_BASE)
734
735 #define REGIO_SINT_VEC_TOPREF (REG_VEC_TOPREF | IO_BASE)
736
737 #define REGIO_DEBUG_LED (DEBUG_LED | IO_BASE)
738
739
740 #define REG_WPRED_CTL 0x0340
741 #define REG_WPRED_SEL 0x0314
742
743
744
745 /*
746 ** The following do not appear in sv_chip_regmap.h
747 **
748 ** From code_in_pump.v:
749 */
750
751 #define DECODE_CIP_CIRC_START 0x00000A40
752 #define DECODE_CIP_CIRC_END 0x00000A44
753 #define DECODE_CIP_START 0x00000A48
754 #define DECODE_CIP_END 0x00000A4C
755 #define DECODE_CIP_CTL 0x00000A50
756
757 /* We define the range of the CIP block register address space... */
758 #define DECODE_CIP_BASE 0x00000A40
759 #define DECODE_CIP_BASEEND 0x00000A53
760
761 /* ...and the three flags in CIP_CTL. */
762 #define CIP_CTL_ENABLE 0x00000001
763 #define CIP_CTL_CMD_Q_EMPTY 0x00000002
764 #define CIP_CTL_DATA_Q_EMPTY 0x00000004
765 /*
766 ** These two macros are used to determine whether the CIP block has finished sending
767 ** data to the CI block. It is then safe to flush the CI block if required.
768 */
769 #define CIP_CTL_MASK ( CIP_CTL_ENABLE | CIP_CTL_CMD_Q_EMPTY | CIP_CTL_DATA_Q_EMPTY )
770 #define CIP_CTL_EMPTY ( CIP_CTL_CMD_Q_EMPTY | CIP_CTL_DATA_Q_EMPTY )
771
772
773 /*
774 ** Defines for the CodeIn control register:
775 */
776 #define CI_CTL_ENA 0x00000001
777 #define CI_CTL_EMU 0x00000002
778 #define CI_CTL_MCHN 0x00000004
779 #define CI_CTL_OWRT 0x00000008
780
781 #define CI_CTL_FLUSH 0x00000010
782 #define CI_CTL_NOBD 0x00000020
783
784 #define CI_CTL_ACT 0x00010000
785 #define CI_CTL_FULL 0x00020000
786 #define CI_CTL_ERR 0x00040000
787
788 #define CI_CTL_GET_ERRTYPE( x ) ( ( (x) >> 19U ) & 0x1F )
789
790 #define CI_CTL_BFULL 0x01000000
791
792
793 #endif
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