Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / vec.h
1 // This file was generated by the create_regs script
2 #define VEC_BASE 0x7e806000
3 #define VEC_REVID HW_REGISTER_RW( 0x7e806100 )
4 #define VEC_REVID_MASK 0xffffffff
5 #define VEC_REVID_WIDTH 32
6 #define VEC_CONFIG0 HW_REGISTER_RW( 0x7e806104 )
7 #define VEC_CONFIG0_MASK 0xffffffff
8 #define VEC_CONFIG0_WIDTH 32
9 #define VEC_SCHPH HW_REGISTER_RW( 0x7e806108 )
10 #define VEC_SCHPH_MASK 0xffffffff
11 #define VEC_SCHPH_WIDTH 32
12 #define VEC_SOFT_RESET HW_REGISTER_RW( 0x7e80610c )
13 #define VEC_SOFT_RESET_MASK 0xffffffff
14 #define VEC_SOFT_RESET_WIDTH 32
15 #define VEC_CPS01_CPS23 HW_REGISTER_RW( 0x7e806120 )
16 #define VEC_CPS01_CPS23_MASK 0xffffffff
17 #define VEC_CPS01_CPS23_WIDTH 32
18 #define VEC_CPS45_CPS67 HW_REGISTER_RW( 0x7e806124 )
19 #define VEC_CPS45_CPS67_MASK 0xffffffff
20 #define VEC_CPS45_CPS67_WIDTH 32
21 #define VEC_CPS89_CPS1011 HW_REGISTER_RW( 0x7e806128 )
22 #define VEC_CPS89_CPS1011_MASK 0xffffffff
23 #define VEC_CPS89_CPS1011_WIDTH 32
24 #define VEC_CPS1213_CPS1415 HW_REGISTER_RW( 0x7e80612c )
25 #define VEC_CPS1213_CPS1415_MASK 0xffffffff
26 #define VEC_CPS1213_CPS1415_WIDTH 32
27 #define VEC_CPS1617_CPS1819 HW_REGISTER_RW( 0x7e806130 )
28 #define VEC_CPS1617_CPS1819_MASK 0xffffffff
29 #define VEC_CPS1617_CPS1819_WIDTH 32
30 #define VEC_CPS2021_CPS2223 HW_REGISTER_RW( 0x7e806134 )
31 #define VEC_CPS2021_CPS2223_MASK 0xffffffff
32 #define VEC_CPS2021_CPS2223_WIDTH 32
33 #define VEC_CPS2425_CPS2627 HW_REGISTER_RW( 0x7e806138 )
34 #define VEC_CPS2425_CPS2627_MASK 0xffffffff
35 #define VEC_CPS2425_CPS2627_WIDTH 32
36 #define VEC_CPS2829_CPS3031 HW_REGISTER_RW( 0x7e80613c )
37 #define VEC_CPS2829_CPS3031_MASK 0xffffffff
38 #define VEC_CPS2829_CPS3031_WIDTH 32
39 #define VEC_CPS32_CPC HW_REGISTER_RW( 0x7e806140 )
40 #define VEC_CPS32_CPC_MASK 0xffffffff
41 #define VEC_CPS32_CPC_WIDTH 32
42 #define VEC_CLMP0_START HW_REGISTER_RW( 0x7e806144 )
43 #define VEC_CLMP0_START_MASK 0xffffffff
44 #define VEC_CLMP0_START_WIDTH 32
45 #define VEC_CLMP0_END HW_REGISTER_RW( 0x7e806148 )
46 #define VEC_CLMP0_END_MASK 0xffffffff
47 #define VEC_CLMP0_END_WIDTH 32
48 #define VEC_FREQ3_2 HW_REGISTER_RW( 0x7e806180 )
49 #define VEC_FREQ3_2_MASK 0xffffffff
50 #define VEC_FREQ3_2_WIDTH 32
51 #define VEC_FREQ1_0 HW_REGISTER_RW( 0x7e806184 )
52 #define VEC_FREQ1_0_MASK 0xffffffff
53 #define VEC_FREQ1_0_WIDTH 32
54 #define VEC_CONFIG1 HW_REGISTER_RW( 0x7e806188 )
55 #define VEC_CONFIG1_MASK 0xffffffff
56 #define VEC_CONFIG1_WIDTH 32
57 #define VEC_CONFIG2 HW_REGISTER_RW( 0x7e80618c )
58 #define VEC_CONFIG2_MASK 0xffffffff
59 #define VEC_CONFIG2_WIDTH 32
60 #define VEC_INTERRUPT_CONTROL HW_REGISTER_RW( 0x7e806190 )
61 #define VEC_INTERRUPT_CONTROL_MASK 0xffffffff
62 #define VEC_INTERRUPT_CONTROL_WIDTH 32
63 #define VEC_INTERRUPT_STATUS HW_REGISTER_RW( 0x7e806194 )
64 #define VEC_INTERRUPT_STATUS_MASK 0xffffffff
65 #define VEC_INTERRUPT_STATUS_WIDTH 32
66 #define VEC_FCW_SECAM_B HW_REGISTER_RW( 0x7e806198 )
67 #define VEC_FCW_SECAM_B_MASK 0xffffffff
68 #define VEC_FCW_SECAM_B_WIDTH 32
69 #define VEC_SECAM_GAIN_VAL HW_REGISTER_RW( 0x7e80619c )
70 #define VEC_SECAM_GAIN_VAL_MASK 0xffffffff
71 #define VEC_SECAM_GAIN_VAL_WIDTH 32
72 #define VEC_CONFIG3 HW_REGISTER_RW( 0x7e8061a0 )
73 #define VEC_CONFIG3_MASK 0xffffffff
74 #define VEC_CONFIG3_WIDTH 32
75 #define VEC_CONFIG4 HW_REGISTER_RW( 0x7e8061a4 )
76 #define VEC_CONFIG4_MASK 0xffffffff
77 #define VEC_CONFIG4_WIDTH 32
78 #define VEC_STATUS0 HW_REGISTER_RW( 0x7e806200 )
79 #define VEC_STATUS0_MASK 0xffffffff
80 #define VEC_STATUS0_WIDTH 32
81 #define VEC_MASK0 HW_REGISTER_RW( 0x7e806204 )
82 #define VEC_MASK0_MASK 0xffffffff
83 #define VEC_MASK0_WIDTH 32
84 #define VEC_CFG HW_REGISTER_RW( 0x7e806208 )
85 #define VEC_CFG_MASK 0xffffffff
86 #define VEC_CFG_WIDTH 32
87 #define VEC_DAC_TEST HW_REGISTER_RW( 0x7e80620c )
88 #define VEC_DAC_TEST_MASK 0xffffffff
89 #define VEC_DAC_TEST_WIDTH 32
90 #define VEC_DAC_CONFIG HW_REGISTER_RW( 0x7e806210 )
91 #define VEC_DAC_CONFIG_MASK 0xffffffff
92 #define VEC_DAC_CONFIG_WIDTH 32
93 #define VEC_DAC_MISC HW_REGISTER_RW( 0x7e806214 )
94 #define VEC_DAC_MISC_MASK 0xffffffff
95 #define VEC_DAC_MISC_WIDTH 32
96 #define VEC_WSE_RESET HW_REGISTER_RW( 0x7e8060c0 )
97 #define VEC_WSE_RESET_MASK 0xffffffff
98 #define VEC_WSE_RESET_WIDTH 32
99 #define VEC_WSE_CONTROL HW_REGISTER_RW( 0x7e8060c4 )
100 #define VEC_WSE_CONTROL_MASK 0xffffffff
101 #define VEC_WSE_CONTROL_WIDTH 32
102 #define VEC_WSE_WSS_DATA HW_REGISTER_RW( 0x7e8060c8 )
103 #define VEC_WSE_WSS_DATA_MASK 0xffffffff
104 #define VEC_WSE_WSS_DATA_WIDTH 32
105 #define VEC_WSE_VPS_DATA_1 HW_REGISTER_RW( 0x7e8060cc )
106 #define VEC_WSE_VPS_DATA_1_MASK 0xffffffff
107 #define VEC_WSE_VPS_DATA_1_WIDTH 32
108 #define VEC_WSE_VPS_CONTROL HW_REGISTER_RW( 0x7e8060d0 )
109 #define VEC_WSE_VPS_CONTROL_MASK 0xffffffff
110 #define VEC_WSE_VPS_CONTROL_WIDTH 32
111 #define VEC_CGMSAE_TOP_CONTROL HW_REGISTER_RW( 0x7e806044 )
112 #define VEC_CGMSAE_TOP_CONTROL_MASK 0xffffffff
113 #define VEC_CGMSAE_TOP_CONTROL_WIDTH 32
114 #define VEC_CGMSAE_RESET HW_REGISTER_RW( 0x7e806040 )
115 #define VEC_CGMSAE_RESET_MASK 0xffffffff
116 #define VEC_CGMSAE_RESET_WIDTH 32
117 #define VEC_CGMSAE_BOT_CONTROL HW_REGISTER_RW( 0x7e806048 )
118 #define VEC_CGMSAE_BOT_CONTROL_MASK 0xffffffff
119 #define VEC_CGMSAE_BOT_CONTROL_WIDTH 32
120 #define VEC_CGMSAE_TOP_FORMAT HW_REGISTER_RW( 0x7e80604c )
121 #define VEC_CGMSAE_TOP_FORMAT_MASK 0xffffffff
122 #define VEC_CGMSAE_TOP_FORMAT_WIDTH 32
123 #define VEC_CGMSAE_BOT_FORMAT HW_REGISTER_RW( 0x7e806050 )
124 #define VEC_CGMSAE_BOT_FORMAT_MASK 0xffffffff
125 #define VEC_CGMSAE_BOT_FORMAT_WIDTH 32
126 #define VEC_CGMSAE_TOP_DATA HW_REGISTER_RW( 0x7e806054 )
127 #define VEC_CGMSAE_TOP_DATA_MASK 0xffffffff
128 #define VEC_CGMSAE_TOP_DATA_WIDTH 32
129 #define VEC_CGMSAE_BOT_DATA HW_REGISTER_RW( 0x7e806058 )
130 #define VEC_CGMSAE_BOT_DATA_MASK 0xffffffff
131 #define VEC_CGMSAE_BOT_DATA_WIDTH 32
132 #define VEC_CGMSAE_REVID HW_REGISTER_RW( 0x7e80605c )
133 #define VEC_CGMSAE_REVID_MASK 0xffffffff
134 #define VEC_CGMSAE_REVID_WIDTH 32
135 #define VEC_ENC_RevID HW_REGISTER_RW( 0x7e806060 )
136 #define VEC_ENC_RevID_MASK 0xffffffff
137 #define VEC_ENC_RevID_WIDTH 32
138 #define VEC_ENC_PrimaryControl HW_REGISTER_RW( 0x7e806068 )
139 #define VEC_ENC_PrimaryControl_MASK 0xffffffff
140 #define VEC_ENC_PrimaryControl_WIDTH 32
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