690fb818f307ac362bbecb19b9729195a3acdb09
[rpi-open-firmware.git] / bcm2708_chip / vpu_arb_ctrl.h
1 // This file was generated by the create_regs script
2 #define VPU_ARB_CTRL_BASE 0x7ee04000
3 #define VPU_ARB_CTRL_UC HW_REGISTER_RW( 0x7ee04000 )
4 #define VPU_ARB_CTRL_UC_MASK 0x0000ffff
5 #define VPU_ARB_CTRL_UC_WIDTH 16
6 #define VPU_ARB_CTRL_UC_RESET 0000000000
7 #define VPU_ARB_CTRL_UC_CHANNEL_INIBIT_BITS 15:8
8 #define VPU_ARB_CTRL_UC_CHANNEL_INIBIT_SET 0x0000ff00
9 #define VPU_ARB_CTRL_UC_CHANNEL_INIBIT_CLR 0xffff00ff
10 #define VPU_ARB_CTRL_UC_CHANNEL_INIBIT_MSB 15
11 #define VPU_ARB_CTRL_UC_CHANNEL_INIBIT_LSB 8
12 #define VPU_ARB_CTRL_UC_CHANNEL_INIBIT_RESET 0x0
13 #define VPU_ARB_CTRL_UC_ALGORITHM_BITS 7:6
14 #define VPU_ARB_CTRL_UC_ALGORITHM_SET 0x000000c0
15 #define VPU_ARB_CTRL_UC_ALGORITHM_CLR 0xffffff3f
16 #define VPU_ARB_CTRL_UC_ALGORITHM_MSB 7
17 #define VPU_ARB_CTRL_UC_ALGORITHM_LSB 6
18 #define VPU_ARB_CTRL_UC_ALGORITHM_RESET 0x0
19 #define VPU_ARB_CTRL_UC_THRESHOLD_BITS 5:4
20 #define VPU_ARB_CTRL_UC_THRESHOLD_SET 0x00000030
21 #define VPU_ARB_CTRL_UC_THRESHOLD_CLR 0xffffffcf
22 #define VPU_ARB_CTRL_UC_THRESHOLD_MSB 5
23 #define VPU_ARB_CTRL_UC_THRESHOLD_LSB 4
24 #define VPU_ARB_CTRL_UC_THRESHOLD_RESET 0x0
25 #define VPU_ARB_CTRL_UC_DELAY_BITS 3:2
26 #define VPU_ARB_CTRL_UC_DELAY_SET 0x0000000c
27 #define VPU_ARB_CTRL_UC_DELAY_CLR 0xfffffff3
28 #define VPU_ARB_CTRL_UC_DELAY_MSB 3
29 #define VPU_ARB_CTRL_UC_DELAY_LSB 2
30 #define VPU_ARB_CTRL_UC_DELAY_RESET 0x0
31 #define VPU_ARB_CTRL_UC_LIMIT_BITS 1:0
32 #define VPU_ARB_CTRL_UC_LIMIT_SET 0x00000003
33 #define VPU_ARB_CTRL_UC_LIMIT_CLR 0xfffffffc
34 #define VPU_ARB_CTRL_UC_LIMIT_MSB 1
35 #define VPU_ARB_CTRL_UC_LIMIT_LSB 0
36 #define VPU_ARB_CTRL_UC_LIMIT_RESET 0x0
37 #define VPU_ARB_CTRL_L2 HW_REGISTER_RW( 0x7ee04004 )
38 #define VPU_ARB_CTRL_L2_MASK 0x0000ffff
39 #define VPU_ARB_CTRL_L2_WIDTH 16
40 #define VPU_ARB_CTRL_L2_RESET 0000000000
41 #define VPU_ARB_CTRL_L2_CHANNEL_INIBIT_BITS 15:8
42 #define VPU_ARB_CTRL_L2_CHANNEL_INIBIT_SET 0x0000ff00
43 #define VPU_ARB_CTRL_L2_CHANNEL_INIBIT_CLR 0xffff00ff
44 #define VPU_ARB_CTRL_L2_CHANNEL_INIBIT_MSB 15
45 #define VPU_ARB_CTRL_L2_CHANNEL_INIBIT_LSB 8
46 #define VPU_ARB_CTRL_L2_CHANNEL_INIBIT_RESET 0x0
47 #define VPU_ARB_CTRL_L2_ALGORITHM_BITS 7:6
48 #define VPU_ARB_CTRL_L2_ALGORITHM_SET 0x000000c0
49 #define VPU_ARB_CTRL_L2_ALGORITHM_CLR 0xffffff3f
50 #define VPU_ARB_CTRL_L2_ALGORITHM_MSB 7
51 #define VPU_ARB_CTRL_L2_ALGORITHM_LSB 6
52 #define VPU_ARB_CTRL_L2_ALGORITHM_RESET 0x0
53 #define VPU_ARB_CTRL_L2_THRESHOLD_BITS 5:4
54 #define VPU_ARB_CTRL_L2_THRESHOLD_SET 0x00000030
55 #define VPU_ARB_CTRL_L2_THRESHOLD_CLR 0xffffffcf
56 #define VPU_ARB_CTRL_L2_THRESHOLD_MSB 5
57 #define VPU_ARB_CTRL_L2_THRESHOLD_LSB 4
58 #define VPU_ARB_CTRL_L2_THRESHOLD_RESET 0x0
59 #define VPU_ARB_CTRL_L2_DELAY_BITS 3:2
60 #define VPU_ARB_CTRL_L2_DELAY_SET 0x0000000c
61 #define VPU_ARB_CTRL_L2_DELAY_CLR 0xfffffff3
62 #define VPU_ARB_CTRL_L2_DELAY_MSB 3
63 #define VPU_ARB_CTRL_L2_DELAY_LSB 2
64 #define VPU_ARB_CTRL_L2_DELAY_RESET 0x0
65 #define VPU_ARB_CTRL_L2_LIMIT_BITS 1:0
66 #define VPU_ARB_CTRL_L2_LIMIT_SET 0x00000003
67 #define VPU_ARB_CTRL_L2_LIMIT_CLR 0xfffffffc
68 #define VPU_ARB_CTRL_L2_LIMIT_MSB 1
69 #define VPU_ARB_CTRL_L2_LIMIT_LSB 0
70 #define VPU_ARB_CTRL_L2_LIMIT_RESET 0x0
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