Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / bcm2708_chip / vpu_l1_cache_ctrl.h
1 // This file was generated by the create_regs script
2 #define L1_BASE 0x7ee02000
3 #define L1_APB_ID 0x4c314343
4 #define L1_IC0_CONTROL HW_REGISTER_RW( 0x7ee02000 )
5 #define L1_IC0_CONTROL_MASK 0x0000007f
6 #define L1_IC0_CONTROL_WIDTH 7
7 #define L1_IC0_CONTROL_RESET 0000000000
8 #define L1_IC0_CONTROL_DISABLE_VLINE_BITS 6:5
9 #define L1_IC0_CONTROL_DISABLE_VLINE_SET 0x00000060
10 #define L1_IC0_CONTROL_DISABLE_VLINE_CLR 0xffffff9f
11 #define L1_IC0_CONTROL_DISABLE_VLINE_MSB 6
12 #define L1_IC0_CONTROL_DISABLE_VLINE_LSB 5
13 #define L1_IC0_CONTROL_RAS_DISABLE_BITS 4:4
14 #define L1_IC0_CONTROL_RAS_DISABLE_SET 0x00000010
15 #define L1_IC0_CONTROL_RAS_DISABLE_CLR 0xffffffef
16 #define L1_IC0_CONTROL_RAS_DISABLE_MSB 4
17 #define L1_IC0_CONTROL_RAS_DISABLE_LSB 4
18 #define L1_IC0_CONTROL_BP_DISABLE_BITS 3:3
19 #define L1_IC0_CONTROL_BP_DISABLE_SET 0x00000008
20 #define L1_IC0_CONTROL_BP_DISABLE_CLR 0xfffffff7
21 #define L1_IC0_CONTROL_BP_DISABLE_MSB 3
22 #define L1_IC0_CONTROL_BP_DISABLE_LSB 3
23 #define L1_IC0_CONTROL_ENABLE_STATS_BITS 2:2
24 #define L1_IC0_CONTROL_ENABLE_STATS_SET 0x00000004
25 #define L1_IC0_CONTROL_ENABLE_STATS_CLR 0xfffffffb
26 #define L1_IC0_CONTROL_ENABLE_STATS_MSB 2
27 #define L1_IC0_CONTROL_ENABLE_STATS_LSB 2
28 #define L1_IC0_CONTROL_START_FLUSH_BITS 1:1
29 #define L1_IC0_CONTROL_START_FLUSH_SET 0x00000002
30 #define L1_IC0_CONTROL_START_FLUSH_CLR 0xfffffffd
31 #define L1_IC0_CONTROL_START_FLUSH_MSB 1
32 #define L1_IC0_CONTROL_START_FLUSH_LSB 1
33 #define L1_IC0_CONTROL_DISABLE_BITS 0:0
34 #define L1_IC0_CONTROL_DISABLE_SET 0x00000001
35 #define L1_IC0_CONTROL_DISABLE_CLR 0xfffffffe
36 #define L1_IC0_CONTROL_DISABLE_MSB 0
37 #define L1_IC0_CONTROL_DISABLE_LSB 0
38 #define L1_IC0_PRIORITY HW_REGISTER_RW( 0x7ee02004 )
39 #define L1_IC0_PRIORITY_MASK 0x0000ffff
40 #define L1_IC0_PRIORITY_WIDTH 16
41 #define L1_IC0_PRIORITY_RESET 0x000034af
42 #define L1_IC0_PRIORITY_IC0_APRIORITY0_BITS 3:0
43 #define L1_IC0_PRIORITY_IC0_APRIORITY0_SET 0x0000000f
44 #define L1_IC0_PRIORITY_IC0_APRIORITY0_CLR 0xfffffff0
45 #define L1_IC0_PRIORITY_IC0_APRIORITY0_MSB 3
46 #define L1_IC0_PRIORITY_IC0_APRIORITY0_LSB 0
47 #define L1_IC0_PRIORITY_IC0_APRIORITY1_BITS 7:4
48 #define L1_IC0_PRIORITY_IC0_APRIORITY1_SET 0x000000f0
49 #define L1_IC0_PRIORITY_IC0_APRIORITY1_CLR 0xffffff0f
50 #define L1_IC0_PRIORITY_IC0_APRIORITY1_MSB 7
51 #define L1_IC0_PRIORITY_IC0_APRIORITY1_LSB 4
52 #define L1_IC0_PRIORITY_IC0_APRIORITY2_BITS 11:8
53 #define L1_IC0_PRIORITY_IC0_APRIORITY2_SET 0x00000f00
54 #define L1_IC0_PRIORITY_IC0_APRIORITY2_CLR 0xfffff0ff
55 #define L1_IC0_PRIORITY_IC0_APRIORITY2_MSB 11
56 #define L1_IC0_PRIORITY_IC0_APRIORITY2_LSB 8
57 #define L1_IC0_PRIORITY_IC0_APRIORITY3_BITS 15:12
58 #define L1_IC0_PRIORITY_IC0_APRIORITY3_SET 0x0000f000
59 #define L1_IC0_PRIORITY_IC0_APRIORITY3_CLR 0xffff0fff
60 #define L1_IC0_PRIORITY_IC0_APRIORITY3_MSB 15
61 #define L1_IC0_PRIORITY_IC0_APRIORITY3_LSB 12
62 #define L1_IC0_FLUSH_S HW_REGISTER_RW( 0x7ee02008 )
63 #define L1_IC0_FLUSH_S_MASK 0xffffffe0
64 #define L1_IC0_FLUSH_S_WIDTH 32
65 #define L1_IC0_FLUSH_S_RESET 0000000000
66 #define L1_IC0_FLUSH_E HW_REGISTER_RW( 0x7ee0200c )
67 #define L1_IC0_FLUSH_E_MASK 0xffffffe0
68 #define L1_IC0_FLUSH_E_WIDTH 32
69 #define L1_IC0_FLUSH_E_RESET 0xffffffff
70 #define L1_IC0_RD_HITS HW_REGISTER_RW( 0x7ee02040 )
71 #define L1_IC0_RD_HITS_MASK 0000000000
72 #define L1_IC0_RD_HITS_WIDTH 0
73 #define L1_IC0_RD_MISSES HW_REGISTER_RO( 0x7ee02044 )
74 #define L1_IC0_RD_MISSES_MASK 0000000000
75 #define L1_IC0_RD_MISSES_WIDTH 0
76 #define L1_IC0_BP_HITS HW_REGISTER_RO( 0x7ee02048 )
77 #define L1_IC0_BP_HITS_MASK 0000000000
78 #define L1_IC0_BP_HITS_WIDTH 0
79 #define L1_IC0_BP_MISSES HW_REGISTER_RO( 0x7ee0204c )
80 #define L1_IC0_BP_MISSES_MASK 0000000000
81 #define L1_IC0_BP_MISSES_WIDTH 0
82 #define L1_IC0_RAS_PUSHES HW_REGISTER_RO( 0x7ee02050 )
83 #define L1_IC0_RAS_PUSHES_MASK 0000000000
84 #define L1_IC0_RAS_PUSHES_WIDTH 0
85 #define L1_IC0_RAS_POPS HW_REGISTER_RO( 0x7ee02054 )
86 #define L1_IC0_RAS_POPS_MASK 0000000000
87 #define L1_IC0_RAS_POPS_WIDTH 0
88 #define L1_IC0_RAS_UNDERFLOW HW_REGISTER_RO( 0x7ee02058 )
89 #define L1_IC0_RAS_UNDERFLOW_MASK 0000000000
90 #define L1_IC0_RAS_UNDERFLOW_WIDTH 0
91 #define L1_IC1_CONTROL HW_REGISTER_RW( 0x7ee02080 )
92 #define L1_IC1_CONTROL_MASK 0x0000007f
93 #define L1_IC1_CONTROL_WIDTH 7
94 #define L1_IC1_CONTROL_RESET 0000000000
95 #define L1_IC1_CONTROL_DISABLE_VLINE_BITS 6:5
96 #define L1_IC1_CONTROL_DISABLE_VLINE_SET 0x00000060
97 #define L1_IC1_CONTROL_DISABLE_VLINE_CLR 0xffffff9f
98 #define L1_IC1_CONTROL_DISABLE_VLINE_MSB 6
99 #define L1_IC1_CONTROL_DISABLE_VLINE_LSB 5
100 #define L1_IC1_CONTROL_RAS_DISABLE_BITS 4:4
101 #define L1_IC1_CONTROL_RAS_DISABLE_SET 0x00000010
102 #define L1_IC1_CONTROL_RAS_DISABLE_CLR 0xffffffef
103 #define L1_IC1_CONTROL_RAS_DISABLE_MSB 4
104 #define L1_IC1_CONTROL_RAS_DISABLE_LSB 4
105 #define L1_IC1_CONTROL_BP_DISABLE_BITS 3:3
106 #define L1_IC1_CONTROL_BP_DISABLE_SET 0x00000008
107 #define L1_IC1_CONTROL_BP_DISABLE_CLR 0xfffffff7
108 #define L1_IC1_CONTROL_BP_DISABLE_MSB 3
109 #define L1_IC1_CONTROL_BP_DISABLE_LSB 3
110 #define L1_IC1_CONTROL_ENABLE_STATS_BITS 2:2
111 #define L1_IC1_CONTROL_ENABLE_STATS_SET 0x00000004
112 #define L1_IC1_CONTROL_ENABLE_STATS_CLR 0xfffffffb
113 #define L1_IC1_CONTROL_ENABLE_STATS_MSB 2
114 #define L1_IC1_CONTROL_ENABLE_STATS_LSB 2
115 #define L1_IC1_CONTROL_START_FLUSH_BITS 1:1
116 #define L1_IC1_CONTROL_START_FLUSH_SET 0x00000002
117 #define L1_IC1_CONTROL_START_FLUSH_CLR 0xfffffffd
118 #define L1_IC1_CONTROL_START_FLUSH_MSB 1
119 #define L1_IC1_CONTROL_START_FLUSH_LSB 1
120 #define L1_IC1_CONTROL_DISABLE_BITS 0:0
121 #define L1_IC1_CONTROL_DISABLE_SET 0x00000001
122 #define L1_IC1_CONTROL_DISABLE_CLR 0xfffffffe
123 #define L1_IC1_CONTROL_DISABLE_MSB 0
124 #define L1_IC1_CONTROL_DISABLE_LSB 0
125 #define L1_IC1_PRIORITY HW_REGISTER_RW( 0x7ee02084 )
126 #define L1_IC1_PRIORITY_MASK 0x0000ffff
127 #define L1_IC1_PRIORITY_WIDTH 16
128 #define L1_IC1_PRIORITY_RESET 0x000034af
129 #define L1_IC1_PRIORITY_IC1_APRIORITY0_BITS 3:0
130 #define L1_IC1_PRIORITY_IC1_APRIORITY0_SET 0x0000000f
131 #define L1_IC1_PRIORITY_IC1_APRIORITY0_CLR 0xfffffff0
132 #define L1_IC1_PRIORITY_IC1_APRIORITY0_MSB 3
133 #define L1_IC1_PRIORITY_IC1_APRIORITY0_LSB 0
134 #define L1_IC1_PRIORITY_IC1_APRIORITY1_BITS 7:4
135 #define L1_IC1_PRIORITY_IC1_APRIORITY1_SET 0x000000f0
136 #define L1_IC1_PRIORITY_IC1_APRIORITY1_CLR 0xffffff0f
137 #define L1_IC1_PRIORITY_IC1_APRIORITY1_MSB 7
138 #define L1_IC1_PRIORITY_IC1_APRIORITY1_LSB 4
139 #define L1_IC1_PRIORITY_IC1_APRIORITY2_BITS 11:8
140 #define L1_IC1_PRIORITY_IC1_APRIORITY2_SET 0x00000f00
141 #define L1_IC1_PRIORITY_IC1_APRIORITY2_CLR 0xfffff0ff
142 #define L1_IC1_PRIORITY_IC1_APRIORITY2_MSB 11
143 #define L1_IC1_PRIORITY_IC1_APRIORITY2_LSB 8
144 #define L1_IC1_PRIORITY_IC1_APRIORITY3_BITS 15:12
145 #define L1_IC1_PRIORITY_IC1_APRIORITY3_SET 0x0000f000
146 #define L1_IC1_PRIORITY_IC1_APRIORITY3_CLR 0xffff0fff
147 #define L1_IC1_PRIORITY_IC1_APRIORITY3_MSB 15
148 #define L1_IC1_PRIORITY_IC1_APRIORITY3_LSB 12
149 #define L1_IC1_FLUSH_S HW_REGISTER_RW( 0x7ee02088 )
150 #define L1_IC1_FLUSH_S_MASK 0xffffffe0
151 #define L1_IC1_FLUSH_S_WIDTH 32
152 #define L1_IC1_FLUSH_S_RESET 0000000000
153 #define L1_IC1_FLUSH_E HW_REGISTER_RW( 0x7ee0208c )
154 #define L1_IC1_FLUSH_E_MASK 0xffffffe0
155 #define L1_IC1_FLUSH_E_WIDTH 32
156 #define L1_IC1_FLUSH_E_RESET 0xffffffff
157 #define L1_IC1_RD_HITS HW_REGISTER_RW( 0x7ee020c0 )
158 #define L1_IC1_RD_HITS_MASK 0000000000
159 #define L1_IC1_RD_HITS_WIDTH 0
160 #define L1_IC1_RD_MISSES HW_REGISTER_RO( 0x7ee020c4 )
161 #define L1_IC1_RD_MISSES_MASK 0000000000
162 #define L1_IC1_RD_MISSES_WIDTH 0
163 #define L1_IC1_BP_HITS HW_REGISTER_RO( 0x7ee020c8 )
164 #define L1_IC1_BP_HITS_MASK 0000000000
165 #define L1_IC1_BP_HITS_WIDTH 0
166 #define L1_IC1_BP_MISSES HW_REGISTER_RO( 0x7ee020cc )
167 #define L1_IC1_BP_MISSES_MASK 0000000000
168 #define L1_IC1_BP_MISSES_WIDTH 0
169 #define L1_IC1_RAS_PUSHES HW_REGISTER_RO( 0x7ee020d0 )
170 #define L1_IC1_RAS_PUSHES_MASK 0000000000
171 #define L1_IC1_RAS_PUSHES_WIDTH 0
172 #define L1_IC1_RAS_POPS HW_REGISTER_RO( 0x7ee020d4 )
173 #define L1_IC1_RAS_POPS_MASK 0000000000
174 #define L1_IC1_RAS_POPS_WIDTH 0
175 #define L1_IC1_RAS_UNDERFLOW HW_REGISTER_RO( 0x7ee020d8 )
176 #define L1_IC1_RAS_UNDERFLOW_MASK 0000000000
177 #define L1_IC1_RAS_UNDERFLOW_WIDTH 0
178 #define L1_D_CONTROL HW_REGISTER_RW( 0x7ee02100 )
179 #define L1_D_CONTROL_MASK 0x0000000f
180 #define L1_D_CONTROL_WIDTH 4
181 #define L1_D_CONTROL_RESET 0000000000
182 #define L1_D_CONTROL_DC_EN_STATS_BITS 3:3
183 #define L1_D_CONTROL_DC_EN_STATS_SET 0x00000008
184 #define L1_D_CONTROL_DC_EN_STATS_CLR 0xfffffff7
185 #define L1_D_CONTROL_DC_EN_STATS_MSB 3
186 #define L1_D_CONTROL_DC_EN_STATS_LSB 3
187 #define L1_D_CONTROL_DC1_FLUSH_BITS 2:2
188 #define L1_D_CONTROL_DC1_FLUSH_SET 0x00000004
189 #define L1_D_CONTROL_DC1_FLUSH_CLR 0xfffffffb
190 #define L1_D_CONTROL_DC1_FLUSH_MSB 2
191 #define L1_D_CONTROL_DC1_FLUSH_LSB 2
192 #define L1_D_CONTROL_DC0_FLUSH_BITS 1:1
193 #define L1_D_CONTROL_DC0_FLUSH_SET 0x00000002
194 #define L1_D_CONTROL_DC0_FLUSH_CLR 0xfffffffd
195 #define L1_D_CONTROL_DC0_FLUSH_MSB 1
196 #define L1_D_CONTROL_DC0_FLUSH_LSB 1
197 #define L1_D_CONTROL_DC_DISABLE_BITS 0:0
198 #define L1_D_CONTROL_DC_DISABLE_SET 0x00000001
199 #define L1_D_CONTROL_DC_DISABLE_CLR 0xfffffffe
200 #define L1_D_CONTROL_DC_DISABLE_MSB 0
201 #define L1_D_CONTROL_DC_DISABLE_LSB 0
202 #define L1_D_FLUSH_S HW_REGISTER_RW( 0x7ee02104 )
203 #define L1_D_FLUSH_S_MASK 0x3fffffe0
204 #define L1_D_FLUSH_S_WIDTH 30
205 #define L1_D_FLUSH_S_RESET 0000000000
206 #define L1_D_FLUSH_E HW_REGISTER_RW( 0x7ee02108 )
207 #define L1_D_FLUSH_E_MASK 0x3fffffe0
208 #define L1_D_FLUSH_E_WIDTH 30
209 #define L1_D_FLUSH_E_RESET 0x3fffffff
210 #define L1_D_PRIORITY HW_REGISTER_RW( 0x7ee0210c )
211 #define L1_D_PRIORITY_MASK 0x0fff0fff
212 #define L1_D_PRIORITY_WIDTH 28
213 #define L1_D_PRIORITY_RESET 0000000000
214 #define L1_D_PRIORITY_c0_l2_priority_BITS 3:0
215 #define L1_D_PRIORITY_c0_l2_priority_SET 0x0000000f
216 #define L1_D_PRIORITY_c0_l2_priority_CLR 0xfffffff0
217 #define L1_D_PRIORITY_c0_l2_priority_MSB 3
218 #define L1_D_PRIORITY_c0_l2_priority_LSB 0
219 #define L1_D_PRIORITY_c0_uc_priority_BITS 7:4
220 #define L1_D_PRIORITY_c0_uc_priority_SET 0x000000f0
221 #define L1_D_PRIORITY_c0_uc_priority_CLR 0xffffff0f
222 #define L1_D_PRIORITY_c0_uc_priority_MSB 7
223 #define L1_D_PRIORITY_c0_uc_priority_LSB 4
224 #define L1_D_PRIORITY_c0_per_priority_BITS 11:8
225 #define L1_D_PRIORITY_c0_per_priority_SET 0x00000f00
226 #define L1_D_PRIORITY_c0_per_priority_CLR 0xfffff0ff
227 #define L1_D_PRIORITY_c0_per_priority_MSB 11
228 #define L1_D_PRIORITY_c0_per_priority_LSB 8
229 #define L1_D_PRIORITY_c1_l2_priority_BITS 19:16
230 #define L1_D_PRIORITY_c1_l2_priority_SET 0x000f0000
231 #define L1_D_PRIORITY_c1_l2_priority_CLR 0xfff0ffff
232 #define L1_D_PRIORITY_c1_l2_priority_MSB 19
233 #define L1_D_PRIORITY_c1_l2_priority_LSB 16
234 #define L1_D_PRIORITY_c1_uc_priority_BITS 23:20
235 #define L1_D_PRIORITY_c1_uc_priority_SET 0x00f00000
236 #define L1_D_PRIORITY_c1_uc_priority_CLR 0xff0fffff
237 #define L1_D_PRIORITY_c1_uc_priority_MSB 23
238 #define L1_D_PRIORITY_c1_uc_priority_LSB 20
239 #define L1_D_PRIORITY_c1_per_priority_BITS 27:24
240 #define L1_D_PRIORITY_c1_per_priority_SET 0x0f000000
241 #define L1_D_PRIORITY_c1_per_priority_CLR 0xf0ffffff
242 #define L1_D_PRIORITY_c1_per_priority_MSB 27
243 #define L1_D_PRIORITY_c1_per_priority_LSB 24
244 #define L1_D0_RD_HITS HW_REGISTER_RW( 0x7ee02140 )
245 #define L1_D0_RD_HITS_MASK 0000000000
246 #define L1_D0_RD_HITS_WIDTH 0
247 #define L1_D0_RD_SNOOPS HW_REGISTER_RO( 0x7ee02144 )
248 #define L1_D0_RD_SNOOPS_MASK 0000000000
249 #define L1_D0_RD_SNOOPS_WIDTH 0
250 #define L1_D0_RD_MISSES HW_REGISTER_RO( 0x7ee02148 )
251 #define L1_D0_RD_MISSES_MASK 0000000000
252 #define L1_D0_RD_MISSES_WIDTH 0
253 #define L1_D0_RD_THRUS HW_REGISTER_RO( 0x7ee0214c )
254 #define L1_D0_RD_THRUS_MASK 0000000000
255 #define L1_D0_RD_THRUS_WIDTH 0
256 #define L1_D0_WR_HITS HW_REGISTER_RO( 0x7ee02150 )
257 #define L1_D0_WR_HITS_MASK 0000000000
258 #define L1_D0_WR_HITS_WIDTH 0
259 #define L1_D0_WR_SNOOPS HW_REGISTER_RO( 0x7ee02154 )
260 #define L1_D0_WR_SNOOPS_MASK 0000000000
261 #define L1_D0_WR_SNOOPS_WIDTH 0
262 #define L1_D0_WR_MISSES HW_REGISTER_RO( 0x7ee02158 )
263 #define L1_D0_WR_MISSES_MASK 0000000000
264 #define L1_D0_WR_MISSES_WIDTH 0
265 #define L1_D0_WR_THRUS HW_REGISTER_RO( 0x7ee0215c )
266 #define L1_D0_WR_THRUS_MASK 0000000000
267 #define L1_D0_WR_THRUS_WIDTH 0
268 #define L1_D0_WBACKS HW_REGISTER_RO( 0x7ee02160 )
269 #define L1_D0_WBACKS_MASK 0000000000
270 #define L1_D0_WBACKS_WIDTH 0
271 #define L1_D1_RD_HITS HW_REGISTER_RW( 0x7ee02180 )
272 #define L1_D1_RD_HITS_MASK 0000000000
273 #define L1_D1_RD_HITS_WIDTH 0
274 #define L1_D1_RD_SNOOPS HW_REGISTER_RO( 0x7ee02184 )
275 #define L1_D1_RD_SNOOPS_MASK 0000000000
276 #define L1_D1_RD_SNOOPS_WIDTH 0
277 #define L1_D1_RD_MISSES HW_REGISTER_RO( 0x7ee02188 )
278 #define L1_D1_RD_MISSES_MASK 0000000000
279 #define L1_D1_RD_MISSES_WIDTH 0
280 #define L1_D1_RD_THRUS HW_REGISTER_RO( 0x7ee0218c )
281 #define L1_D1_RD_THRUS_MASK 0000000000
282 #define L1_D1_RD_THRUS_WIDTH 0
283 #define L1_D1_WR_HITS HW_REGISTER_RO( 0x7ee02190 )
284 #define L1_D1_WR_HITS_MASK 0000000000
285 #define L1_D1_WR_HITS_WIDTH 0
286 #define L1_D1_WR_SNOOPS HW_REGISTER_RO( 0x7ee02194 )
287 #define L1_D1_WR_SNOOPS_MASK 0000000000
288 #define L1_D1_WR_SNOOPS_WIDTH 0
289 #define L1_D1_WR_MISSES HW_REGISTER_RO( 0x7ee02198 )
290 #define L1_D1_WR_MISSES_MASK 0000000000
291 #define L1_D1_WR_MISSES_WIDTH 0
292 #define L1_D1_WR_THRUS HW_REGISTER_RO( 0x7ee0219c )
293 #define L1_D1_WR_THRUS_MASK 0000000000
294 #define L1_D1_WR_THRUS_WIDTH 0
295 #define L1_D1_WBACKS HW_REGISTER_RO( 0x7ee021a0 )
296 #define L1_D1_WBACKS_MASK 0000000000
297 #define L1_D1_WBACKS_WIDTH 0
298 #define L1_L1_SANDBOX_START0 HW_REGISTER_RW( 0x7ee02800 )
299 #define L1_L1_SANDBOX_START0_MASK 0x3fffffff
300 #define L1_L1_SANDBOX_START0_WIDTH 30
301 #define L1_L1_SANDBOX_START0_RESET 0x00000007
302 #define L1_L1_SANDBOX_START0_START_ADDR_BITS 29:5
303 #define L1_L1_SANDBOX_START0_START_ADDR_SET 0x3fffffe0
304 #define L1_L1_SANDBOX_START0_START_ADDR_CLR 0xc000001f
305 #define L1_L1_SANDBOX_START0_START_ADDR_MSB 29
306 #define L1_L1_SANDBOX_START0_START_ADDR_LSB 5
307 #define L1_L1_SANDBOX_START0_CTRL_BITS 0:0
308 #define L1_L1_SANDBOX_START0_CTRL_SET 0x00000001
309 #define L1_L1_SANDBOX_START0_CTRL_CLR 0xfffffffe
310 #define L1_L1_SANDBOX_START0_CTRL_MSB 0
311 #define L1_L1_SANDBOX_START0_CTRL_LSB 0
312 #define L1_L1_SANDBOX_END0 HW_REGISTER_RW( 0x7ee02804 )
313 #define L1_L1_SANDBOX_END0_MASK 0x3fffffe0
314 #define L1_L1_SANDBOX_END0_WIDTH 30
315 #define L1_L1_SANDBOX_END0_RESET 0x3fffffe0
316 #define L1_L1_SANDBOX_START1 HW_REGISTER_RW( 0x7ee02808 )
317 #define L1_L1_SANDBOX_START1_MASK 0x3fffffff
318 #define L1_L1_SANDBOX_START1_WIDTH 30
319 #define L1_L1_SANDBOX_START1_RESET 0000000000
320 #define L1_L1_SANDBOX_START1_START_ADDR_BITS 29:5
321 #define L1_L1_SANDBOX_START1_START_ADDR_SET 0x3fffffe0
322 #define L1_L1_SANDBOX_START1_START_ADDR_CLR 0xc000001f
323 #define L1_L1_SANDBOX_START1_START_ADDR_MSB 29
324 #define L1_L1_SANDBOX_START1_START_ADDR_LSB 5
325 #define L1_L1_SANDBOX_START1_CTRL_BITS 0:0
326 #define L1_L1_SANDBOX_START1_CTRL_SET 0x00000001
327 #define L1_L1_SANDBOX_START1_CTRL_CLR 0xfffffffe
328 #define L1_L1_SANDBOX_START1_CTRL_MSB 0
329 #define L1_L1_SANDBOX_START1_CTRL_LSB 0
330 #define L1_L1_SANDBOX_END1 HW_REGISTER_RW( 0x7ee0280c )
331 #define L1_L1_SANDBOX_END1_MASK 0x3fffffe0
332 #define L1_L1_SANDBOX_END1_WIDTH 30
333 #define L1_L1_SANDBOX_END1_RESET 0000000000
334 #define L1_L1_SANDBOX_START2 HW_REGISTER_RW( 0x7ee02810 )
335 #define L1_L1_SANDBOX_START2_MASK 0x3fffffff
336 #define L1_L1_SANDBOX_START2_WIDTH 30
337 #define L1_L1_SANDBOX_START2_RESET 0000000000
338 #define L1_L1_SANDBOX_START2_START_ADDR_BITS 29:5
339 #define L1_L1_SANDBOX_START2_START_ADDR_SET 0x3fffffe0
340 #define L1_L1_SANDBOX_START2_START_ADDR_CLR 0xc000001f
341 #define L1_L1_SANDBOX_START2_START_ADDR_MSB 29
342 #define L1_L1_SANDBOX_START2_START_ADDR_LSB 5
343 #define L1_L1_SANDBOX_START2_CTRL_BITS 0:0
344 #define L1_L1_SANDBOX_START2_CTRL_SET 0x00000001
345 #define L1_L1_SANDBOX_START2_CTRL_CLR 0xfffffffe
346 #define L1_L1_SANDBOX_START2_CTRL_MSB 0
347 #define L1_L1_SANDBOX_START2_CTRL_LSB 0
348 #define L1_L1_SANDBOX_END2 HW_REGISTER_RW( 0x7ee02814 )
349 #define L1_L1_SANDBOX_END2_MASK 0x3fffffe0
350 #define L1_L1_SANDBOX_END2_WIDTH 30
351 #define L1_L1_SANDBOX_END2_RESET 0000000000
352 #define L1_L1_SANDBOX_START3 HW_REGISTER_RW( 0x7ee02818 )
353 #define L1_L1_SANDBOX_START3_MASK 0x3fffffff
354 #define L1_L1_SANDBOX_START3_WIDTH 30
355 #define L1_L1_SANDBOX_START3_RESET 0000000000
356 #define L1_L1_SANDBOX_START3_START_ADDR_BITS 29:5
357 #define L1_L1_SANDBOX_START3_START_ADDR_SET 0x3fffffe0
358 #define L1_L1_SANDBOX_START3_START_ADDR_CLR 0xc000001f
359 #define L1_L1_SANDBOX_START3_START_ADDR_MSB 29
360 #define L1_L1_SANDBOX_START3_START_ADDR_LSB 5
361 #define L1_L1_SANDBOX_START3_CTRL_BITS 0:0
362 #define L1_L1_SANDBOX_START3_CTRL_SET 0x00000001
363 #define L1_L1_SANDBOX_START3_CTRL_CLR 0xfffffffe
364 #define L1_L1_SANDBOX_START3_CTRL_MSB 0
365 #define L1_L1_SANDBOX_START3_CTRL_LSB 0
366 #define L1_L1_SANDBOX_END3 HW_REGISTER_RW( 0x7ee0281c )
367 #define L1_L1_SANDBOX_END3_MASK 0x3fffffe0
368 #define L1_L1_SANDBOX_END3_WIDTH 30
369 #define L1_L1_SANDBOX_END3_RESET 0000000000
370 #define L1_L1_SANDBOX_START4 HW_REGISTER_RW( 0x7ee02820 )
371 #define L1_L1_SANDBOX_START4_MASK 0x3fffffff
372 #define L1_L1_SANDBOX_START4_WIDTH 30
373 #define L1_L1_SANDBOX_START4_RESET 0000000000
374 #define L1_L1_SANDBOX_START4_START_ADDR_BITS 29:5
375 #define L1_L1_SANDBOX_START4_START_ADDR_SET 0x3fffffe0
376 #define L1_L1_SANDBOX_START4_START_ADDR_CLR 0xc000001f
377 #define L1_L1_SANDBOX_START4_START_ADDR_MSB 29
378 #define L1_L1_SANDBOX_START4_START_ADDR_LSB 5
379 #define L1_L1_SANDBOX_START4_CTRL_BITS 0:0
380 #define L1_L1_SANDBOX_START4_CTRL_SET 0x00000001
381 #define L1_L1_SANDBOX_START4_CTRL_CLR 0xfffffffe
382 #define L1_L1_SANDBOX_START4_CTRL_MSB 0
383 #define L1_L1_SANDBOX_START4_CTRL_LSB 0
384 #define L1_L1_SANDBOX_END4 HW_REGISTER_RW( 0x7ee02824 )
385 #define L1_L1_SANDBOX_END4_MASK 0x3fffffe0
386 #define L1_L1_SANDBOX_END4_WIDTH 30
387 #define L1_L1_SANDBOX_END4_RESET 0000000000
388 #define L1_L1_SANDBOX_START5 HW_REGISTER_RW( 0x7ee02828 )
389 #define L1_L1_SANDBOX_START5_MASK 0x3fffffff
390 #define L1_L1_SANDBOX_START5_WIDTH 30
391 #define L1_L1_SANDBOX_START5_RESET 0000000000
392 #define L1_L1_SANDBOX_START5_START_ADDR_BITS 29:5
393 #define L1_L1_SANDBOX_START5_START_ADDR_SET 0x3fffffe0
394 #define L1_L1_SANDBOX_START5_START_ADDR_CLR 0xc000001f
395 #define L1_L1_SANDBOX_START5_START_ADDR_MSB 29
396 #define L1_L1_SANDBOX_START5_START_ADDR_LSB 5
397 #define L1_L1_SANDBOX_START5_CTRL_BITS 0:0
398 #define L1_L1_SANDBOX_START5_CTRL_SET 0x00000001
399 #define L1_L1_SANDBOX_START5_CTRL_CLR 0xfffffffe
400 #define L1_L1_SANDBOX_START5_CTRL_MSB 0
401 #define L1_L1_SANDBOX_START5_CTRL_LSB 0
402 #define L1_L1_SANDBOX_END5 HW_REGISTER_RW( 0x7ee0282c )
403 #define L1_L1_SANDBOX_END5_MASK 0x3fffffe0
404 #define L1_L1_SANDBOX_END5_WIDTH 30
405 #define L1_L1_SANDBOX_END5_RESET 0000000000
406 #define L1_L1_SANDBOX_START6 HW_REGISTER_RW( 0x7ee02830 )
407 #define L1_L1_SANDBOX_START6_MASK 0x3fffffff
408 #define L1_L1_SANDBOX_START6_WIDTH 30
409 #define L1_L1_SANDBOX_START6_RESET 0000000000
410 #define L1_L1_SANDBOX_START6_START_ADDR_BITS 29:5
411 #define L1_L1_SANDBOX_START6_START_ADDR_SET 0x3fffffe0
412 #define L1_L1_SANDBOX_START6_START_ADDR_CLR 0xc000001f
413 #define L1_L1_SANDBOX_START6_START_ADDR_MSB 29
414 #define L1_L1_SANDBOX_START6_START_ADDR_LSB 5
415 #define L1_L1_SANDBOX_START6_CTRL_BITS 0:0
416 #define L1_L1_SANDBOX_START6_CTRL_SET 0x00000001
417 #define L1_L1_SANDBOX_START6_CTRL_CLR 0xfffffffe
418 #define L1_L1_SANDBOX_START6_CTRL_MSB 0
419 #define L1_L1_SANDBOX_START6_CTRL_LSB 0
420 #define L1_L1_SANDBOX_END6 HW_REGISTER_RW( 0x7ee02834 )
421 #define L1_L1_SANDBOX_END6_MASK 0x3fffffe0
422 #define L1_L1_SANDBOX_END6_WIDTH 30
423 #define L1_L1_SANDBOX_END6_RESET 0000000000
424 #define L1_L1_SANDBOX_START7 HW_REGISTER_RW( 0x7ee02838 )
425 #define L1_L1_SANDBOX_START7_MASK 0x3fffffff
426 #define L1_L1_SANDBOX_START7_WIDTH 30
427 #define L1_L1_SANDBOX_START7_RESET 0000000000
428 #define L1_L1_SANDBOX_START7_START_ADDR_BITS 29:5
429 #define L1_L1_SANDBOX_START7_START_ADDR_SET 0x3fffffe0
430 #define L1_L1_SANDBOX_START7_START_ADDR_CLR 0xc000001f
431 #define L1_L1_SANDBOX_START7_START_ADDR_MSB 29
432 #define L1_L1_SANDBOX_START7_START_ADDR_LSB 5
433 #define L1_L1_SANDBOX_START7_CTRL_BITS 0:0
434 #define L1_L1_SANDBOX_START7_CTRL_SET 0x00000001
435 #define L1_L1_SANDBOX_START7_CTRL_CLR 0xfffffffe
436 #define L1_L1_SANDBOX_START7_CTRL_MSB 0
437 #define L1_L1_SANDBOX_START7_CTRL_LSB 0
438 #define L1_L1_SANDBOX_END7 HW_REGISTER_RW( 0x7ee0283c )
439 #define L1_L1_SANDBOX_END7_MASK 0x3fffffe0
440 #define L1_L1_SANDBOX_END7_WIDTH 30
441 #define L1_L1_SANDBOX_END7_RESET 0000000000
442 #define L1_L1_SANDBOX_PERI_BR HW_REGISTER_RW( 0x7ee02840 )
443 #define L1_L1_SANDBOX_PERI_BR_MASK 0x00001f1f
444 #define L1_L1_SANDBOX_PERI_BR_WIDTH 13
445 #define L1_L1_SANDBOX_PERI_BR_RESET 0x00000707
446 #define L1_L1_SANDBOX_PERI_BR_sandbox_peri_BITS 12:8
447 #define L1_L1_SANDBOX_PERI_BR_sandbox_peri_SET 0x00001f00
448 #define L1_L1_SANDBOX_PERI_BR_sandbox_peri_CLR 0xffffe0ff
449 #define L1_L1_SANDBOX_PERI_BR_sandbox_peri_MSB 12
450 #define L1_L1_SANDBOX_PERI_BR_sandbox_peri_LSB 8
451 #define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_BITS 4:0
452 #define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_SET 0x0000001f
453 #define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_CLR 0xffffffe0
454 #define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_MSB 4
455 #define L1_L1_SANDBOX_PERI_BR_sandbox_bootrom_LSB 0
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