add basic secure monitor code for armv7+, for some reason sdram security does not...
[rpi-open-firmware.git] / hardware.h
1 /*=============================================================================
2 Copyright (C) 2016-2017 Authors of rpi-open-firmware
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 Glue code for Broadcom's register definitions as well as certain registers
17 that are missing from the release. This is also used by ARM.
18
19 =============================================================================*/
20
21 #pragma once
22
23 #define VC4_PERIPH_BASE 0x7E000000
24 #define ARM_PERIPH_BASE 0x3F000000
25
26 #define VC4_TO_ARM_PERIPH(addr) ((addr - VC4_PERIPH_BASE) + ARM_PERIPH_BASE)
27
28 #define VC4_CPUID_BCM2709_PLUS 0x40
29
30 #ifdef __arm__
31 #define HW_REGISTER_RW(addr) (*(volatile unsigned int *)(VC4_TO_ARM_PERIPH(addr)))
32 #define HW_REGISTER_RO(addr) (*(const volatile unsigned int *)(VC4_TO_ARM_PERIPH(addr)))
33 #else
34 #define HW_REGISTER_RW(addr) (*(volatile unsigned int *)(addr))
35 #define HW_REGISTER_RO(addr) (*(const volatile unsigned int *)(addr))
36 #endif
37
38 #define mmio_read32(addr) HW_REGISTER_RW(addr)
39 #define mmio_write32(addr, value) (HW_REGISTER_RW(addr) = value)
40
41 #include "broadcom/hardware_vc4.h"
42
43 /*
44 * this is not included by hardware_vc4.h
45 */
46 #include "broadcom/bcm2708_chip/aux_io.h"
47 #include "broadcom/bcm2708_chip/testbus.h"
48
49 #define RAM_SIZE_1GB 0
50 #define RAM_SIZE_512MB 1
51 #define RAM_SIZE_256MB 2
52 #define RAM_SIZE_128MB 3
53 #define RAM_SIZE_UNKNOWN 4
54
55 /*
56 * LPDDR mode registers.
57 */
58 #define LPDDR2_MR_DEVICE_INFO 0
59 #define LPDDR2_MR_DEVICE_FEATURE_1 1
60 #define LPDDR2_MR_DEVICE_FEATURE_2 2
61 #define LPDDR2_MR_IO_CONFIG 3
62 #define LPDDR2_MR_TEMPERATURE 4
63 #define LPDDR2_MR_MANUFACTURER_ID 5
64 #define LPDDR2_MR_REV_1 6
65 #define LPDDR2_MR_REV_2 7
66 #define LPDDR2_MR_METRICS 8
67 #define LPDDR2_MR_CALIBRATION 10
68
69 #define CM_SRC_GND 0
70 #define CM_SRC_OSC 1
71 #define CM_SRC_TESTDEBUG0 2
72 #define CM_SRC_TESTDEBUG1 3
73 #define CM_SRC_PLLA_CORE 4
74 #define CM_SRC_PLLA_PER 4
75 #define CM_SRC_PLLC_CORE0 5
76 #define CM_SRC_PLLC_PER 5
77 #define CM_SRC_PLLC_CORE1 8
78 #define CM_SRC_PLLD_CORE 6
79 #define CM_SRC_PLLD_PER 6
80 #define CM_SRC_PLLH_AUX 7
81 #define CM_SRC_PLLC_CORE1 8
82 #define CM_SRC_PLLC_CORE2 9
83
84 typedef struct {
85 uint32_t sdram_size;
86 uint32_t vpu_cpuid;
87 uint32_t reserved[3];
88 } firmware_arm_data_t;
89
90 #ifdef __arm__
91 extern firmware_arm_data_t g_FirmwareData;
92 #endif
This page took 0.072175 seconds and 4 git commands to generate.