Working SDHOST/FatFS, boot partition mounts, some other minor fixes too.
[rpi-open-firmware.git] / hardware_vc4.h
1 /*=============================================================================
2 Copyright (c) 2006 Broadcom Europe Limited.
3 All rights reserved.
4
5 Project : VideoCore
6 Module : VideoCore hardware headers
7 File : $Id$
8
9 FILE DESCRIPTION
10 Public interface definition file for hardware specified registers.
11
12 =============================================================================*/
13
14 #ifndef _HARDWARE_VC4_H
15 #define _HARDWARE_VC4_H
16
17
18 /********************************************************
19 * VideoCore IV support
20 ********************************************************/
21
22 /*
23 VC4 Processor Control Register usage
24
25 p0 PRFPXCS - See "Scalar Floating Point Exception Control" in the VCIV Architecture Specification.
26 p1 PRCANARY - If stack protection is enabled, this register holds the canary.
27 p2-p9 Unassigned
28 p10 [B0] PRPOWCTL - Closely Coupled Power Control (VPU clock gating)
29 p11 [B0] PRTIMCTL - Closely Coupled Timer Control (core and sleep timers)
30 p12 [B0] PRCORTIM - Core Timer Result
31 p13 [B0] PRSLPTIM - Sleep Timer Result
32 p14 PROWCNT - Count of outstanding writes. See "Scalar Memory Engine" in the VC4AS.
33 p15 PRORCNT - Count of outstanding reads. See "Scalar Memory Engine" in the VC4AS.
34
35 p16-p31 are single-bit mutexes, shared between the two VPUs. See "P-Reg Semaphore" in the VC4AS.
36 p16 PRSPINL - Used by spinlock, a lightweight mutex.
37 p17 - Used by vcos_quickslow_mutex on ThreadX. (TODO: could we just use p16 instead?)
38 p18 Unassigned
39 p19 Unassigned
40 p20 Unassigned
41 p21 Unassigned
42 p22 Unassigned
43 p23 Unassigned
44 p24 Unassigned
45 p25 Unassigned
46 p26 Unassigned
47 p27 Unassigned
48 p28 Unassigned
49 p29 Unassigned
50 p30 Unassigned
51 p31 Unassigned
52 */
53
54
55 //#define FORCE_SECOND_CORE
56
57 #include "bcm2708_chip/arm_control.h"
58 #include "bcm2708_chip/apb_async_bridge_ctrl.h"
59 #include "bcm2708_chip/axi_dma0.h"
60 #ifdef __BCM2708A0__
61 #include "bcm2708_chip/axi_dma8.h"
62 #else
63 #include "bcm2708_chip/axi_dma15.h"
64 #endif
65 #ifdef __BCM2708A0__
66 #include "bcm2708_chip/cam0_a0.h"
67 #include "bcm2708_chip/cam1_a0.h"
68 #include "bcm2708_chip/ccp2tx_a0.h"
69 #else
70 #include "bcm2708_chip/cam0.h"
71 #include "bcm2708_chip/cam1.h"
72 #include "bcm2708_chip/ccp2tx.h"
73 #endif
74 #include "bcm2708_chip/clkman_image.h"
75 // #include "bcm2708_chip/clkman_audio.h"
76 // #include "bcm2708_chip/clkman_run.h"
77 #include "bcm2708_chip/cpg.h"
78 #ifdef __BCM2708A0__
79 #include "bcm2708_chip/cpr_clkman_a0.h"
80 #include "bcm2708_chip/cpr_powman_a0.h"
81 #include "bcm2708_chip/cpr_apb2wtap_a0.h"
82 #else
83 #include "bcm2708_chip/cpr_clkman.h"
84 #include "bcm2708_chip/cpr_powman.h"
85 #include "bcm2708_chip/cpr_apb2wtap.h"
86 #endif
87 #include "bcm2708_chip/dpi.h"
88 #include "bcm2708_chip/dsi.h"
89 #include "bcm2708_chip/dsi4.h"
90 #include "bcm2708_chip/gpio.h"
91 #include "bcm2708_chip/hdcp.h"
92 #include "bcm2708_chip/hdmi.h"
93 #include "bcm2708_chip/hdmicore.h"
94 #include "bcm2708_chip/hvs.h"
95 #include "bcm2708_chip/i2c0.h"
96 #include "bcm2708_chip/i2c1.h"
97 #include "bcm2708_chip/i2c2.h"
98 #include "bcm2708_chip/intctrl0.h"
99 #include "bcm2708_chip/intctrl1.h"
100 #include "bcm2708_chip/isp.h"
101 #include "bcm2708_chip/l2_cache_ctrl.h"
102 #include "bcm2708_chip/jpeg_top.h"
103 #include "bcm2708_chip/mphi.h"
104 #include "bcm2708_chip/multicore_sync.h"
105 #include "bcm2708_chip/nexus_uba.h"
106 #include "bcm2708_chip/otp.h"
107 #include "bcm2708_chip/pcm.h"
108 #include "bcm2708_chip/perfmon.h"
109 #include "bcm2708_chip/pixel_valve0.h"
110 #include "bcm2708_chip/pixel_valve1.h"
111 #include "bcm2708_chip/pixel_valve2.h"
112 #include "bcm2708_chip/pwm.h"
113 // #include "bcm2708_chip/reset_ctrl.h"
114 #include "bcm2708_chip/sdc_ctrl.h"
115 #include "bcm2708_chip/sdc_addr_front.h"
116 #include "bcm2708_chip/sdc_dq_front.h"
117 #include "bcm2708_chip/sdhost.h"
118 #if defined(__BCM2708A0__)
119 #include "bcm2708_chip/slimbus_a0.h"
120 #else
121 #include "bcm2708_chip/slimbus.h"
122 #endif
123 #include "bcm2708_chip/spi_master.h"
124 #include "bcm2708_chip/system_arbiter_ctrl.h"
125 #include "bcm2708_chip/vpu_arb_ctrl.h"
126 #include "bcm2708_chip/peri_image_arb_ctrl.h"
127 #ifdef __BCM2708A0__
128 #include "bcm2708_chip/tectl_a0.h"
129 #else
130 #include "bcm2708_chip/tectl.h"
131 #endif
132 #include "bcm2708_chip/timer.h"
133 #include "bcm2708_chip/tempsens.h"
134 #include "bcm2708_chip/txp.h"
135 #include "bcm2708_chip/uart.h"
136 #include "bcm2708_chip/v3d.h"
137 #include "bcm2708_chip/vec.h"
138 #include "bcm2708_chip/vpu_l1_cache_ctrl.h"
139 #include "bcm2708_chip/mphi.h"
140 #include "bcm2708_chip/usb.h"
141 #ifdef __BCM2708A0__
142 #include "bcm2708_chip/rng_a0.h"
143 #else
144 #include "bcm2708_chip/rng.h"
145 #endif
146
147 // Note: these macro evaluate argument twice - beware of side effects
148 #define ALIAS_NORMAL(x) ((void*)(((unsigned)(x)&~0xc0000000)|0x00000000)) // normal cached data (uses main 128K L2 cache)
149 #define ALIAS_L1_NONALLOCATING(x) ((void*)(((unsigned)(x)&~0xc0000000)|0x40000000)) // Doesn't allocate in L1 cache, will allocate in L2
150 #if defined(__BCM2708__)
151 // HW-2827 workaround
152 #define ALIAS_L1L2_NONALLOCATING(x) ALIAS_L1_NONALLOCATING(x)
153 #define ALIAS_L1L2_NONALLOCATING_READ(x) ((void*)(((unsigned)(x)&~0xc0000000)|0x80000000)) // cache coherent but non-allocating in L1 and L2
154 #else
155 #define ALIAS_L1L2_NONALLOCATING(x) ((void*)(((unsigned)(x)&~0xc0000000)|0x80000000)) // cache coherent but non-allocating in L1 and L2
156 #define ALIAS_L1L2_NONALLOCATING_READ(x) ALIAS_L1L2_NONALLOCATING(x)
157 #endif
158 #define ALIAS_COHERENT(x) ALIAS_L1L2_NONALLOCATING(x)
159 #define ALIAS_DIRECT(x) ((void*)(((unsigned)(x)&~0xc0000000)|0xc0000000)) // uncached
160 #define ALIAS_ANY_NONALLOCATING(x) (IS_ALIAS_DIRECT(x)?ALIAS_DIRECT(x):ALIAS_L1L2_NONALLOCATING(x)) // eliminate L1+L2 allocation from whatever alias is supplied
161 #define ALIAS_ANY_NONALLOCATING_READ(x) (IS_ALIAS_DIRECT(x)?ALIAS_DIRECT(x):ALIAS_L1L2_NONALLOCATING_READ(x))
162 #define ALIAS_ANY_L1_NONALLOCATING(x) (IS_ALIAS_DIRECT(x)?ALIAS_DIRECT(x):ALIAS_L1_NONALLOCATING(x)) // eliminate L1 allocation from whatever alias is supplied
163
164 #define IS_ALIAS_NORMAL(x) ((((unsigned)(x)>>30)&0x3)==0)
165 #define IS_ALIAS_L1_NONALLOCATING(x) ((((unsigned)(x)>>30)&0x3)==1)
166 #if defined(__BCM2708__)
167 // HW-2827 workaround
168 #define IS_ALIAS_L1L2_NONALLOCATING(x) IS_ALIAS_L1_NONALLOCATING(x)
169 #else
170 #define IS_ALIAS_L1L2_NONALLOCATING(x) ((((unsigned)(x)>>29)&0x7)==4) // make sure we are not considering peripherals
171 #endif
172 #define IS_ALIAS_DIRECT(x) ((((unsigned)(x)>>30)&0x3)==3)
173 #define IS_ALIAS_NONALLOCATING(x) (((unsigned)(x)>>29)>=3)
174 #define IS_ALIAS_PERIPHERAL(x) (((unsigned)(x)>>29)==0x3)
175 #define IS_ALIAS_COHERENT(x) IS_ALIAS_L1L2_NONALLOCATING(x)
176 #define IS_ALIAS_NOT_L1(p) (IS_ALIAS_L1_NONALLOCATING(p) || IS_ALIAS_NONALLOCATING(p))
177
178 //number of cores
179 #define VIDEOCORE_NUM_CORES 2
180
181 //The size of the stacked SDRAM
182 #define SDRAM_SIZE (1024 * 1024 * 128) //32MBytes
183 #define SDRAM_START_ADDRESS 0 //starts at 0 in our memory space
184
185 //The size of the L2 cache
186 #define L2CACHE_SIZE (1024 * 128) //starts at 0 in our memory space
187
188 //default interrupt vector table base address
189 #define INTERRUPT_VECTOR_BASE 0
190
191 //common interrupts
192 #define INTERRUPT_EXCEPTION_OFFSET 0
193 #define INTERRUPT_EXCEPTION_NUM 32
194
195 #define INTERRUPT_SOFTINT_OFFSET 32
196 #define INTERRUPT_SOFTINT_NUM 32
197
198 #define INTERRUPT_HARDINT_OFFSET 64
199 #define INTERRUPT_HARDINT_NUM 64
200
201 #define MAX_TIMER_NUM 4
202 #define MAX_EXCEPTION_NUM 8
203
204 // In A0 address order (ie RESET_CONTROLLER for B0 is later in the list)
205
206 #define BOOTROM_BASE_ADDRESS 0x60000000
207
208 #define L2CACHE_BASE L2_BASE
209 #define I0CACHE_BASE L1_BASE
210 #define D0CACHE_BASE (L1_BASE+0x100)
211
212 #define SDRAM_BASE_ADDRESS SD_BASE
213 #define DEBUG_MASTER_BASE NU_BASE
214 #define ARBITER_CTRL_BASE SYSAC_BASE
215 #define VPU0_THREAD_CTRL_BASE_ADDRESS 0x18011000
216
217
218 // vc_run APB Bridge - 0x1A00_0000 - 0x1A0F_FFFF
219 #define RUN_ARBITER_CTRL_BASE_ADDRESS 0x1A003000
220 #define V3D_BASE_ADDRESS 0x1A005000
221 #define VPU1_THREAD_CTRL_BASE_ADDRESS 0x1A008000
222 #define VPU1_UNIFORM_MEM_BASE_ADDRESS 0x1A00A000
223 #define V3D_MEM1_BASE_ADDRESS 0x1A00B000
224 #define V3D_MEM2_BASE_ADDRESS 0x1A00C000
225 #define VIDEOCODEC_BASE_ADDRESS 0x7f000000
226
227 // peri_audio APB Bridge - 0x7e20_0000 - 0x7E21_FFFF
228 #define UART_BASE_ADDRESS UART_BASE
229 #define I2C_BASE_0 I2C0_BASE
230 #define PIXELVALVE_0_BASE_ADDRESS PIXELVALVE0_BASE
231 #define PIXELVALVE_1_BASE_ADDRESS PIXELVALVE1_BASE
232 #define DSI_BASE DSI0_BASE
233 #define PWM_BASE_ADDRESS PWM_BASE
234 #define PERFMON_BASE_ADDRESS PRM_BASE
235 // #define SPI_BASE_ADDRESS SPI_BASE
236 // #define DSI1_BASE_ADDRESS DSI1_BASE
237 #define OTP_BASE_ADDRESS OTP_BASE
238 // #define CPG_BASE_ADDRESS CPG_BASE
239 // #define TEMP_SENS_BASE_ADDRESS TS_BASE
240
241
242 // cprman Audio APB bridge
243 #define POWERMAN_BASE_ADDRESS PM_BASE
244 #define RESET_CONTROLLER_BASE RS_BASE
245
246 #define JPEG_BASE JP_BASE
247 #define TRANSPOSER_BASE_ADDRESS TXP_BASE
248 //#define CCP2TX_BASE CCP2TX_BASE // definition in ccp2tx.h
249
250 // what to do with these ??
251 #define DISPC_BASE_ADDRESS 0x1C009000
252 #define CDP_BASE 0x1C00E000
253 #define ACIS_BASE_ADDRESS 0x1C004800
254 #define ADC_BASE_ADDRESS 0x1C00E000
255
256 // The AXI bus to the SMI - 0x1C20_0000 - 0x1C2F_FFFF
257 #define SMI_BASE 0x7E600000
258 #define SMI_BASE_DIRECT 0x7E601000
259
260 // perp run APB bridge
261
262 // peri_image APB Bridge - 0x7e80_0000 - 0x7E81_FFFF
263 // Camera - now have two Unicam modules at
264 // CAM 0 : 0x7e800000 (CAM0_BASE)
265 // CAM 1 : 0x7e801000 (CAM1_BASE)
266
267 #define I2C_BASE_1 I2C1_BASE
268 #define I2C_BASE_2 I2C2_BASE
269 #define PIXELVALVE_2_BASE_ADDRESS PIXELVALVE2_BASE
270 #define VEC_BASE_ADDRESS VEC_BASE
271
272 //interrupt definitions
273 #define INTERRUPT_HW_NUM (64)
274 #define INTERRUPT_HW_OFFSET (64)
275 #define INTERRUPT_SW_OFFSET (32)
276 #define INTERRUPT_SW_NUM (32)
277
278 #define INTERRUPT_TIMER0 (INTERRUPT_HW_OFFSET + 0 )
279 #define INTERRUPT_TIMER1 (INTERRUPT_HW_OFFSET + 1 )
280 #define INTERRUPT_TIMER2 (INTERRUPT_HW_OFFSET + 2 )
281 #define INTERRUPT_TIMER3 (INTERRUPT_HW_OFFSET + 3 )
282 #define INTERRUPT_CODEC0 (INTERRUPT_HW_OFFSET + 4 )
283 #define INTERRUPT_CODEC1 (INTERRUPT_HW_OFFSET + 5 )
284 #define INTERRUPT_CODEC2 (INTERRUPT_HW_OFFSET + 6 )
285 #define INTERRUPT_JPEG (INTERRUPT_HW_OFFSET + 7 )
286 #define INTERRUPT_ISP (INTERRUPT_HW_OFFSET + 8 )
287 #define INTERRUPT_USB (INTERRUPT_HW_OFFSET + 9 )
288 #define INTERRUPT_3D (INTERRUPT_HW_OFFSET + 10 )
289 #define INTERRUPT_TRANSPOSER (INTERRUPT_HW_OFFSET + 11 )
290 #define INTERRUPT_MULTICORESYNC0 (INTERRUPT_HW_OFFSET + 12 )
291 #define INTERRUPT_MULTICORESYNC1 (INTERRUPT_HW_OFFSET + 13 )
292 #define INTERRUPT_MULTICORESYNC2 (INTERRUPT_HW_OFFSET + 14 )
293 #define INTERRUPT_MULTICORESYNC3 (INTERRUPT_HW_OFFSET + 15 )
294 #define INTERRUPT_DMA0 (INTERRUPT_HW_OFFSET + 16 )
295 #define INTERRUPT_DMA1 (INTERRUPT_HW_OFFSET + 17 )
296 #define INTERRUPT_DMA2 (INTERRUPT_HW_OFFSET + 18 )
297 #define INTERRUPT_DMA3 (INTERRUPT_HW_OFFSET + 19 )
298 #define INTERRUPT_DMA4 (INTERRUPT_HW_OFFSET + 20 )
299 #define INTERRUPT_DMA5 (INTERRUPT_HW_OFFSET + 21 )
300 #define INTERRUPT_DMA6 (INTERRUPT_HW_OFFSET + 22 )
301 #define INTERRUPT_DMA7 (INTERRUPT_HW_OFFSET + 23 )
302 #define INTERRUPT_DMA8 (INTERRUPT_HW_OFFSET + 24 )
303 #if defined(__BCM2708A0__)
304 // A0 only has 9 dma interrupts
305 //#define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 )
306 //#define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 )
307 //#define INTERRUPT_DMA11 (INTERRUPT_HW_OFFSET + 27 )
308 //#define INTERRUPT_DMA12 (INTERRUPT_HW_OFFSET + 28 )
309 //#define INTERRUPT_DMA13 (INTERRUPT_HW_OFFSET + 29 )
310 //#define INTERRUPT_DMA14 (INTERRUPT_HW_OFFSET + 30 )
311 //#define INTERRUPT_DMA15 (INTERRUPT_HW_OFFSET + 31 )
312 #else
313 #define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 )
314 #define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 )
315 #define INTERRUPT_DMA11_12_13_14 (INTERRUPT_HW_OFFSET + 27 )
316 #define INTERRUPT_DMA_ALL (INTERRUPT_HW_OFFSET + 28 )
317 #define INTERRUPT_UART_SPI0_SPI1 (INTERRUPT_HW_OFFSET + 29 )
318 #define INTERRUPT_AUXIO INTERRUPT_UART_SPI0_SPI1
319 #define INTERRUPT_ARM (INTERRUPT_HW_OFFSET + 30 )
320 #define INTERRUPT_DMA_VPU (INTERRUPT_HW_OFFSET + 31 )
321 #endif
322 #define INTERRUPT_HOSTPORT (INTERRUPT_HW_OFFSET + 32 )
323 #define INTERRUPT_VIDEOSCALER (INTERRUPT_HW_OFFSET + 33 )
324 #define INTERRUPT_CCP2TX (INTERRUPT_HW_OFFSET + 34 )
325 #define INTERRUPT_SDC (INTERRUPT_HW_OFFSET + 35 )
326 #define INTERRUPT_DSI0 (INTERRUPT_HW_OFFSET + 36 )
327 #define INTERRUPT_AVE (INTERRUPT_HW_OFFSET + 37 )
328 #define INTERRUPT_CAM0 (INTERRUPT_HW_OFFSET + 38 )
329 # define INTERRUPT_CCP2 INTERRUPT_CAM0 // backward compatibility
330 #define INTERRUPT_CAM1 (INTERRUPT_HW_OFFSET + 39 )
331 # define INTERRUPT_CSI2 INTERRUPT_CAM1 // backward compatibility
332 #define INTERRUPT_HDMI0 (INTERRUPT_HW_OFFSET + 40 )
333 #define INTERRUPT_HDMI1 (INTERRUPT_HW_OFFSET + 41 )
334 #define INTERRUPT_PIXELVALVE1 (INTERRUPT_HW_OFFSET + 42 )
335 #define INTERRUPT_I2C_SLV (INTERRUPT_HW_OFFSET + 43 )
336 #define INTERRUPT_DSI1 (INTERRUPT_HW_OFFSET + 44 )
337 #define INTERRUPT_PWA0 (INTERRUPT_HW_OFFSET + 45 )
338 #define INTERRUPT_PWA1 (INTERRUPT_HW_OFFSET + 46 )
339 #define INTERRUPT_CPR (INTERRUPT_HW_OFFSET + 47 )
340 #define INTERRUPT_SMI (INTERRUPT_HW_OFFSET + 48 )
341 #define INTERRUPT_GPIO0 (INTERRUPT_HW_OFFSET + 49 )
342 #define INTERRUPT_GPIO1 (INTERRUPT_HW_OFFSET + 50 )
343 #define INTERRUPT_GPIO2 (INTERRUPT_HW_OFFSET + 51 )
344 #define INTERRUPT_GPIO3 (INTERRUPT_HW_OFFSET + 52 )
345 #define INTERRUPT_I2C (INTERRUPT_HW_OFFSET + 53 )
346 #define INTERRUPT_SPI (INTERRUPT_HW_OFFSET + 54 )
347 #define INTERRUPT_I2SPCM (INTERRUPT_HW_OFFSET + 55 )
348 #define INTERRUPT_SDIO (INTERRUPT_HW_OFFSET + 56 )
349 #define INTERRUPT_UART (INTERRUPT_HW_OFFSET + 57 )
350 #define INTERRUPT_SLIMBUS (INTERRUPT_HW_OFFSET + 58 )
351 #define INTERRUPT_VEC (INTERRUPT_HW_OFFSET + 59 )
352 #define INTERRUPT_CPG (INTERRUPT_HW_OFFSET + 60 )
353 #define INTERRUPT_RNG (INTERRUPT_HW_OFFSET + 61 )
354 #if defined(__BCM2708A0__)
355 // FIXME: see middleware/rpc/rpc.c
356 #define INTERRUPT_SPARE4 (INTERRUPT_HW_OFFSET + 62 )
357 #define INTERRUPT_SPARE5 (INTERRUPT_HW_OFFSET + 63 )
358 #else
359 #define INTERRUPT_ASDIO (INTERRUPT_HW_OFFSET + 62 )
360 #define INTERRUPT_AVSPMON (INTERRUPT_HW_OFFSET + 63 )
361 #endif
362 #define INTERRUPT_DUMMY (INTERRUPT_HW_OFFSET + 63 )
363
364 // aliases
365 #define INTERRUPT_HOSTINTERFACE INTERRUPT_HOSTPORT
366 #define INTERRUPT_SDCARDHOST INTERRUPT_SDIO
367
368
369 // temporary dummy register definitions to avoid compile errors
370 #define DUMMYREG HW_REGISTER_RW( 0x7C ) //software exception vector 15
371
372 /*---------------------------------------------------------------------------*/
373 /* TODO FIXME ETC... VCII Clock Manager defs */
374 #define CMPREC DUMMYREG
375 #define CMPRE1 DUMMYREG
376 #define CMPRE2 DUMMYREG
377 #define CMPRE3 DUMMYREG
378 #define CMPLLC DUMMYREG
379 #define CMPLL1 DUMMYREG
380 #define CMPLL2 DUMMYREG
381 #define CMPLL3 DUMMYREG
382 #define CMCORE DUMMYREG
383 #define CMCAM DUMMYREG
384 #define CMLCD DUMMYREG
385 #define CMACIS DUMMYREG
386 #define CMPCM DUMMYREG
387 #define CMUSB DUMMYREG
388 #define CMGEN DUMMYREG
389 #define CMMSP DUMMYREG
390 #define CMUART DUMMYREG
391 #define CMTIMER DUMMYREG
392 #define CMUARTF DUMMYREG
393 #define CMTIMERF DUMMYREG
394 #define CMNVT DUMMYREG
395
396 /*---------------------------------------------------------------------------*/
397 /* Nexus Controller */
398
399 #define NOWNT HW_REGISTER_RW(DEBUG_MASTER_BASE + 0x4)
400 #define NIOREQ HW_REGISTER_RW(DEBUG_MASTER_BASE + 0x0)
401
402 /*---------------------------------------------------------------------------*/
403 /* Reset Controller */
404
405 // #define RSTCS HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x0)
406 // #define RSTWD HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x4)
407 // #define RSTID HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x8)
408 // #define RSTFD HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0xc)
409 //
410 // #define RSC0ADDR HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x10)
411
412 /*---------------------------------------------------------------------------*/
413 /* Scaler hardware registers */
414
415 #define SCALER_BASE_ADDRESS SCALER_BASE
416 #define SCALER_INPUT_CONTROL HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x00 )
417 #define SCALER_IRQ_STATUS HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x04 )
418 #define SCALER_ID HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x08 )
419 #define SCALER_ALT_CONTROL HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x0C )
420 #define SCALER_PROFILE HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x10 )
421 #define SCALER_DITHER HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x14 )
422 //#define SCALER_DISPEOLN HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x18 )
423
424 #define SCALER_DISP_LIST_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x20 )
425 #define SCALER_DISP_LIST_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x24 )
426 #define SCALER_DISP_LIST_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x28 )
427 #define SCALER_DISP_LIST_STATUS HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x2C )
428
429 #define SCALER_DISPCTL_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x40 )
430 #define SCALER_DISPBKGND_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x44 )
431 #define SCALER_DISPSTAT_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x48 )
432
433 #define SCALER_DISPCTL_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x50 )
434 #define SCALER_DISPBKGND_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x54 )
435 #define SCALER_DISPSTAT_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x58 )
436 #define SCALER_DISPBASE_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x5C )
437
438 #define SCALER_DISPCTL_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x60 )
439 #define SCALER_DISPBKGND_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x64 )
440 #define SCALER_DISPSTAT_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x68 )
441 #define SCALER_DISPBASE_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x6C )
442
443 #define SCALER_GAM_ADDRESS HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x78 )
444 #define SCALER_GAM_DATA HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xE0 )
445
446 //#define SCALER_DISPSLAVE0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xC0 )
447 //#define SCALER_DISPSLAVE1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xC8 )
448 //#define SCALER_DISPSLAVE2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xD0 )
449
450 //the start location of the scalers context memory
451 #define SCALER_CONTEXT_MEMORY_START (SCALER_BASE_ADDRESS + 0x2000)
452
453 #define SCALER_CONTEXT_MEM_SIZE ( 1024 * 16 ) //16k
454
455 //the size of the line buffer memory
456 #define SCALER_LINE_BUFFER_MEM_SIZE (94 * 1024)
457
458 //The size of the COB buffer (the output fifo) in pixels
459 #define SCALER_COB_FIFO_SIZE (0x4000) //16Kpix == 48kBytes
460
461 /*---------------------------------------------------------------------------*/
462 /* PWM */
463 #define PWMCTL HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x00 )
464 #define PWMSTA HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x04 )
465 #define PWMDMAC HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x08 )
466 #define PWMRNG1 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x10 )
467 #define PWMDAT1 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x14 )
468 #define PWMFIF1 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x18 )
469 #define PWMRNG2 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x20 )
470 #define PWMDAT2 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x24 )
471 #define PWMRNG3 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x30 )
472 #define PWMDAT3 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x34 )
473 #define PWMRNG4 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x40 )
474 #define PWMDAT4 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x44 )
475
476 #define PWMRNG(n) HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x10*n ) // n=1,2,3,4
477 #define PWMDAT(n) HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x10*n + 4 )
478
479 #define PWMCTL_PWEN1 0
480 #define PWMCTL_MODE1 1
481 #define PWMCTL_RPTL1 2
482 #define PWMCTL_SBIT1 3
483 #define PWMCTL_POLA1 4
484 #define PWMCTL_USEF1 5
485 #define PWMCTL_CLRF1 6
486 #define PWMCTL_MSEN1 7
487 #define PWMCTL_PWEN2 8
488 #define PWMCTL_MODE2 9
489 #define PWMCTL_RPTL2 10
490 #define PWMCTL_SBIT2 11
491 #define PWMCTL_POLA2 12
492 #define PWMCTL_USEF2 13
493 #define PWMCTL_MSEN2 15
494 #define PWMCTL_PWEN3 16
495 #define PWMCTL_MODE3 17
496 #define PWMCTL_RPTL3 18
497 #define PWMCTL_SBIT3 19
498 #define PWMCTL_POLA3 20
499 #define PWMCTL_USEF3 21
500 #define PWMCTL_MSEN3 23
501 #define PWMCTL_PWEN4 24
502 #define PWMCTL_MODE4 25
503 #define PWMCTL_RPTL4 26
504 #define PWMCTL_SBIT4 27
505 #define PWMCTL_POLA4 28
506 #define PWMCTL_USEF4 29
507 #define PWMCTL_MSEN4 31
508 #define PWMCTL_PWEN(n) (((n-1)<<3)+0) // n=1,2,3,4
509 #define PWMCTL_MODE(n) (((n-1)<<3)+1)
510 #define PWMCTL_RPTL(n) (((n-1)<<3)+2)
511 #define PWMCTL_SBIT(n) (((n-1)<<3)+3)
512 #define PWMCTL_POLA(n) (((n-1)<<3)+4)
513 #define PWMCTL_USEF(n) (((n-1)<<3)+5)
514 #define PWMCTL_MSEN(n) (((n-1)<<3)+7)
515
516 #define PWMSTA_FULL1 0
517 #define PWMSTA_EMPT1 1
518 #define PWMSTA_WERR1 2
519 #define PWMSTA_RERR1 3
520 #define PWMSTA_GAPO1 4
521 #define PWMSTA_GAPO2 5
522 #define PWMSTA_GAPO3 6
523 #define PWMSTA_GAPO4 7
524 #define PWMSTA_BERR 8
525 #define PWMSTA_STA1 9
526 #define PWMSTA_STA2 10
527 #define PWMSTA_STA3 11
528 #define PWMSTA_STA4 12
529
530 #define PWMDMAC_DREQ_LEN 8
531 #define PWMDMAC_DREQ 0
532 #define PWMDMAC_PANIC_LEN 8
533 #define PWMDMAC_PANIC 8
534 #define PWMDMAC_ENAB 31
535
536 /*---------------------------------------------------------------------------*/
537 /* Transposer */
538
539 #define TRANSPOSER_DST_PTR HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x00 )
540 #define TRANSPOSER_DST_PITCH HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x04 )
541 #define TRANSPOSER_DIMENSIONS HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x08 )
542 #define TRANSPOSER_CONTROL HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x0C )
543 #define TRANSPOSER_PROGRESS HW_REGISTER_RO( TRANSPOSER_BASE_ADDRESS + 0x10 )
544
545 /*---------------------------------------------------------------------------*/
546 /* Video Codec */
547
548 #define VCSIGNAL0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408b4)
549 #define VCINTMASK0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408b8)
550 #define VCSIGNAL1 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408bc)
551 #define VCINTMASK1 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408c0)
552 #ifndef VCODEC_VERSION
553 // Set default to old A0 version
554 #define VCODEC_VERSION 821
555 #endif
556
557 #if (VCODEC_VERSION>=800)
558
559 #define VCE_BASE 0x7f100000
560 #define VCE_DATA_MEM_OFFSET 0
561 #define VCE_DATA_MEM_SIZE 0x2000
562 #define VCE_PROGRAM_MEM_OFFSET 0x10000
563 #define VCE_PROGRAM_MEM_SIZE 0x4000
564 #define VCE_REGISTERS_OFFSET 0x20000
565 #define VCE_REGISTERS_COUNT 63
566 #define VCE_STATUS_OFFSET 0x40000
567 #define VCE_STATUS_BUSYBITS_MASK 0xffff
568 #define VCE_STATUS_REASON_POS 16
569 #define VCE_STATUS_REASON_MASK 0x1f
570 #define VCE_BUSY_BKPT 0x00
571 #define VCE_BUSY_USER 0x01 // up to 0x07 inclusive
572 #define VCE_BUSY_DMAIN 0x08
573 #define VCE_BUSY_DMAOUT 0x09
574 #define VCE_BUSY_MEMSYNC 0x0a
575 #define VCE_BUSY_SLEEP 0x0b
576 #define VCE_REASON_STOPPED 0x10
577 #define VCE_REASON_RUNNING 0x11
578 #define VCE_REASON_RESET 0x12
579 #define VCE_REASON_SINGLE 0x13
580 #define VCE_STATUS_RUNNING_POS 24
581 #define VCE_STATUS_NANOFLAG_POS 25
582 #define VCE_STATUS_INTERRUPT_POS 31
583 #define VCE_VERSION_OFFSET 0x40004
584 #define VCE_PC_PF0_OFFSET 0x40008
585 #define VCE_PC_IF0_OFFSET 0x4000c
586 #define VCE_PC_RD0_OFFSET 0x40010
587 #define VCE_PC_EX0_OFFSET 0x40014
588 #define VCE_CONTROL_OFFSET 0x40020
589 #define VCE_CONTROL_CLEAR_RUN 0
590 #define VCE_CONTROL_SET_RUN 1
591 #define VCE_CONTROL_SINGLE_STEP 3
592 #define VCE_BAD_ADDR_OFFSET 0x40030
593 #define VCE_SEMA_CLEAR_OFFSET 0x40024
594 #define VCE_SEMA_SET_OFFSET 0x40028
595 #define VCE_SEMA_COUNT 8
596 #define VCE_SIM_DEBUG_OPTIONS_OFFSET 0x40100
597
598 #define VCE_DATA_MEM_BASE HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x100000)
599 #define VCE_PROGRAM_MEM_BASE HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110000)
600 #define VCE_REGISTERS_BASE HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x120000)
601 #define VCE_STATUS HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140000)
602 #define VCE_VERSION HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140004)
603 #define VCE_PC_PF0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140008)
604 #define VCE_PC_IF0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x14000C)
605 #define VCE_PC_RD0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140010)
606 #define VCE_PC_EX0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140014)
607 #define VCE_CONTROL HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140020)
608 #define VCE_SEMA_CLEAR HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140024)
609 #define VCE_SEMA_SET HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140028)
610 #define VCE_BAD_ADDR HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140030)
611 #define VCE_SIM_DEBUG_OPTIONS HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140100)
612
613 #else
614 #define PP_PC HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110000)
615 #define PP_CNTL HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110004)
616 #define PP_ACC HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110008)
617 #endif
618
619 /*---------------------------------------------------------------------------*/
620 /* DSI */
621
622 // Define some macros for compatability with old VCIII code which does not
623 // know about more than one dsi peripheral. Just direct it to DSI0...
624 #define DSI_CTRL HW_REGISTER_RW( DSI_BASE + 0x00 )
625 #define DSI_CMD_PKTC HW_REGISTER_RW( DSI_BASE + 0x04 )
626 #define DSI_CMD_PKTH HW_REGISTER_RW( DSI_BASE + 0x08 )
627 #define DSI_RX1_PKTH HW_REGISTER_RW( DSI_BASE + 0x0C )
628 #define DSI_RX2_PKTH HW_REGISTER_RW( DSI_BASE + 0x10 )
629 #define DSI_CMD_DATA_FIFO HW_REGISTER_RW( DSI_BASE + 0x14 )
630 #define DSI_DISP0_CTRL HW_REGISTER_RW( DSI_BASE + 0x18 )
631 #define DSI_DISP1_CTRL HW_REGISTER_RW( DSI_BASE + 0x1C )
632 #define DSI_PIX_FIFO HW_REGISTER_RW( DSI_BASE + 0x20 )
633 #define DSI_INT_STATUS HW_REGISTER_RW( DSI_BASE + 0x24 )
634 #define DSI_INT_ENABLE HW_REGISTER_RW( DSI_BASE + 0x28 )
635 #define DSI_STAT HW_REGISTER_RW( DSI_BASE + 0x2C )
636 #define DSI_HSTX_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x30 )
637 #define DSI_LPRX_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x34 )
638 #define DSI_TA_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x38 )
639 #define DSI_PR_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x3C )
640 #define DSI_PHY_CONTROL HW_REGISTER_RW( DSI_BASE + 0x40 )
641 // HSCLKZERO, HSCLKPRE, HSCLKPREP
642 #define DSI_HS_CLT0 HW_REGISTER_RW( DSI_BASE + 0x44 )
643 // HSCLKTRAIL, HSCLKPOST
644 #define DSI_HS_CLT1 HW_REGISTER_RW( DSI_BASE + 0x48 )
645 // HSWAKEUP
646 #define DSI_HS_CLT2 HW_REGISTER_RW( DSI_BASE + 0x4C )
647 // HS EXIT, ZERO, PRE
648 #define DSI_HS_DLT3 HW_REGISTER_RW( DSI_BASE + 0x50 )
649 // HS TRAIL LPX
650 #define DSI_HS_DLT4 HW_REGISTER_RW( DSI_BASE + 0x54 )
651 // HS INIT
652 #define DSI_HS_DLT5 HW_REGISTER_RW( DSI_BASE + 0x58 )
653 // lp GET SURE GO LPX
654 #define DSI_LP_DLT6 HW_REGISTER_RW( DSI_BASE + 0x5C )
655 // LP WAKEUP
656 #define DSI_LP_DLT7 HW_REGISTER_RW( DSI_BASE + 0x60 )
657 #define DSI_AFEC0 HW_REGISTER_RW( DSI_BASE + 0x64 )
658 #define DSI_AFEC1 HW_REGISTER_RW( DSI_BASE + 0x68 )
659 #define DSI_TST_SEL HW_REGISTER_RW( DSI_BASE + 0x6C )
660 #define DSI_TST_MON HW_REGISTER_RW( DSI_BASE + 0x70 )
661
662 /*---------------------------------------------------------------------------*/
663 /* CDP */
664
665 #define CDPC HW_REGISTER_RW( CDP_BASE + 0x00 )
666 #define CDP_PHYC HW_REGISTER_RW( CDP_BASE + 0x04 )
667 #define CDP_PHYTSTDAT HW_REGISTER_RW( CDP_BASE + 0x08 )
668 #define CDP_DEBUG0 HW_REGISTER_RW( CDP_BASE + 0x0C )
669 #define CDP_DEBUG1 HW_REGISTER_RW( CDP_BASE + 0x10 )
670
671 /*---------------------------------------------------------------------------*/
672 /* BootROM Peripheral */
673
674 #define BOOTROM_ROM_START ( BOOTROM_BASE_ADDRESS + 0x0 ) //Start of the ROM
675 #define BOOTROM_ROM_LENGTH ( 1024 * 32 ) // Length of the Boot ROM
676
677 #define BOOTROM_RAM_START ( BOOTROM_BASE_ADDRESS + 0x8000 ) //Start of the RAM
678 #define BOOTROM_RAM_LENGTH ( 1024 * 2 ) // Length of the Boot RAM
679
680 #define BOOTROM_BRCTL HW_REGISTER_RW( BOOTROM_BASE_ADDRESS + 0xC000 )
681
682 /*---------------------------------------------------------------------------*/
683 /* Unicam Peripheral */
684 #define UNICAM_REG( x, d ) HW_REGISTER_RW( (((x) == 0) ? CAM0_BASE : CAM1_BASE) + d )
685
686 #if defined(__BCM2708A0__)
687 #define UNICAM_CTRL( x ) UNICAM_REG( x, 0x000 )
688 #define UNICAM_STA( x ) UNICAM_REG( x, 0x004 )
689 #define UNICAM_ANA( x ) UNICAM_REG( x, 0x008 )
690 #define UNICAM_PRI( x ) UNICAM_REG( x, 0x00c )
691 #define UNICAM_CLK( x ) UNICAM_REG( x, 0x010 )
692 #define UNICAM_DAT0( x ) UNICAM_REG( x, 0x014 )
693 #define UNICAM_DAT1( x ) UNICAM_REG( x, 0x018 )
694 #define UNICAM_DAT2( x ) UNICAM_REG( x, 0x01c )
695 #define UNICAM_DAT3( x ) UNICAM_REG( x, 0x020 )
696 #define UNICAM_CMP0( x ) UNICAM_REG( x, 0x024 )
697 #define UNICAM_CMP1( x ) UNICAM_REG( x, 0x028 )
698 #define UNICAM_CAP0( x ) UNICAM_REG( x, 0x02c )
699 #define UNICAM_CAP1( x ) UNICAM_REG( x, 0x030 )
700 #define UNICAM_DBG0( x ) UNICAM_REG( x, 0x0f0 )
701 #define UNICAM_DBG1( x ) UNICAM_REG( x, 0x0f4 )
702 #define UNICAM_DBG2( x ) UNICAM_REG( x, 0x0f8 )
703 #define UNICAM_ICTL( x ) UNICAM_REG( x, 0x100 )
704 #define UNICAM_ISTA( x ) UNICAM_REG( x, 0x104 )
705 #define UNICAM_IDI( x ) UNICAM_REG( x, 0x108 )
706 #define UNICAM_IPIPE( x ) UNICAM_REG( x, 0x10c )
707 #define UNICAM_IBSA( x ) UNICAM_REG( x, 0x110 )
708 #define UNICAM_IBEA( x ) UNICAM_REG( x, 0x114 )
709 #define UNICAM_IBLS( x ) UNICAM_REG( x, 0x118 )
710 #define UNICAM_IBWP( x ) UNICAM_REG( x, 0x11c )
711 #define UNICAM_IHWIN( x ) UNICAM_REG( x, 0x120 )
712 #define UNICAM_IHSTA( x ) UNICAM_REG( x, 0x124 )
713 #define UNICAM_IVWIN( x ) UNICAM_REG( x, 0x128 )
714 #define UNICAM_IVSTA( x ) UNICAM_REG( x, 0x12c )
715 #define UNICAM_DCS( x ) UNICAM_REG( x, 0x200 )
716 #define UNICAM_DBSA( x ) UNICAM_REG( x, 0x204 )
717 #define UNICAM_DBEA( x ) UNICAM_REG( x, 0x208 )
718 #define UNICAM_DBWP( x ) UNICAM_REG( x, 0x20c )
719 #else
720 #define UNICAM_CTRL( x ) UNICAM_REG( x, 0x000 )
721 #define UNICAM_STA( x ) UNICAM_REG( x, 0x004 )
722 #define UNICAM_ANA( x ) UNICAM_REG( x, 0x008 )
723 #define UNICAM_PRI( x ) UNICAM_REG( x, 0x00c )
724 #define UNICAM_CLK( x ) UNICAM_REG( x, 0x010 )
725 #define UNICAM_CLT( x ) UNICAM_REG( x, 0x014 )
726 #define UNICAM_DAT0( x ) UNICAM_REG( x, 0x018 )
727 #define UNICAM_DAT1( x ) UNICAM_REG( x, 0x01c )
728 #define UNICAM_DAT2( x ) UNICAM_REG( x, 0x020 )
729 #define UNICAM_DAT3( x ) UNICAM_REG( x, 0x024 )
730 #define UNICAM_DLT( x ) UNICAM_REG( x, 0x028 )
731 #define UNICAM_CMP0( x ) UNICAM_REG( x, 0x02c )
732 #define UNICAM_CMP1( x ) UNICAM_REG( x, 0x030 )
733 #define UNICAM_CAP0( x ) UNICAM_REG( x, 0x034 )
734 #define UNICAM_CAP1( x ) UNICAM_REG( x, 0x038 )
735 #define UNICAM_ICTL( x ) UNICAM_REG( x, 0x100 )
736 #define UNICAM_ISTA( x ) UNICAM_REG( x, 0x104 )
737 #define UNICAM_IDI0( x ) UNICAM_REG( x, 0x108 )
738 #define UNICAM_IPIPE( x ) UNICAM_REG( x, 0x10c )
739 #define UNICAM_IBSA0( x ) UNICAM_REG( x, 0x110 )
740 #define UNICAM_IBEA0( x ) UNICAM_REG( x, 0x114 )
741 #define UNICAM_IBLS( x ) UNICAM_REG( x, 0x118 )
742 #define UNICAM_IBWP( x ) UNICAM_REG( x, 0x11c )
743 #define UNICAM_IHWIN( x ) UNICAM_REG( x, 0x120 )
744 #define UNICAM_IHSTA( x ) UNICAM_REG( x, 0x124 )
745 #define UNICAM_IVWIN( x ) UNICAM_REG( x, 0x128 )
746 #define UNICAM_IVSTA( x ) UNICAM_REG( x, 0x12c )
747 #define UNICAM_ICC( x ) UNICAM_REG( x, 0x130 )
748 #define UNICAM_ICS( x ) UNICAM_REG( x, 0x134 )
749 #define UNICAM_IDC( x ) UNICAM_REG( x, 0x138 )
750 #define UNICAM_IDPO( x ) UNICAM_REG( x, 0x13c )
751 #define UNICAM_IDCA( x ) UNICAM_REG( x, 0x140 )
752 #define UNICAM_IDCD( x ) UNICAM_REG( x, 0x144 )
753 #define UNICAM_IDS( x ) UNICAM_REG( x, 0x148 )
754 #define UNICAM_DCS( x ) UNICAM_REG( x, 0x200 )
755 #define UNICAM_DBSA0( x ) UNICAM_REG( x, 0x204 )
756 #define UNICAM_DBEA0( x ) UNICAM_REG( x, 0x208 )
757 #define UNICAM_DBWP( x ) UNICAM_REG( x, 0x20c )
758 #define UNICAM_DBCTL( x ) UNICAM_REG( x, 0x300 )
759 #define UNICAM_IBSA1( x ) UNICAM_REG( x, 0x304 )
760 #define UNICAM_IBEA1( x ) UNICAM_REG( x, 0x308 )
761 #define UNICAM_IDI1( x ) UNICAM_REG( x, 0x30c )
762 #define UNICAM_DBSA1( x ) UNICAM_REG( x, 0x310 )
763 #define UNICAM_DBEA1( x ) UNICAM_REG( x, 0x314 )
764 #define UNICAM_MISC( x ) UNICAM_REG( x, 0x400 )
765 #endif
766
767 /*---------------------------------------------------------------------------*/
768 /* CCP2TX Peripheral - now from ccp2tx[_a0].h */
769 #define CCP2TC CCP2TX_TC
770 #define CCP2TS CCP2TX_TS
771 #ifndef __BCM2708A0__
772 #define CCP2TAC CCP2TX_TAC
773 #endif
774 #define CCP2TPC CCP2TX_TPC
775 #define CCP2TSC CCP2TX_TSC
776 #define CCP2TIC CCP2TX_TIC
777 #define CCP2TTC CCP2TX_TTC
778 #define CCP2TBA CCP2TX_TBA
779 #define CCP2TDL CCP2TX_TDL
780 #define CCP2TD CCP2TX_TD
781 #ifndef __BCM2708A0__
782 #define CCP2TSPARE CCP2TX_TSPARE
783 #endif
784
785 /*---------------------------------------------------------------------------*/
786 /* VEC Peripheral */
787
788 #define WSE_RESET VEC_WSE_RESET
789 #define WSE_CONTROL VEC_WSE_CONTROL
790 #define WSE_WSS_DATA VEC_WSE_WSS_DATA
791 #define WSE_VPS_DATA_1 VEC_WSE_VPS_DATA_1
792 #define WSE_VPS_CONTROL VEC_WSE_VPS_CONTROL
793
794 #define CGMSAE_RESET VEC_CGMSAE_RESET
795 #define CGMSAE_TOP_CONTROL VEC_CGMSAE_TOP_CONTROL
796 #define CGMSAE_BOT_CONTROL VEC_CGMSAE_BOT_CONTROL
797 #define CGMSAE_TOP_FORMAT VEC_CGMSAE_TOP_FORMAT
798 #define CGMSAE_BOT_FORMAT VEC_CGMSAE_BOT_FORMAT
799 #define CGMSAE_TOP_DATA VEC_CGMSAE_TOP_DATA
800 #define CGMSAE_BOT_DATA VEC_CGMSAE_BOT_DATA
801 #define CGMSAE_REVID VEC_CGMSAE_REVID
802
803 /*---------------------------------------------------------------------------*/
804 /* System Timer */
805
806 // The old register names are used all over the place, so we probably need to
807 // keep these for now.
808 // These also appear in systimer.h; ideally, any modules which access these
809 // registers directly should #include that header file.
810 #if 1 // TODO: remove these one day.
811 #define STCS_0 ST_CS
812 #define STC_0 ST_CLO
813 #define STCLO_0 ST_CLO
814 #define STCHI_0 ST_CHI
815 #define STC0_0 ST_C0
816 #define STC1_0 ST_C1
817 #define STC2_0 ST_C2
818 #define STC3_0 ST_C3
819
820 #define STCS ST_CS
821 #define STC ST_CLO
822 #define STCLO ST_CLO
823 #define STCHI ST_CHI
824 #define STC0 ST_C0
825 #define STC1 ST_C1
826 #define STC2 ST_C2
827 #define STC3 ST_C3
828 #endif
829 /*---------------------------------------------------------------------------*/
830 /* Crypto/ID module */
831 #define IDCLVWMCU HW_REGISTER_RW(0x10002000)
832 #define IDCMDIDU HW_REGISTER_RW(0x10002004)
833 #define IDCKEYHU HW_REGISTER_RW(0x10002008)
834 #define IDCKEYLU HW_REGISTER_RW(0x1000200C)
835 #define IDCCMD HW_REGISTER_RW(0x10002010)
836 #define IDCCFG HW_REGISTER_RW(0x10002014)
837 #define IDCKSEL HW_REGISTER_RW(0x10002018)
838 #define IDCLVWMC HW_REGISTER_RW(0x10002020)
839 #define IDCMDID HW_REGISTER_RW(0x10002024)
840
841 /*---------------------------------------------------------------------------*/
842 /* Single 16550 UART */
843 #define URBR HW_REGISTER_RO(UART_BASE + 0x00)
844 #define UTHR HW_REGISTER_RW(UART_BASE + 0x00)
845 #define UIER HW_REGISTER_RW(UART_BASE + 0x04)
846 #define UIIR HW_REGISTER_RO(UART_BASE + 0x08)
847 #define UFCR HW_REGISTER_RW(UART_BASE + 0x08)
848 #define ULCR HW_REGISTER_RW(UART_BASE + 0x0C)
849 #define UMCR HW_REGISTER_RW(UART_BASE + 0x10)
850 #define ULSR HW_REGISTER_RW(UART_BASE + 0x14)
851 #define UMSR HW_REGISTER_RW(UART_BASE + 0x18)
852 #define USCR HW_REGISTER_RW(UART_BASE + 0x1C)
853 #define UDLL HW_REGISTER_RW(UART_BASE + 0x00)
854 #define UDLM HW_REGISTER_RW(UART_BASE + 0x04)
855 #define UEN HW_REGISTER_RW(UART_BASE + 0x20)
856
857 #define VIDEOCORE_NUM_UART_PORTS 1
858
859 /*---------------------------------------------------------------------------*/
860 /* ADC */
861 #define ADCCS HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x00)
862 #define ADCR0 HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x04)
863 #define ADCR1 HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x08)
864
865 /*---------------------------------------------------------------------------*/
866 /* General Purpose I/O */
867
868 //Max num of pins in the chip
869 #define GPIO_MAX_PINS 54
870
871 /*---------------------------------------------------------------------------*/
872 /* JPEG block */
873 #define JCTRL HW_REGISTER_RW(JPEG_BASE + 0)
874 #define JICST HW_REGISTER_RW(JPEG_BASE + 0x4)
875 #define JMCTRL HW_REGISTER_RW(JPEG_BASE + 0x8)
876 #define JDCCTRL HW_REGISTER_RW(JPEG_BASE + 0x0C)
877 #define JCBA HW_REGISTER_RW(JPEG_BASE + 0x10)
878 #define JNCB HW_REGISTER_RW(JPEG_BASE + 0x14)
879 #define JSDA HW_REGISTER_RW(JPEG_BASE + 0x18)
880 #define JNSB HW_REGISTER_RW(JPEG_BASE + 0x1C)
881 #define JSBO HW_REGISTER_RW(JPEG_BASE + 0x20)
882 #define JMOP HW_REGISTER_RW(JPEG_BASE + 0x24)
883 #define JHADDR HW_REGISTER_RW(JPEG_BASE + 0x28)
884 #define JHWDATA HW_REGISTER_RW(JPEG_BASE + 0x2C)
885 #define JMADDR HW_REGISTER_RW(JPEG_BASE + 0x30)
886 #define JMWDATA HW_REGISTER_RW(JPEG_BASE + 0x34)
887 #define JOADDR HW_REGISTER_RW(JPEG_BASE + 0x38)
888 #define JOWDATA HW_REGISTER_RW(JPEG_BASE + 0x3C)
889 #define JQADDR HW_REGISTER_RW(JPEG_BASE + 0x40)
890 #define JQWDATA HW_REGISTER_RW(JPEG_BASE + 0x44)
891 #define JQCTRL HW_REGISTER_RW(JPEG_BASE + 0x48)
892 #define JC0BA HW_REGISTER_RW(JPEG_BASE + 0x4C)
893 #define JC1BA HW_REGISTER_RW(JPEG_BASE + 0x50)
894 #define JC2BA HW_REGISTER_RW(JPEG_BASE + 0x54)
895 #define JC0S HW_REGISTER_RW(JPEG_BASE + 0x58)
896 #define JC1S HW_REGISTER_RW(JPEG_BASE + 0x5C)
897 #define JC2S HW_REGISTER_RW(JPEG_BASE + 0x60)
898 #define JC0W HW_REGISTER_RW(JPEG_BASE + 0x64)
899 #define JC1W HW_REGISTER_RW(JPEG_BASE + 0x68)
900 #define JC2W HW_REGISTER_RW(JPEG_BASE + 0x6C)
901
902 #define JCTRL_START (1 << 7)
903 #define JCTRL_DCTEN (1 << 4)
904 #define JCTRL_RESET (1 << 3)
905 #define JCTRL_FLUSH (1 << 2)
906 #define JCTRL_STUFF (1 << 1)
907 #define JCTRL_MODE (1 << 0)
908
909 #define JHADDR_TABLEF (1 << 31)
910
911 #define JICST_ERR (1 << 19)
912 #define JICST_MARKER (1 << 18)
913 #define JICST_SDONE (1 << 17)
914 #define JICST_CDONE (1 << 16)
915 #define JICST_INTE (1 << 3)
916 #define JICST_INTM (1 << 2)
917 #define JICST_INTSD (1 << 1)
918 #define JICST_INTCD (1 << 0)
919
920 #define JDCCTRL_DISDC (1 << 20)
921 #define JDCCTRL_SETDC(n) (1 << ((n) + 16))
922 #define JDCCTRL_DCCOMP_MASK 0xFFFF
923
924 #define JMCTRL_DC_TAB(n) (1 << (2*(n)))
925 #define JMCTRL_AC_TAB(n) (1 << (2*(n)+1))
926 #define JMCTRL_NUMCMP (1 << 8)
927 #define JMCTRL_CMP(n) (1 << (4*(n) + 16))
928 #define JMCTRL_420_MODE (0 << 14)
929 #define JMCTRL_422_MODE (1 << 14)
930 #define JMCTRL_444_MODE (2 << 14)
931
932 #define JMCTRL_UNUSED_BITS ((1 << 13) | (1 << 12) | (1 << 11))
933
934 #define AC_HUFFTABLE_OFFSET(t) ((t) * 0x100)
935 #define DC_HUFFTABLE_OFFSET(t) ((t) * 0x10 + 0x200)
936
937 #define AC_OSETTABLE_OFFSET(t) ((t) * 0x10)
938 #define DC_OSETTABLE_OFFSET(t) ((t) * 0x10 + 0x20)
939
940 #define AC_MAXCTABLE_OFFSET(t) ((t) * 0x10)
941 #define DC_MAXCTABLE_OFFSET(t) ((t) * 0x10 + 0x20)
942
943 /*---------------------------------------------------------------------------*/
944 /* External Memory Interface */
945 #define SDCS HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x00)
946 #define SDSA HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x04)
947 #define SDSB HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x08)
948 #define SDSC HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x0C)
949 #define SDEM HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x10)
950 #define SDPT HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x14)
951 #define SDIDL HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x18)
952 #define SDRTC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x1C)
953 #define SDWTC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x20)
954 #define SDRDC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x24)
955 #define SDWDC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x28)
956 #define SDRAC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x2C)
957 #define SDCYC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x30)
958 #define SDACC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x34)
959 #define SDDAT HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x38)
960 #define SDSECSRT0 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x3C)
961 #define SDSECEND0 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x40)
962 #define SDSECSRT1 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x44)
963 #define SDSECEND1 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x48)
964 #define SDSECSRT2 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x4C)
965 #define SDSECEND2 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x50)
966 #define SDSECSRT3 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x54)
967 #define SDSECEND3 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x58)
968 #define SDDELC0 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x5C)
969 #define SDDELS0 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x60)
970 #define SDDELC1 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x64)
971 #define SDDELS1 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x68)
972 #define SDDELC2 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x6C)
973 #define SDDELS2 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x70)
974 #define SDDELC3 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x74)
975 #define SDDELS3 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x78)
976 #define SDTMC HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x7C)
977
978
979 /*---------------------------------------------------------------------------*/
980 /* Secondary Memory Interface */
981
982 #define SMICS HW_REGISTER_RW(SMI_BASE + 0x00)
983 #define SMIL HW_REGISTER_RW(SMI_BASE + 0x04)
984 #define SMIA HW_REGISTER_RW(SMI_BASE + 0x08)
985 #define SMID HW_REGISTER_RW(SMI_BASE + 0x0C)
986 #define SMIDSR0 HW_REGISTER_RW(SMI_BASE + 0x10)
987 #define SMIDSW0 HW_REGISTER_RW(SMI_BASE + 0x14)
988 #define SMIDSR1 HW_REGISTER_RW(SMI_BASE + 0x18)
989 #define SMIDSW1 HW_REGISTER_RW(SMI_BASE + 0x1C)
990 #define SMIDSR2 HW_REGISTER_RW(SMI_BASE + 0x20)
991 #define SMIDSW2 HW_REGISTER_RW(SMI_BASE + 0x24)
992 #define SMIDSR3 HW_REGISTER_RW(SMI_BASE + 0x28)
993 #define SMIDSW3 HW_REGISTER_RW(SMI_BASE + 0x2C)
994 #define SMIDC HW_REGISTER_RW(SMI_BASE + 0x30)
995 #define SMIDCS HW_REGISTER_RW(SMI_BASE + 0x34)
996 #define SMIDA HW_REGISTER_RW(SMI_BASE + 0x38)
997 #define SMIDD HW_REGISTER_RW(SMI_BASE + 0x3C)
998 #define SMIFD HW_REGISTER_RW(SMI_BASE + 0x40)
999
1000 #define SMI_FIFO_ADDRESS(device,addr) (((((device))&0x3)<<8)|((addr)&0xff))
1001
1002 // SMI control register bits
1003 #define SMICS_ENABLE 0
1004 #define SMICS_DONE 1
1005 #define SMICS_ACTIVE 2
1006 #define SMICS_START 3
1007 #define SMICS_CLEARFIFO 4
1008 #define SMICS_WRITE 5
1009 #define SMICS_PAD 6
1010 #define SMICS_TEEN 8
1011 #define SMICS_INTD 9
1012 #define SMICS_INTT 10
1013 #define SMICS_INTR 11
1014 #define SMICS_PVMODE 12
1015 #define SMICS_SETERR 13
1016 #define SMICS_PXLDAT 14
1017 #define SMICS_EDREQ 15
1018 #define SMICS_AFERR 25
1019 #define SMICS_TXW 26
1020 #define SMICS_RXR 27
1021 #define SMICS_TXD 28
1022 #define SMICS_RXD 29
1023 #define SMICS_TXE 30
1024 #define SMICS_RXF 31
1025
1026 // SMI address and direct address register bits.
1027 #define SMIA_DEVICE 8
1028 #define SMIDA_DEVICE 8
1029
1030 // SMI DSR* and DSW* common fields
1031 #define SMIDS_STROBE 0
1032 #define SMIDS_DREQ 7
1033 #define SMIDS_PACE 8
1034 #define SMIDS_PACEALL 15
1035 #define SMIDS_HOLD 16
1036 #define SMIDS_SETUP 24
1037 #define SMIDS_WIDTH 30
1038 // SMI DSR* register specific
1039 #define SMIDS_FSETUP 22
1040 #define SMIDS_MODE68 23
1041 // SMI DSW* register specific
1042 #define SMIDS_SWAP 22
1043 #define SMIDS_FORMAT 23
1044
1045 // SMI direct control/status register bits.
1046 #define SMIDCS_ENABLE 0
1047 #define SMIDCS_START 1
1048 #define SMIDCS_DONE 2
1049 #define SMIDCS_WRITE 3
1050
1051 // SMI dma control threshold register bits.
1052 #define SMIDC_REQW 0
1053 #define SMIDC_REQR 6
1054 #define SMIDC_PANICW 12
1055 #define SMIDC_PANICR 18
1056 #define SMIDC_DMAP 24
1057 #define SMIDC_DMAEN 28
1058
1059 // SMI FIFO debug
1060 #define SMIFD_FCNT 0
1061 #define SMIFD_FLVL 8
1062
1063 /*---------------------------------------------------------------------------*/
1064 /* AC'97/I2S Controller */
1065 #define ACISCS HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x00 )
1066 #define ACISFIFO HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x04 )
1067 #define ACISCA HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x08 )
1068 #define ACISCD HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x0C )
1069 #define ACISMODE HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x10 )
1070 #define ACISASR HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x14 )
1071
1072 #define ACPLAYRATE 0x2c
1073 #define ACRECORDRATE 0x32
1074
1075 /*---------------------------------------------------------------------------*/
1076 /* SLIMbus interface */
1077 #define SLIM_NUM_DCC 10 /* there are 10 data channel controllers */
1078 #define SLIM_DCC_BASE(n) (SLIM_BASE + 0x200 + (n) * 0x20)
1079 #define SLIM_DCC_PA0(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x00)
1080 #define SLIM_DCC_PA1(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x04)
1081 #define SLIM_DCC_CON(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x08)
1082 #define SLIM_DCC_STAT(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x0c)
1083
1084 #if defined(__BCM2708A0__)
1085 // backward compatibility for drivers that use B0 register definitions
1086 #define SLIM_MC_IN_CON SLIM_SMC_IN_CON
1087 #define SLIM_MC_OUT_CON SLIM_SMC_OUT_CON
1088 #define SLIM_MC_IN_STAT SLIM_SMC_IN_STAT
1089 #define SLIM_MC_OUT_STAT SLIM_SMC_OUT_STAT
1090 #define SLIM_DMA_MC_TX SLIM_DMA_SMC_TX
1091 #define SLIM_DMA_MC_RX SLIM_DMA_SMC_RX
1092 #endif
1093
1094 /*---------------------------------------------------------------------------*/
1095 /* USB Peripheral */
1096 #define USB_DIEPINT_off(n) HW_REGISTER_RW(&USB_DIEPINT+(n*0x20))
1097 #define USB_HCINT_off(n) HW_REGISTER_RW(&USB_HCINT+(n*0x20))
1098
1099 #define USB_DFIFOn(n) HW_REGISTER_RW(USB_BASE+0x1000+(n*0x1000))
1100 #define USB_DIEPCTLn(n) HW_REGISTER_RW(USB_BASE+0x0900+(n*0x20))
1101 #define USB_DIEPTSIZn(n) HW_REGISTER_RW(USB_BASE+0x0910+(n*0x20))
1102 #define USB_DIEPDMAn(n) HW_REGISTER_RW(USB_BASE+0x0914+(n*0x20))
1103 #define USB_DTXFSTSn(n) HW_REGISTER_RW(USB_BASE+0x0918+(n*0x20))
1104
1105 #define USB_MDIO_CSR HW_REGISTER_RW( USB_BASE + 0x80 )
1106 #define USB_MDIO_GEN HW_REGISTER_RW( USB_BASE + 0x84 )
1107 #define USB_VBUS_DRV HW_REGISTER_RW( USB_BASE + 0x88 )
1108 #define USB_VBUS_DRV_SESSEND (1<<0)
1109 #define USB_VBUS_DRV_VBUSVALID (1<<1)
1110 #define USB_VBUS_DRV_BVALID (1<<2)
1111 #define USB_VBUS_DRV_AVALID (1<<3)
1112 #define USB_VBUS_DRV_DRVVBUS (1<<4)
1113 #define USB_VBUS_DRV_CHRGVBUS (1<<5)
1114 #define USB_VBUS_DRV_DISCHRGVBUS (1<<6)
1115
1116 /*---------------------------------------------------------------------------*/
1117 /* PCM Controller */
1118 #define PCMCS PCM_CS_A
1119 //#define PCMFIFO PCM_FIFO_A erroneously defined as _RO in bcm2708_chip/pcm.h
1120 #define PCMFIFO HW_REGISTER_RW( PCM_BASE + 0x04 )
1121 #define PCMMODE PCM_MODE_A
1122 #define PCMRXC PCM_RXC_A
1123 #define PCMTXC PCM_TXC_A
1124 #define PCMDREQ HW_REGISTER_RW( PCM_BASE + 0x14 )
1125 #define PCMINTEN HW_REGISTER_RW( PCM_BASE + 0x18 )
1126 #define PCMINTSTC HW_REGISTER_RW( PCM_BASE + 0x1c )
1127
1128
1129 // bit fields for PCMCS
1130 #define PCMCS_EN (1 << 0)
1131 #define PCMCS_RXON (1 << 1)
1132 #define PCMCS_TXON (1 << 2)
1133 #define PCMCS_TXCLR (1 << 3)
1134 #define PCMCS_RXCLR (1 << 4)
1135 #define PCMCS_TXTHR_LSB 5
1136 #define PCMCS_TXTHR_EMPTY (0 << PCMCS_TXTHR_LSB)
1137 #define PCMCS_TXTHR_1_QUARTER (1 << PCMCS_TXTHR_LSB)
1138 #define PCMCS_TXTHR_3_QUARTER (2 << PCMCS_TXTHR_LSB)
1139 #define PCMCS_TXTHR_FULL (3 << PCMCS_TXTHR_LSB)
1140 #define PCMCS_RXTHR_LSB 7
1141 #define PCMCS_RXTHR_EMPTY (0 << PCMCS_RXTHR_LSB)
1142 #define PCMCS_RXTHR_1_QUARTER (1 << PCMCS_RXTHR_LSB)
1143 #define PCMCS_RXTHR_3_QUARTER (2 << PCMCS_RXTHR_LSB)
1144 #define PCMCS_RXTHR_FULL (3 << PCMCS_RXTHR_LSB)
1145
1146 #define PCMCS_DMAEN (1 << 9)
1147 #define PCMCS_INTT (1 << 10)
1148 #define PCMCS_INTR (1 << 11)
1149 #define PCMCS_INTE (1 << 12)
1150 #define PCMCS_TXSYNC (1 << 13)
1151 #define PCMCS_RXSYNC (1 << 14)
1152 #define PCMCS_TXERR (1 << 15)
1153 #define PCMCS_RXERR (1 << 16)
1154 #define PCMCS_TXW (1 << 17)
1155 #define PCMCS_RXR (1 << 18)
1156 #define PCMCS_TXD (1 << 19)
1157 #define PCMCS_RXD (1 << 20)
1158 #define PCMCS_TXE (1 << 21)
1159 #define PCMCS_RXF (1 << 22)
1160 #define PCMCS_RXSEX (1 << 23)
1161 #define PCMCS_SYNC (1 << 24)
1162
1163 // bit fields for PCMMODE
1164 #define PCMMODE_FSI (1 << 20)
1165 #define PCMMODE_FSM (1 << 21)
1166 #define PCMMODE_CLKI (1 << 22)
1167 #define PCMMODE_CLKM (1 << 23)
1168 #define PCMMODE_FLEN 10
1169 #define PCMMODE_FSLEN 0
1170 #define PCMMODE_FTXP (1 << 24)
1171 #define PCMMODE_FRXP (1 << 25)
1172 #define PCMMODE_PDMRX (1 << 26)
1173 #define PCMMODE_PDMRXN (1 << 27)
1174
1175 // macros for PCMTXC and PCMRXC
1176 #define PCM_CH1POS_LSB 20
1177 #define PCM_CH1WID_LSB 16
1178 #define PCM_CH2POS_LSB 4
1179 #define PCM_CH2WID_LSB 0
1180 // parameters --> bitmasks
1181 #define PCM_CH1WEX (1 << 31)
1182 #define PCM_CH2WEX (1 << 15)
1183 #define PCM_WIDTH2(x) ( (((x - 8) & 0x0f) << PCM_CH2WID_LSB) + PCM_CH2WEX * (((x-8)&0x10)>>4) )
1184 #define PCM_POS2(x) (((x) & 0x3ff) << PCM_CH2POS_LSB)
1185 #define PCM_WIDTH1(x) ( (((x - 8) & 0x0f) << PCM_CH1WID_LSB) + PCM_CH1WEX * (((x-8)&0x10)>>4) )
1186 #define PCM_POS1(x) (((x) & 0x3ff) << PCM_CH1POS_LSB)
1187 #define PCM_CH2EN (1 << 14)
1188 #define PCM_CH1EN (1 << 30)
1189 // bitmasks --> parameters
1190 #define PCM_WID1(x) ( (((x >> PCM_CH1WID_LSB) & 0x0f) + 8) + ((x & PCM_CH1WEX) ? 16 : 0) )
1191 #define PCM_WID2(x) ( (((x >> PCM_CH2WID_LSB) & 0x0f) + 8) + ((x & PCM_CH2WEX) ? 16 : 0) )
1192
1193 // bit fields in the PCMDREQ register
1194 #define PCMDREQ_TXPANICTHR_LSB 24
1195 #define PCMDREQ_RXPANICTHR_LSB 16
1196 #define PCMDREQ_TXDREQTHR_LSB 8
1197 #define PCMDREQ_RXDREQTHR_LSB 0
1198
1199 #define PCM_FIFO_DEPTH 64 // words
1200
1201
1202 /*---------------------------------------------------------------------------*/
1203 /* I2C Master */
1204 #define I2CC_0 HW_REGISTER_RW(I2C_BASE_0 + 0x00)
1205 #define I2CS_0 HW_REGISTER_RW(I2C_BASE_0 + 0x04)
1206 #define I2CDLEN_0 HW_REGISTER_RW(I2C_BASE_0 + 0x08)
1207 #define I2CA_0 HW_REGISTER_RW(I2C_BASE_0 + 0x0C)
1208 #define I2CFIFO_0 HW_REGISTER_RW(I2C_BASE_0 + 0x10)
1209 #define I2CDIV_0 HW_REGISTER_RW(I2C_BASE_0 + 0x14)
1210 #define I2CDEL_0 HW_REGISTER_RW(I2C_BASE_0 + 0x18)
1211 #define I2CCLKT_0 HW_REGISTER_RW(I2C_BASE_0 + 0x1C)
1212
1213 #define I2CC_1 HW_REGISTER_RW(I2C_BASE_1 + 0x00)
1214 #define I2CS_1 HW_REGISTER_RW(I2C_BASE_1 + 0x04)
1215 #define I2CDLEN_1 HW_REGISTER_RW(I2C_BASE_1 + 0x08)
1216 #define I2CA_1 HW_REGISTER_RW(I2C_BASE_1 + 0x0C)
1217 #define I2CFIFO_1 HW_REGISTER_RW(I2C_BASE_1 + 0x10)
1218 #define I2CDIV_1 HW_REGISTER_RW(I2C_BASE_1 + 0x14)
1219 #define I2CDEL_1 HW_REGISTER_RW(I2C_BASE_1 + 0x18)
1220 #define I2CCLKT_1 HW_REGISTER_RW(I2C_BASE_1 + 0x1C)
1221
1222 #define I2CC_2 HW_REGISTER_RW(I2C_BASE_2 + 0x00)
1223 #define I2CS_2 HW_REGISTER_RW(I2C_BASE_2 + 0x04)
1224 #define I2CDLEN_2 HW_REGISTER_RW(I2C_BASE_2 + 0x08)
1225 #define I2CA_2 HW_REGISTER_RW(I2C_BASE_2 + 0x0C)
1226 #define I2CFIFO_2 HW_REGISTER_RW(I2C_BASE_2 + 0x10)
1227 #define I2CDIV_2 HW_REGISTER_RW(I2C_BASE_2 + 0x14)
1228 #define I2CDEL_2 HW_REGISTER_RW(I2C_BASE_2 + 0x18)
1229 #define I2CCLKT_2 HW_REGISTER_RW(I2C_BASE_2 + 0x1C)
1230
1231 #define I2CC_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x00 )
1232 #define I2CS_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x04 )
1233 #define I2CDLEN_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x08 )
1234 #define I2CA_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x0C )
1235 #define I2CFIFO_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x10 )
1236 #define I2CDIV_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x14 )
1237 #define I2CDEL_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x18 )
1238 #define I2CCLKT_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x1C )
1239
1240 // define some bitfields within these I2C registers...
1241 #define I2CC_EN (1 << 15)
1242 #define I2CC_INTR (1 << 10)
1243 #define I2CC_INTT (1 << 9)
1244 #define I2CC_INTD (1 << 8)
1245 #define I2CC_START (1 << 7)
1246 #define I2CC_CLEAR (3 << 4)
1247 #define I2CC_READ (1 << 0)
1248
1249 #define I2CS_CLKT (1 << 9)
1250 #define I2CS_ERR (1 << 8)
1251 #define I2CS_RXF (1 << 7)
1252 #define I2CS_TXE (1 << 6)
1253 #define I2CS_RXD (1 << 5)
1254 #define I2CS_TXD (1 << 4)
1255 #define I2CS_RXR (1 << 3)
1256 #define I2CS_TXW (1 << 2)
1257 #define I2CS_DONE (1 << 1)
1258 #define I2CS_TA (1 << 0)
1259
1260 #define I2CDEL_FEDL (16)
1261 #define I2CDEL_REDL (0)
1262
1263 //Note! Remove this eventually.
1264 //Just define the old VCII I2C peripheral
1265 #define I2CC I2CC_0
1266 #define I2CS I2CS_0
1267 #define I2CDLEN I2CDLEN_0
1268 #define I2CA I2CA_0
1269 #define I2CFIFO I2CFIFO_0
1270 #define I2CDIV I2CDIV_0
1271 #define I2CDEL I2CDEL_0
1272 #define I2CCLKT I2CCLKT_0
1273
1274 /*---------------------------------------------------------------------------*/
1275 /* Performance Monitor */
1276 #define PRMCS HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x00)
1277 #define PRMCV HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x04)
1278 #define PRMSCC HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x08)
1279
1280 /*---------------------------------------------------------------------------*/
1281 /* OTP */
1282
1283 //#define OTP_CONFIG_REG OTP_WRAP_CONFIG_REG
1284 //OTP bit definitions
1285 // NB the addressing has changed between VCIII and VCIV - we now address by row (each row contains 32 bits)
1286 #define OTP_JTAG_DEBUG_KEY_ROW 8
1287 #define OTP_JTAG_DEBUG_KEY_SIZE_IN_ROWS 4
1288 #define OTP_VPU_CACHE_KEY_ROW (OTP_JTAG_DEBUG_KEY_ROW+OTP_JTAG_DEBUG_KEY_SIZE_IN_ROWS)
1289 #define OTP_VPU_CACHE_KEY_SIZE_IN_ROWS 4
1290
1291 #define OTP_CONTROL_ROW (OTP_VPU_CACHE_KEY_ROW+OTP_VPU_CACHE_KEY_SIZE_IN_ROWS)
1292 #define OTP_CONTROL_SIZE_IN_ROWS 1
1293
1294 #define OTP_BOOT_ROM_ROW (OTP_CONTROL_ROW+OTP_CONTROL_SIZE_IN_ROWS)
1295 #define OTP_BOOT_ROM_SIZE_IN_ROWS 1
1296
1297 #define OTP_BOOT_ROM_ROW_REDUNDANT (OTP_BOOT_ROM_ROW+OTP_BOOT_ROM_SIZE_IN_ROWS)
1298
1299 #ifdef __BCM2708A0__
1300 #define OTP_BOOT_SIGNING_KEY_ROW (OTP_BOOT_ROM_ROW_REDUNDANT+OTP_BOOT_ROM_SIZE_IN_ROWS)
1301 #define OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS 4
1302
1303 #define OTP_BOOT_SIGNING_PARITY_ROW (OTP_BOOT_SIGNING_KEY_ROW+OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS)
1304 #define OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS 1
1305
1306 #define OTP_CODE_SIGNING_KEY_ROW (OTP_BOOT_SIGNING_PARITY_ROW+OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS)
1307 #define OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS 4
1308
1309 #define OTP_CODE_SIGNING_PARITY_ROW (OTP_CODE_SIGNING_KEY_ROW+OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS)
1310 #define OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS 1
1311
1312 #define OTP_HDCP_AES_KEY_ROW (OTP_CODE_SIGNING_PARITY_ROW+OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS)
1313 #define OTP_HDCP_AES_KEY_SIZE_IN_ROWS 4
1314
1315 #define OTP_HDCP_AES_PARITY_ROW (OTP_HDCP_AES_KEY_ROW+OTP_HDCP_AES_KEY_SIZE_IN_ROWS)
1316 #define OTP_HDCP_AES_PARITY_SIZE_IN_ROWS 1
1317
1318 #define OTP_PUBLIC_KEY_ROW (OTP_HDCP_AES_PARITY_ROW+OTP_HDCP_AES_PARITY_SIZE_IN_ROWS)
1319 #define OTP_PUBLIC_KEY_SIZE_IN_ROWS 4
1320
1321 #define OTP_PUBLIC_PARITY_ROW (OTP_PUBLIC_KEY_ROW+OTP_PUBLIC_KEY_SIZE_IN_ROWS)
1322 #define OTP_PUBLIC_PARITY_SIZE_IN_ROWS 1
1323
1324 #define OTP_PRIVATE_KEY_ROW (OTP_PUBLIC_PARITY_ROW+OTP_PUBLIC_PARITY_SIZE_IN_ROWS)
1325 #define OTP_PRIVATE_KEY_SIZE_IN_ROWS 4
1326
1327 #define OTP_PRIVATE_PARITY_ROW (OTP_PRIVATE_KEY_ROW+OTP_PRIVATE_KEY_SIZE_IN_ROWS)
1328 #define OTP_PRIVATE_PARITY_SIZE_IN_ROWS 1
1329
1330 #define OTP_CODE_SIGNING_FLAG_ROW (OTP_PRIVATE_PARITY_ROW+OTP_PRIVATE_PARITY_SIZE_IN_ROWS)
1331 #define OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS 1
1332
1333 // Suspend/resume secure RAM key: ensure that these values match the ones
1334 // used in vcsuspend_asm_vc4.s
1335 #define OTP_SUSPEND_SECURE_RAM_KEY (OTP_CODE_SIGNING_FLAG_ROW+OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS) // 64
1336 #define OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS 2
1337
1338 // to allow A0 to continue to build without too many #ifdefs define the redundant rows to be the same as the original
1339 #define OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT OTP_BOOT_SIGNING_KEY_ROW
1340 #define OTP_CODE_SIGNING_KEY_ROW_REDUNDANT OTP_CODE_SIGNING_KEY_ROW
1341 #define OTP_HDCP_AES_KEY_ROW_REDUNDANT OTP_HDCP_AES_KEY_ROW
1342 #define OTP_PUBLIC_KEY_ROW_REDUNDANT OTP_PUBLIC_KEY_ROW
1343 #define OTP_PRIVATE_KEY_ROW_REDUNDANT OTP_PRIVATE_KEY_ROW
1344 #else
1345 // BCM2708B0 has less reliable OTP so we need a redundant row for the boot signing key (and the corresponding parity)
1346 #define OTP_BOOT_SIGNING_KEY_ROW (OTP_BOOT_ROM_ROW_REDUNDANT+OTP_BOOT_ROM_SIZE_IN_ROWS) // 19
1347 #define OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS 4
1348
1349 #define OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT (OTP_BOOT_SIGNING_KEY_ROW+OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS) // 23
1350
1351 #define OTP_BOOT_SIGNING_PARITY_ROW (OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT+OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS) // 27
1352 #define OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS 1
1353
1354 #define OTP_CODE_SIGNING_KEY_ROW (OTP_BOOT_SIGNING_PARITY_ROW+OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS) // 28
1355 #define OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS 4
1356
1357 #define OTP_CODE_SIGNING_KEY_ROW_REDUNDANT (OTP_CODE_SIGNING_KEY_ROW+OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS) // 32
1358
1359 #define OTP_CODE_SIGNING_PARITY_ROW (OTP_CODE_SIGNING_KEY_ROW_REDUNDANT+OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS) // 36
1360 #define OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS 1
1361
1362 #define OTP_HDCP_AES_KEY_ROW (OTP_CODE_SIGNING_PARITY_ROW+OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS) // 37
1363 #define OTP_HDCP_AES_KEY_SIZE_IN_ROWS 4
1364
1365 #define OTP_HDCP_AES_KEY_ROW_REDUNDANT (OTP_HDCP_AES_KEY_ROW+OTP_HDCP_AES_KEY_SIZE_IN_ROWS) // 41
1366
1367 #define OTP_HDCP_AES_PARITY_ROW (OTP_HDCP_AES_KEY_ROW_REDUNDANT+OTP_HDCP_AES_KEY_SIZE_IN_ROWS) // 45
1368 #define OTP_HDCP_AES_PARITY_SIZE_IN_ROWS 1
1369
1370 #define OTP_PUBLIC_KEY_ROW (OTP_HDCP_AES_PARITY_ROW+OTP_HDCP_AES_PARITY_SIZE_IN_ROWS) // 46
1371 #define OTP_PUBLIC_KEY_SIZE_IN_ROWS 4
1372
1373 #define OTP_PUBLIC_KEY_ROW_REDUNDANT (OTP_PUBLIC_KEY_ROW+OTP_PUBLIC_KEY_SIZE_IN_ROWS) // 50
1374
1375 #define OTP_PUBLIC_PARITY_ROW (OTP_PUBLIC_KEY_ROW_REDUNDANT+OTP_PUBLIC_KEY_SIZE_IN_ROWS) // 54
1376 #define OTP_PUBLIC_PARITY_SIZE_IN_ROWS 1
1377
1378 #define OTP_PRIVATE_KEY_ROW (OTP_PUBLIC_PARITY_ROW+OTP_PUBLIC_PARITY_SIZE_IN_ROWS) // 55
1379 #define OTP_PRIVATE_KEY_SIZE_IN_ROWS 4
1380
1381 #define OTP_PRIVATE_KEY_ROW_REDUNDANT (OTP_PRIVATE_KEY_ROW+OTP_PRIVATE_KEY_SIZE_IN_ROWS) // 59
1382
1383 #define OTP_PRIVATE_PARITY_ROW (OTP_PRIVATE_KEY_ROW_REDUNDANT+OTP_PRIVATE_KEY_SIZE_IN_ROWS) // 63
1384 #define OTP_PRIVATE_PARITY_SIZE_IN_ROWS 1
1385
1386 #define OTP_CODE_SIGNING_FLAG_ROW (OTP_PRIVATE_PARITY_ROW+OTP_PRIVATE_PARITY_SIZE_IN_ROWS) // 64
1387 #define OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS 1
1388
1389 // Suspend/resume secure RAM key: ensure that these values match the ones
1390 // used in vcsuspend_asm_vc4.s
1391 #define OTP_SUSPEND_SECURE_RAM_KEY (OTP_CODE_SIGNING_FLAG_ROW+OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS) // 65
1392 #define OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS 2
1393
1394 // strictly this is C0 only
1395 #define OTP_BOOT_EXTRAS_ROW (OTP_SUSPEND_SECURE_RAM_KEY+OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS) // 67
1396 #define OTP_BOOT_EXTRAS_ROW_SIZE_IN_ROWS 1
1397 // locations fixed by hardware
1398 #define OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT 68
1399 #define OTP_VPU_CACHE_KEY_ROW_REDUNDANT 72
1400 #define OTP_JTAG_VPU_PARITY_REDUNDANT 76
1401
1402 #if( OTP_BOOT_EXTRAS_ROW+OTP_BOOT_EXTRAS_ROW_SIZE_IN_ROWS > OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT )
1403 #error "User OTP space has overwritten CPU bits" OTP_SUSPEND_SECURE_RAM_KEY OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT
1404 #endif
1405
1406 #endif
1407
1408
1409 #define OTP_MIN_ROW OTP_JTAG_DEBUG_KEY_ROW
1410 #define OTP_MAX_ROW OTP_SUSPEND_SECURE_RAM_KEY
1411
1412 // bit locations in the CONTROL OTP register
1413 #define OTP_JTAG_DEBUG_KEY_PARITY_START_BIT 0
1414 #define OTP_VPU_CACHE_KEY_PARITY_START_BIT 8
1415 #define OTP_JTAG_DISABLE_BIT 16
1416 #define OTP_JTAG_DISABLE_REDUNDANT_BIT 17
1417 #define OTP_MACROVISION_START_BIT 18
1418 #define OTP_MACROVISION_REDUNDANT_START_BIT 20
1419 #define OTP_DECRYPTION_ENABLE_FOR_DEBUG 22
1420 #define OTP_ARM_DISABLE_BIT 24
1421 #define OTP_ARM_DISABLE_REDUNDANT_BIT 25
1422
1423 #define OTP_JTAG_PARITY_MASK 0xFF
1424 #define OTP_VPU_CACHE_PARITY_MASK 0xFF
1425
1426 #define OTP_BYTES_PER_ROW 4
1427
1428 // make sure locations used by the hardware are correct
1429 #if( OTP_CONTROL_ROW != 16)
1430 #error "The OTP control row has moved - it must be 16!"
1431 #endif
1432 #if( OTP_BOOT_ROM_ROW != 17 )
1433 #error "The OTP bootrom row has moved - it must be 17!"
1434 #endif
1435 #if( OTP_BOOT_ROM_ROW_REDUNDANT != 18 )
1436 #error "The OTP bootrom copy row has moved - it must be 18!"
1437 #endif
1438
1439 /*---------------------------------------------------------------------------*/
1440 /* Threading unit */
1441
1442 /* Registers for the threading unit */
1443 #define TH0_BASE 0x18011000
1444 #define TH0_ADDR_MASK 0x0000003F
1445 #define TH1_BASE 0x1A008000
1446 #define TH1_ADDR_MASK 0x0000003F
1447
1448 #define TH0CS HW_REGISTER_RW(TH0_BASE + 0x00)
1449 #define TH0CFG HW_REGISTER_RW(TH0_BASE + 0x04)
1450 #define TH0STPC HW_REGISTER_RW(TH0_BASE + 0x08)
1451 #define TH0ITPC HW_REGISTER_RW(TH0_BASE + 0x0C)
1452 #define TH0T0PC HW_REGISTER_RW(TH0_BASE + 0x10)
1453 #define TH0T0UD HW_REGISTER_RW(TH0_BASE + 0x14)
1454 #define TH0T1PC HW_REGISTER_RW(TH0_BASE + 0x18)
1455 #define TH0T1UD HW_REGISTER_RW(TH0_BASE + 0x1C)
1456 #define TH0T2PC HW_REGISTER_RW(TH0_BASE + 0x20)
1457 #define TH0T2UD HW_REGISTER_RW(TH0_BASE + 0x24)
1458 #define TH0T3PC HW_REGISTER_RW(TH0_BASE + 0x28)
1459 #define TH0T3UD HW_REGISTER_RW(TH0_BASE + 0x2C)
1460
1461 #define TH1CS HW_REGISTER_RW(TH1_BASE + 0x00)
1462 #define TH1CFG HW_REGISTER_RW(TH1_BASE + 0x04)
1463 #define TH1STPC HW_REGISTER_RW(TH1_BASE + 0x08)
1464 #define TH1ITPC HW_REGISTER_RW(TH1_BASE + 0x0C)
1465 #define TH1T0PC HW_REGISTER_RW(TH1_BASE + 0x10)
1466 #define TH1T0UD HW_REGISTER_RW(TH1_BASE + 0x14)
1467 #define TH1T1PC HW_REGISTER_RW(TH1_BASE + 0x18)
1468 #define TH1T1UD HW_REGISTER_RW(TH1_BASE + 0x1C)
1469 #define TH1T2PC HW_REGISTER_RW(TH1_BASE + 0x20)
1470 #define TH1T2UD HW_REGISTER_RW(TH1_BASE + 0x24)
1471 #define TH1T3PC HW_REGISTER_RW(TH1_BASE + 0x28)
1472 #define TH1T3UD HW_REGISTER_RW(TH1_BASE + 0x2C)
1473
1474 /* Windows Open GL plugin - emulator only */
1475 #define WOGLPTR HW_REGISTER_RW(0x1C00FFFC)
1476
1477 /* Hardware 3D unit */
1478
1479 #define GR_VCACHE_BASE 0x1a00a000
1480 #define GR_VCACHE_ADDR_MASK 0x00001fff
1481 #define GR_VCACHE_SIZE 0x00002000 // in bytes
1482
1483 #define GR_UNIFORM_BASE 0x1a00c000
1484 #define GR_UNIFORM_ADDR_MASK 0x00000fff
1485 #define GR_UNIFORM_SIZE 0x00001000 // in bytes
1486
1487 /* Registers for Vertex Cache Manager */
1488 #define GR_VCM_BASE 0x1A005C00
1489 #define GR_VCM_ADDR_MASK 0x0000003f
1490 #define GR_VCM_CI_BASE 0x1A005C80
1491 #define GR_VCM_CI_ADDR_MASK 0x0000007f
1492
1493 #define GRMCS HW_REGISTER_RW(GR_VCM_BASE + 0x00)
1494 #define GRMCFG HW_REGISTER_RW(GR_VCM_BASE + 0x04)
1495 #define GRMSVI HW_REGISTER_RW(GR_VCM_BASE + 0x08)
1496 #define GRMSADR HW_REGISTER_RW(GR_VCM_BASE + 0x0C)
1497 #define GRMSCT HW_REGISTER_RW(GR_VCM_BASE + 0x10)
1498 #define GRMOADR HW_REGISTER_RW(GR_VCM_BASE + 0x14)
1499 #define GRMOCT HW_REGISTER_RW(GR_VCM_BASE + 0x18)
1500 #define GRMMCT HW_REGISTER_RW(GR_VCM_BASE + 0x1C)
1501 #define GRMSSI0 HW_REGISTER_RW(GR_VCM_BASE + 0x20)
1502 #define GRMSSI1 HW_REGISTER_RW(GR_VCM_BASE + 0x24)
1503 #define GRMCCT HW_REGISTER_RW(GR_VCM_BASE + 0x28)
1504
1505 #define GRMCIL0 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x00)
1506 #define GRMCIL1 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x20)
1507 #define GRMCIH0 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x40)
1508 #define GRMCIH1 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x60)
1509
1510 #define GR_VCD_BASE 0x1A005A00
1511 #define GR_VCD_ADDR_MASK 0x0000007f
1512
1513 #define GRDCS HW_REGISTER_RW(GR_VCD_BASE + 0x00)
1514 #define GRDCFG HW_REGISTER_RW(GR_VCD_BASE + 0x04)
1515 #define GRDACFG0 HW_REGISTER_RW(GR_VCD_BASE + 0x20)
1516 #define GRDACFG1 HW_REGISTER_RW(GR_VCD_BASE + 0x24)
1517 #define GRDACFG2 HW_REGISTER_RW(GR_VCD_BASE + 0x28)
1518 #define GRDACFG3 HW_REGISTER_RW(GR_VCD_BASE + 0x2C)
1519 #define GRDACFG4 HW_REGISTER_RW(GR_VCD_BASE + 0x30)
1520 #define GRDACFG5 HW_REGISTER_RW(GR_VCD_BASE + 0x34)
1521 #define GRDACFG6 HW_REGISTER_RW(GR_VCD_BASE + 0x38)
1522 #define GRDACFG7 HW_REGISTER_RW(GR_VCD_BASE + 0x3C)
1523 #define GRDAADR0 HW_REGISTER_RW(GR_VCD_BASE + 0x40)
1524 #define GRDAADR1 HW_REGISTER_RW(GR_VCD_BASE + 0x44)
1525 #define GRDAADR2 HW_REGISTER_RW(GR_VCD_BASE + 0x48)
1526 #define GRDAADR3 HW_REGISTER_RW(GR_VCD_BASE + 0x4C)
1527 #define GRDAADR4 HW_REGISTER_RW(GR_VCD_BASE + 0x50)
1528 #define GRDAADR5 HW_REGISTER_RW(GR_VCD_BASE + 0x54)
1529 #define GRDAADR6 HW_REGISTER_RW(GR_VCD_BASE + 0x58)
1530 #define GRDAADR7 HW_REGISTER_RW(GR_VCD_BASE + 0x5C)
1531
1532 /* Registers for Primitive Setup Engine */
1533 #define GR_PSE_BASE 0x1A005800
1534 #define GR_PSE_ADDR_MASK 0x0000007f
1535
1536 #define GRSCS HW_REGISTER_RW(GR_PSE_BASE + 0x00)
1537 #define GRSCFG HW_REGISTER_RW(GR_PSE_BASE + 0x04)
1538 #define GRSVADR HW_REGISTER_RW(GR_PSE_BASE + 0x08)
1539 #define GRSVFMT HW_REGISTER_RW(GR_PSE_BASE + 0x0C)
1540 #define GRSSP HW_REGISTER_RW(GR_PSE_BASE + 0x10)
1541 #define GRSPADR HW_REGISTER_RW(GR_PSE_BASE + 0x14)
1542 #define GRSPCT HW_REGISTER_RW(GR_PSE_BASE + 0x18)
1543 #define GRSAADR HW_REGISTER_RW(GR_PSE_BASE + 0x1C)
1544 #define GRSACT HW_REGISTER_RW(GR_PSE_BASE + 0x20)
1545 #define GRSDOF HW_REGISTER_RW(GR_PSE_BASE + 0x24)
1546 #define GRSDOU HW_REGISTER_RW(GR_PSE_BASE + 0x28)
1547 #define GRSDMIN HW_REGISTER_RW(GR_PSE_BASE + 0x2C)
1548 #define GRSDMAX HW_REGISTER_RW(GR_PSE_BASE + 0x30)
1549 #define GRSPSZ HW_REGISTER_RW(GR_PSE_BASE + 0x34)
1550 #define GRSLW HW_REGISTER_RW(GR_PSE_BASE + 0x38)
1551 #define GRSFSF HW_REGISTER_RW(GR_PSE_BASE + 0x3C)
1552 #define GRSDZS HW_REGISTER_RW(GR_PSE_BASE + 0x40)
1553 #define GRSHPX HW_REGISTER_RW(GR_PSE_BASE + 0x44)
1554
1555 /* Debug Registers for Primitive Setup Engine */
1556 #define GR_PSE_DEBUG_BASE 0x1A005900
1557 #define GR_PSE_DEBUG_ADDR_MASK 0x00000003
1558
1559 #define GRS_DBGE HW_REGISTER_RW(GR_PSE_DEBUG_BASE + 0x00)
1560
1561 /* Registers for Pixel Pipeline */
1562 #define GR_PPL_BASE 0x1A005600
1563 #define GR_PPL_ADDR_MASK 0x0000007F
1564
1565 #define GRPCS HW_REGISTER_RW(GR_PPL_BASE + 0x00)
1566 #define GRPCFG HW_REGISTER_RW(GR_PPL_BASE + 0x04)
1567 #define GRPCLXY HW_REGISTER_RW(GR_PPL_BASE + 0x08)
1568 #define GRPCLSZ HW_REGISTER_RW(GR_PPL_BASE + 0x0C)
1569 #define GRPVORG HW_REGISTER_RW(GR_PPL_BASE + 0x10)
1570 // gap of 8 bytes
1571 // gap of 16 bytes
1572 // gap of 16 bytes
1573 #define GRPZBCG HW_REGISTER_RW(GR_PPL_BASE + 0x40)
1574 #define GRPSFCG HW_REGISTER_RW(GR_PPL_BASE + 0x44)
1575 #define GRPSBCG HW_REGISTER_RW(GR_PPL_BASE + 0x48)
1576 #define GRPSCC HW_REGISTER_RW(GR_PPL_BASE + 0x4C)
1577 #define GRPBCFG HW_REGISTER_RW(GR_PPL_BASE + 0x50)
1578 #define GRPBCC HW_REGISTER_RW(GR_PPL_BASE + 0x54)
1579 #define GRPCDSM HW_REGISTER_RW(GR_PPL_BASE + 0x58) // xxx dc4
1580 #define GRPCZSM HW_REGISTER_RW(GR_PPL_BASE + 0x58)
1581
1582 #define GRPCBS HW_REGISTER_RW(GR_PPL_BASE + 0x5C)
1583 #define GRPABS HW_REGISTER_RW(GR_PPL_BASE + 0x60)
1584 #define GRPFCOL HW_REGISTER_RW(GR_PPL_BASE + 0x64)
1585
1586 /* Debug Registers for Pixel Pipeline */
1587 #define GR_PPL_DEBUG_BASE 0x1A005740
1588 #define GR_PPL_DEBUG_ADDR_MASK 0x0000001F
1589
1590 #define GRP_FDBGO HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x00)
1591 #define GRP_FDBGB HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x04)
1592 #define GRP_FDBGR HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x08)
1593 #define GRP_FDBGS HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x0C)
1594 #define GRP_SDBG0 HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x10)
1595
1596
1597 /* Registers for the Frame Buffer Cache */
1598 #define GR_FBC_BASE 0x1A005400
1599 #define GR_FBC_ADDR_MASK 0x0000007F
1600
1601 #define GRFCS HW_REGISTER_RW(GR_FBC_BASE + 0x00)
1602 #define GRFCFG HW_REGISTER_RW(GR_FBC_BASE + 0x04)
1603 #define GRFTLOC HW_REGISTER_RW(GR_FBC_BASE + 0x08)
1604 #define GRFDIMS HW_REGISTER_RW(GR_FBC_BASE + 0x0C)
1605 #define GRFCCFG HW_REGISTER_RW(GR_FBC_BASE + 0x10)
1606 #define GRFCBA HW_REGISTER_RW(GR_FBC_BASE + 0x14)
1607 #define GRFZCFG HW_REGISTER_RW(GR_FBC_BASE + 0x1C)
1608 #define GRFZBA HW_REGISTER_RW(GR_FBC_BASE + 0x20)
1609 #define GRFZCV HW_REGISTER_RW(GR_FBC_BASE + 0x24)
1610 #define GRFSCV HW_REGISTER_RW(GR_FBC_BASE + 0x28)
1611 #define GRFCMSK HW_REGISTER_RW(GR_FBC_BASE + 0x2C)
1612 #define GRFECFG HW_REGISTER_RW(GR_FBC_BASE + 0x30)
1613 #define GRFEBA HW_REGISTER_RW(GR_FBC_BASE + 0x34)
1614 #define GRFCCV0 HW_REGISTER_RW(GR_FBC_BASE + 0x40)
1615 #define GRFCCV1 HW_REGISTER_RW(GR_FBC_BASE + 0x44)
1616 #define GRFCCV2 HW_REGISTER_RW(GR_FBC_BASE + 0x48)
1617 #define GRFCCV3 HW_REGISTER_RW(GR_FBC_BASE + 0x4C)
1618 #define GRFCCV4 HW_REGISTER_RW(GR_FBC_BASE + 0x50)
1619 #define GRFCCV5 HW_REGISTER_RW(GR_FBC_BASE + 0x54)
1620 #define GRFCCV6 HW_REGISTER_RW(GR_FBC_BASE + 0x58)
1621 #define GRFCCV7 HW_REGISTER_RW(GR_FBC_BASE + 0x5C)
1622
1623 #define GR_FBC_DEBUG_BASE 0x1A005500
1624 #define GR_FBC_DEBUG_ADDR_MASK 0x7F
1625
1626 #define GRFCSTAT HW_REGISTER_RW(GR_FBC_DEBUG_BASE + 0x00)
1627
1628 /* VPM access via VRF configuration */
1629 #define GR_VPM_VRFCFG_BASE 0x1A005D00
1630 #define GR_VPM_VRFCFG_ADDR_MASK 0x00000003
1631 #define GRVVSTRD HW_REGISTER_RW(GR_VPM_VRFCFG_BASE + 0x00)
1632
1633 /* Registers for the Texture Unit */
1634
1635 /* Mipmap pointer memoies (TU0 & TU1) */
1636 #define GRTMPM0_BASE 0x1A005E00
1637 #define GRTMPM1_BASE 0x1A005F00
1638
1639 #define GRTMPM0 HW_REGISTER_RW(GRTMPM0_BASE + 0x00)
1640 #define GRTMPM1 HW_REGISTER_RW(GRTMPM1_BASE + 0x00)
1641
1642 #define GRTMPM_MASK 0xFFFFFF00
1643
1644 #define GR_TU_BASE0 0x1A005200
1645 #define GR_TU_BASE1 0x1A005220
1646 #define GR_TU_BASE2 0x1A005240
1647 #define GR_TU_BASE3 0x1A005260
1648
1649 #define GR_TU_BASE4 0x1A005280
1650 #define GR_TU_BASE5 0x1A0052A0
1651 #define GR_TU_BASE6 0x1A0052C0
1652 #define GR_TU_BASE7 0x1A0052E0
1653
1654 #define GR_TU_DBG_BASE 0x1A005300
1655
1656 #define GR_TU_ADDR_MASK 0x000000FF
1657 #define GR_TU_UNIT_MASK 0xFFFFFF1F
1658
1659 /* Control/Status registers for TU0 & TU1 */
1660 #define GRTCS0 HW_REGISTER_RW(GR_TU_BASE0 + 0x00)
1661 #define GRTCS1 HW_REGISTER_RW(GR_TU_BASE4 + 0x00)
1662
1663 /* Common palette for all contexts per texutre unit */
1664 #define GRTPTBA0 HW_REGISTER_RW(GR_TU_BASE1 + 0x00)
1665 #define GRTPTBA1 HW_REGISTER_RW(GR_TU_BASE5 + 0x00)
1666
1667 /* 4 sets of context registers for physical texture unit 0 */
1668 #define GRTCFG0 HW_REGISTER_RW(GR_TU_BASE0 + 0x04)
1669 #define GRTDIM0 HW_REGISTER_RW(GR_TU_BASE0 + 0x08)
1670 #define GRTBCOL0 HW_REGISTER_RW(GR_TU_BASE0 + 0x0C)
1671 #define GRTLBIAS0 HW_REGISTER_RW(GR_TU_BASE0 + 0x1C)
1672
1673 #define GRTCFG1 HW_REGISTER_RW(GR_TU_BASE1 + 0x04)
1674 #define GRTDIM1 HW_REGISTER_RW(GR_TU_BASE1 + 0x08)
1675 #define GRTBCOL1 HW_REGISTER_RW(GR_TU_BASE1 + 0x0C)
1676 #define GRTLBIAS1 HW_REGISTER_RW(GR_TU_BASE1 + 0x1C)
1677
1678 #define GRTCFG2 HW_REGISTER_RW(GR_TU_BASE2 + 0x04)
1679 #define GRTDIM2 HW_REGISTER_RW(GR_TU_BASE2 + 0x08)
1680 #define GRTBCOL2 HW_REGISTER_RW(GR_TU_BASE2 + 0x0C)
1681 #define GRTLBIAS2 HW_REGISTER_RW(GR_TU_BASE2 + 0x1C)
1682
1683 #define GRTCFG3 HW_REGISTER_RW(GR_TU_BASE3 + 0x04)
1684 #define GRTDIM3 HW_REGISTER_RW(GR_TU_BASE3 + 0x08)
1685 #define GRTBCOL3 HW_REGISTER_RW(GR_TU_BASE3 + 0x0C)
1686 #define GRTLBIAS3 HW_REGISTER_RW(GR_TU_BASE3 + 0x1C)
1687
1688 /* 4 sets of context registers for physical texture unit 1 */
1689 #define GRTCFG4 HW_REGISTER_RW(GR_TU_BASE4 + 0x04)
1690 #define GRTDIM4 HW_REGISTER_RW(GR_TU_BASE4 + 0x08)
1691 #define GRTBCOL4 HW_REGISTER_RW(GR_TU_BASE4 + 0x0C)
1692 #define GRTLBIAS4 HW_REGISTER_RW(GR_TU_BASE4 + 0x1C)
1693
1694 #define GRTCFG5 HW_REGISTER_RW(GR_TU_BASE5 + 0x04)
1695 #define GRTDIM5 HW_REGISTER_RW(GR_TU_BASE5 + 0x08)
1696 #define GRTBCOL5 HW_REGISTER_RW(GR_TU_BASE5 + 0x0C)
1697 #define GRTLBIAS5 HW_REGISTER_RW(GR_TU_BASE5 + 0x1C)
1698
1699 #define GRTCFG6 HW_REGISTER_RW(GR_TU_BASE6 + 0x04)
1700 #define GRTDIM6 HW_REGISTER_RW(GR_TU_BASE6 + 0x08)
1701 #define GRTBCOL6 HW_REGISTER_RW(GR_TU_BASE6 + 0x0C)
1702 #define GRTLBIAS6 HW_REGISTER_RW(GR_TU_BASE6 + 0x1C)
1703
1704 #define GRTCFG7 HW_REGISTER_RW(GR_TU_BASE7 + 0x04)
1705 #define GRTDIM7 HW_REGISTER_RW(GR_TU_BASE7 + 0x08)
1706 #define GRTBCOL7 HW_REGISTER_RW(GR_TU_BASE7 + 0x0C)
1707 #define GRTLBIAS7 HW_REGISTER_RW(GR_TU_BASE7 + 0x1C)
1708
1709 /* TU debug registers */
1710 #define GRTDBG0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x00)
1711
1712 /* Extra registers per TU for child image support */
1713 #define GRTCOFF0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x04)
1714 #define GRTCDIM0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x08)
1715 #define GRTCOFF1 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x84)
1716 #define GRTCDIM1 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x88)
1717
1718
1719 /* System Registers */
1720 #define GR_SYSTEM_BASE 0x1A005000
1721
1722 #define GROCS HW_REGISTER_RW(GR_SYSTEM_BASE)
1723 #define GROCFG HW_REGISTER_RW(GR_SYSTEM_BASE + 4)
1724 #define GROIDC HW_REGISTER_RW(GR_SYSTEM_BASE + 8)
1725
1726 /* System debug register */
1727 #define GR_SYSTEM_DEBUG_BASE 0x1A005100
1728
1729 #define GRODBGA HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x000)
1730
1731 /* Performance Counters Regs */
1732 #define GROPCTRC HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x070)
1733 #define GROPCTRE HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x074)
1734
1735 #define GROPCTR0 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x080)
1736 #define GROPCTRS0 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x084)
1737 #define GROPCTR1 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x088)
1738 #define GROPCTRS1 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x08C)
1739 #define GROPCTR2 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x090)
1740 #define GROPCTRS2 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x094)
1741 #define GROPCTR3 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x098)
1742 #define GROPCTRS3 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x09C)
1743 #define GROPCTR4 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A0)
1744 #define GROPCTRS4 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A4)
1745 #define GROPCTR5 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A8)
1746 #define GROPCTRS5 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0AC)
1747 #define GROPCTR6 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B0)
1748 #define GROPCTRS6 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B4)
1749 #define GROPCTR7 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B8)
1750 #define GROPCTRS7 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0BC)
1751 #define GROPCTR8 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C0)
1752 #define GROPCTRS8 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C4)
1753 #define GROPCTR9 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C8)
1754 #define GROPCTRS9 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0CC)
1755 #define GROPCTR10 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D0)
1756 #define GROPCTRS10 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D4)
1757 #define GROPCTR11 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D8)
1758 #define GROPCTRS11 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0DC)
1759
1760 /* Performance Counters Defs */
1761
1762 #define GROPCTR_FOVCULLEDPRIMS 0x01
1763 #define GROPCTR_FOVCLIPPEDPRIMS 0x02
1764 #define GROPCTR_REVCULLEDPRIMS 0x03
1765 #define GROPCTR_NOFEPIXELPRIMS 0x04
1766 #define GROPCTR_FEVALIDPRIMS 0x05
1767 #define GROPCTR_FEZCULLEDQUADS 0x06
1768 #define GROPCTR_FEVALIDQUADS 0x07
1769 #define GROPCTR_FEINVALIDPIXELS 0x08
1770 #define GROPCTR_FEPEZRDY 0x09
1771 #define GROPCTR_FEPEZIDLE 0x0A
1772 #define GROPCTR_FESTALLPREFETCH 0x0B
1773 #define GROPCTR_FESPMRDY 0x0C
1774 #define GROPCTR_FESPMSTALL 0x0D
1775 #define GROPCTR_TU0_SAME_SET_STALL 0x0E
1776 #define GROPCTR_TU0_SAME_BANK_STALL 0x0F
1777 #define GROPCTR_TU0_AXI_REQ_FIFO_FULL 0x10
1778 #define GROPCTR_TU0_CACHE_ACCESSES 0x11
1779 #define GROPCTR_TU0_CACHE_STALLS 0x12
1780 #define GROPCTR_TU0_CACHE_REQ_STALLS 0x13
1781 #define GROPCTR_TU0_CACHE_MISSES 0x14
1782 #define GROPCTR_TU0_CACHE_RCV_WAITS 0x15
1783 #define GROPCTR_TU1_SAME_SET_STALL 0x16
1784 #define GROPCTR_TU1_SAME_BANK_STALL 0x17
1785 #define GROPCTR_TU1_AXI_REQ_FIFO_FULL 0x18
1786 #define GROPCTR_TU1_CACHE_ACCESSES 0x19
1787 #define GROPCTR_TU1_CACHE_STALLS 0x1A
1788 #define GROPCTR_TU1_CACHE_REQ_STALLS 0x1B
1789 #define GROPCTR_TU1_CACHE_MISSES 0x1C
1790 #define GROPCTR_TU1_CACHE_RCV_WAITS 0x1D
1791 #define GROPCTR_PBE_FE_STALLS 0x1E
1792 #define GROPCTR_PBE_DEPTH_TEST_FAIL 0x1F
1793 #define GROPCTR_PBE_STCL_TEST_FAIL 0x20
1794 #define GROPCTR_PBE_DPTH_STCL_PASS 0x21
1795 #define GROPCTR_FBC_CZ_CLRFLG_FETCHES 0x22
1796 #define GROPCTR_FBC_CZ_LINE_FLUSHES 0x23
1797 #define GROPCTR_FBC_CZ_PBE_REQS 0x24
1798 #define GROPCTR_FBC_CZ_PBE_STALLS 0x25
1799 #define GROPCTR_FBC_CZ_PBE_MISSES 0x26
1800 #define GROPCTR_FBC_CZ_PBE_HITS 0x27
1801 #define GROPCTR_FBC_CZ_FETCH_STALLS 0x28
1802 #define GROPCTR_FBC_CZ_FE_QUAD_REQS 0x29
1803 #define GROPCTR_FBC_CZ_FE_LINE_REQS 0x2A
1804 #define GROPCTR_FBC_CZ_FE_UNUSED 0x2B
1805 #define GROPCTR_FBC_CZ_FE_MISSES 0x2C
1806 #define GROPCTR_FBC_CZ_FE_HITS 0x2D
1807 #define GROPCTR_FBC_CZ_FE_DISCARDED 0x2E
1808 #define GROPCTR_FBC_CZ_UM_STALLS 0x2F
1809 #define GROPCTR_FBC_CZ_FETCHES 0x30
1810 #define GROPCTR_FBC_CZ_EVICTIONS 0x31
1811 #define GROPCTR_FBC_EZ_CLRFLG_FETCHES 0x32
1812 #define GROPCTR_FBC_EZ_LINE_FLUSHES 0x33
1813 #define GROPCTR_FBC_EZ_PBE_REQS 0x34
1814 #define GROPCTR_FBC_EZ_PBE_STALLS 0x35
1815 #define GROPCTR_FBC_EZ_PBE_MISSES 0x36
1816 #define GROPCTR_FBC_EZ_PBE_HITS 0x37
1817 #define GROPCTR_FBC_EZ_FETCH_STALLS 0x38
1818 #define GROPCTR_FBC_EZ_FE_REQS 0x39
1819 #define GROPCTR_FBC_EZ_FE_MISSES 0x3A
1820 #define GROPCTR_FBC_EZ_FE_HITS 0x3B
1821 #define GROPCTR_FBC_EZ_FE_FETCHES 0x3C
1822 #define GROPCTR_FBC_EZ_UM_STALLS 0x3D
1823 #define GROPCTR_FBC_EZ_FETCHES 0x3E
1824 #define GROPCTR_FBC_EZ_EVICTIONS 0x3F
1825
1826 //VRF defines
1827 #define VRF_SIZE (4096+64+64)
1828
1829 #endif /* _HARDWARE_VC4_H */
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