Begin UART0 integration
[rpi-open-firmware.git] / romstage.c
1 /*=============================================================================
2 Copyright (C) 2016 Kristina Brooks
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 VideoCoreIV first stage bootloader.
17
18 =============================================================================*/
19
20 #include <common.h>
21 #include <hardware.h>
22
23 uint32_t g_CPUID;
24
25 #define UART_DR (UART_BASE+0x00)
26 #define UART_RSRECR (UART_BASE+0x04)
27 #define UART_FR (UART_BASE+0x18)
28 #define UART_ILPR (UART_BASE+0x20)
29 #define UART_IBRD (UART_BASE+0x24)
30 #define UART_FBRD (UART_BASE+0x28)
31 #define UART_LCRH (UART_BASE+0x2C)
32 #define UART_CR (UART_BASE+0x30)
33 #define UART_IFLS (UART_BASE+0x34)
34 #define UART_IMSC (UART_BASE+0x38)
35 #define UART_RIS (UART_BASE+0x3C)
36 #define UART_MIS (UART_BASE+0x40)
37 #define UART_ICR (UART_BASE+0x44)
38 #define UART_DMACR (UART_BASE+0x48)
39 #define UART_ITCR (UART_BASE+0x80)
40 #define UART_ITIP (UART_BASE+0x84)
41 #define UART_ITOP (UART_BASE+0x88)
42 #define UART_TDR (UART_BASE+0x8C)
43
44 void uart_putc(unsigned int ch)
45 {
46 while(UART_MSR & 0x20) break;
47 UART_RBRTHRDLL = ch;
48 }
49
50 void uart_init(void) {
51 mmio_write32(UART_CR, 0);
52
53 unsigned int ra = GP_FSEL1;
54 ra &= ~(7 << 12);
55 ra |= 4 << 12;
56 GP_FSEL1 = ra;
57
58 GP_PUD = 0;
59
60 udelay(150);
61 GP_PUDCLK0 = (1 << 14) | (1 << 15);
62 udelay(150);
63 GP_PUDCLK0 = 0;
64
65 CM_UARTDIV = CM_PASSWORD | 42667;
66 CM_UARTCTL = CM_PASSWORD | CM_SRC_OSC | CM_UARTCTL_FRAC_SET | CM_UARTCTL_ENAB_SET;
67
68 mmio_write32(UART_ICR, 0x7FF);
69 mmio_write32(UART_IBRD, 1);
70 mmio_write32(UART_FBRD, 40);
71 mmio_write32(UART_LCRH, 0x70);
72 mmio_write32(UART_CR, 0x301);
73
74 for(;;) uart_putc('B');
75 }
76
77 void led_init(void) {
78 unsigned int ra;
79
80 ra = GP_FSEL1;
81 ra &= ~(7 << 18);
82 ra |= 1 << 18;
83
84 GP_FSEL1 = ra;
85 }
86
87 /*
88 #define CM_PLLC_DIGRST_BITS 9:9
89 #define CM_PLLC_DIGRST_SET 0x00000200
90 #define CM_PLLC_ANARST_BITS 8:8
91 #define CM_PLLC_ANARST_SET 0x00000100
92 #define CM_PLLC_HOLDPER_BITS 7:7
93 #define CM_PLLC_HOLDPER_SET 0x00000080
94 #define CM_PLLC_LOADPER_BITS 6:6
95 #define CM_PLLC_LOADPER_SET 0x00000040
96 #define CM_PLLC_HOLDCORE2_BITS 5:5
97 #define CM_PLLC_HOLDCORE2_SET 0x00000020
98 #define CM_PLLC_LOADCORE2_BITS 4:4
99 #define CM_PLLC_LOADCORE2_SET 0x00000010
100 #define CM_PLLC_HOLDCORE1_BITS 3:3
101 #define CM_PLLC_HOLDCORE1_SET 0x00000008
102 #define CM_PLLC_LOADCORE1_BITS 2:2
103 #define CM_PLLC_LOADCORE1_SET 0x00000004
104 #define CM_PLLC_HOLDCORE0_BITS 1:1
105 #define CM_PLLC_HOLDCORE0_SET 0x00000002
106 #define CM_PLLC_LOADCORE0_BITS 0:0
107 #define CM_PLLC_LOADCORE0_SET 0x00000001
108 */
109
110 void switch_vpu_to_pllc() {
111 A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_PLLCEN_SET;
112
113 A2W_PLLC_FRAC = A2W_PASSWORD | 87380;
114 A2W_PLLC_CTRL = A2W_PASSWORD | 52 | 0x1000;
115
116 A2W_PLLC_ANA3 = A2W_PASSWORD | 0x100;
117 A2W_PLLC_ANA2 = A2W_PASSWORD | 0x0;
118 A2W_PLLC_ANA1 = A2W_PASSWORD | 0x144000;
119 A2W_PLLC_ANA0 = A2W_PASSWORD | 0x0;
120
121 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET;
122
123 /* hold all */
124 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |
125 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |
126 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;
127
128 A2W_PLLC_DIG3 = A2W_PASSWORD | 0x0;
129 A2W_PLLC_DIG2 = A2W_PASSWORD | 0x400000;
130 A2W_PLLC_DIG1 = A2W_PASSWORD | 0x5;
131 A2W_PLLC_DIG0 = A2W_PASSWORD | 52 | 0x555000;
132
133 A2W_PLLC_CTRL = A2W_PASSWORD | 52 | 0x1000 | A2W_PLLC_CTRL_PRSTN_SET;
134
135 A2W_PLLC_DIG3 = A2W_PASSWORD | 0x42;
136 A2W_PLLC_DIG2 = A2W_PASSWORD | 0x500401;
137 A2W_PLLC_DIG1 = A2W_PASSWORD | 0x4005;
138 A2W_PLLC_DIG0 = A2W_PASSWORD | 52 | 0x555000;
139
140 A2W_PLLC_CORE0 = A2W_PASSWORD | 2;
141
142 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |
143 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |
144 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET | CM_PLLC_LOADCORE0_SET;
145
146 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |
147 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |
148 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;
149
150 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |
151 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |
152 CM_PLLC_HOLDCORE1_SET;
153
154 CM_VPUCTL = CM_PASSWORD | CM_VPUCTL_FRAC_SET | CM_SRC_OSC | CM_VPUCTL_GATE_SET;
155 CM_VPUDIV = CM_PASSWORD | (4 << 12);
156 CM_VPUCTL = CM_PASSWORD | CM_SRC_PLLC_CORE0 | CM_VPUCTL_GATE_SET;
157 CM_VPUCTL = CM_PASSWORD | CM_SRC_PLLC_CORE0 | CM_VPUCTL_GATE_SET | 0x10; /* ENAB */
158
159 CM_TIMERDIV = CM_PASSWORD | (19 << 12) | 819;
160 CM_TIMERCTL = CM_PASSWORD | CM_SRC_OSC | 0x10;
161 }
162
163 extern void sdram_init();
164 extern void arm_init();
165 extern void monitor_start();
166
167 void print_crap() {
168 printf("TB_BOOT_OPT = 0x%X\n", TB_BOOT_OPT);
169 }
170
171 int _main(unsigned int cpuid, unsigned int load_address) {
172 switch_vpu_to_pllc();
173
174 led_init();
175 uart_init();
176
177 printf(
178 "=========================================================\n"
179 "::\n"
180 ":: kFW for bcm2708, Copyright 2016, Kristina Brooks. \n"
181 "::\n"
182 ":: BUILDATE : %s %s \n"
183 ":: BUILDSTYLE: %s \n"
184 "::\n"
185 "=========================================================\n",
186 __DATE__, __TIME__,
187 "OPENSOURCE"
188 );
189
190 printf("CPUID = 0x%X\n", cpuid);
191 printf("LoadAddr = 0x%X\n", load_address);
192
193 print_crap();
194
195 g_CPUID = cpuid;
196
197 /* bring up SDRAM */
198 sdram_init();
199 printf("SDRAM initialization completed successfully!\n");
200
201 /* bring up ARM */
202 arm_init();
203
204 /* start vpu monitor */
205 monitor_start();
206
207 panic("main exiting!");
208 }
209
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