Et voila! Nous avons un UART!
[rpi-open-firmware.git] / romstage.c
1 /*=============================================================================
2 Copyright (C) 2016 Kristina Brooks
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 VideoCoreIV first stage bootloader.
17
18 =============================================================================*/
19
20 #include <common.h>
21 #include <hardware.h>
22
23 uint32_t g_CPUID;
24
25 #define UART_DR (UART_BASE+0x00)
26 #define UART_RSRECR (UART_BASE+0x04)
27 #define UART_FR (UART_BASE+0x18)
28 #define UART_ILPR (UART_BASE+0x20)
29 #define UART_IBRD (UART_BASE+0x24)
30 #define UART_FBRD (UART_BASE+0x28)
31 #define UART_LCRH (UART_BASE+0x2C)
32 #define UART_CR (UART_BASE+0x30)
33 #define UART_IFLS (UART_BASE+0x34)
34 #define UART_IMSC (UART_BASE+0x38)
35 #define UART_RIS (UART_BASE+0x3C)
36 #define UART_MIS (UART_BASE+0x40)
37 #define UART_ICR (UART_BASE+0x44)
38 #define UART_DMACR (UART_BASE+0x48)
39 #define UART_ITCR (UART_BASE+0x80)
40 #define UART_ITIP (UART_BASE+0x84)
41 #define UART_ITOP (UART_BASE+0x88)
42 #define UART_TDR (UART_BASE+0x8C)
43
44 void uart_putc(unsigned int ch)
45 {
46 while(UART_MSR & 0x20);
47 UART_RBRTHRDLL = ch;
48 }
49
50 void uart_init(void) {
51 unsigned int ra = GP_FSEL1;
52 ra &= ~(7 << 12);
53 ra |= 4 << 12;
54 GP_FSEL1 = ra;
55
56 /*
57 CM_UARTCTL = CM_PASSWORD | CM_SRC_OSC | CM_UARTCTL_FRAC_SET;
58 udelay(150);
59 CM_UARTDIV = CM_PASSWORD | 0x6666;
60 udelay(150);
61 CM_UARTCTL |= CM_UARTCTL_ENAB_SET;
62 udelay(150);*/
63
64 mmio_write32(UART_CR, 0);
65
66 GP_PUD = 0;
67 udelay(150);
68 GP_PUDCLK0 = (1 << 14) | (1 << 15);
69 udelay(150);
70 GP_PUDCLK0 = 0;
71
72 CM_UARTDIV = CM_PASSWORD | 0x6666;
73 CM_UARTCTL = CM_PASSWORD | CM_SRC_OSC | CM_UARTCTL_FRAC_SET | CM_UARTCTL_ENAB_SET;
74
75 mmio_write32(UART_ICR, 0x7FF);
76 mmio_write32(UART_IBRD, 1);
77 mmio_write32(UART_FBRD, 40);
78 mmio_write32(UART_LCRH, 0x70);
79 mmio_write32(UART_CR, 0x301);
80
81 // for(;;) uart_putc('B');
82 }
83
84 void led_init(void) {
85 unsigned int ra;
86
87 ra = GP_FSEL1;
88 ra &= ~(7 << 18);
89 ra |= 1 << 18;
90
91 GP_FSEL1 = ra;
92 }
93
94 /*
95 #define CM_PLLC_DIGRST_BITS 9:9
96 #define CM_PLLC_DIGRST_SET 0x00000200
97 #define CM_PLLC_ANARST_BITS 8:8
98 #define CM_PLLC_ANARST_SET 0x00000100
99 #define CM_PLLC_HOLDPER_BITS 7:7
100 #define CM_PLLC_HOLDPER_SET 0x00000080
101 #define CM_PLLC_LOADPER_BITS 6:6
102 #define CM_PLLC_LOADPER_SET 0x00000040
103 #define CM_PLLC_HOLDCORE2_BITS 5:5
104 #define CM_PLLC_HOLDCORE2_SET 0x00000020
105 #define CM_PLLC_LOADCORE2_BITS 4:4
106 #define CM_PLLC_LOADCORE2_SET 0x00000010
107 #define CM_PLLC_HOLDCORE1_BITS 3:3
108 #define CM_PLLC_HOLDCORE1_SET 0x00000008
109 #define CM_PLLC_LOADCORE1_BITS 2:2
110 #define CM_PLLC_LOADCORE1_SET 0x00000004
111 #define CM_PLLC_HOLDCORE0_BITS 1:1
112 #define CM_PLLC_HOLDCORE0_SET 0x00000002
113 #define CM_PLLC_LOADCORE0_BITS 0:0
114 #define CM_PLLC_LOADCORE0_SET 0x00000001
115 */
116
117 void switch_vpu_to_pllc() {
118 A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_PLLCEN_SET;
119
120 A2W_PLLC_FRAC = A2W_PASSWORD | 87380;
121 A2W_PLLC_CTRL = A2W_PASSWORD | 52 | 0x1000;
122
123 A2W_PLLC_ANA3 = A2W_PASSWORD | 0x100;
124 A2W_PLLC_ANA2 = A2W_PASSWORD | 0x0;
125 A2W_PLLC_ANA1 = A2W_PASSWORD | 0x144000;
126 A2W_PLLC_ANA0 = A2W_PASSWORD | 0x0;
127
128 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET;
129
130 /* hold all */
131 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |
132 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |
133 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;
134
135 A2W_PLLC_DIG3 = A2W_PASSWORD | 0x0;
136 A2W_PLLC_DIG2 = A2W_PASSWORD | 0x400000;
137 A2W_PLLC_DIG1 = A2W_PASSWORD | 0x5;
138 A2W_PLLC_DIG0 = A2W_PASSWORD | 52 | 0x555000;
139
140 A2W_PLLC_CTRL = A2W_PASSWORD | 52 | 0x1000 | A2W_PLLC_CTRL_PRSTN_SET;
141
142 A2W_PLLC_DIG3 = A2W_PASSWORD | 0x42;
143 A2W_PLLC_DIG2 = A2W_PASSWORD | 0x500401;
144 A2W_PLLC_DIG1 = A2W_PASSWORD | 0x4005;
145 A2W_PLLC_DIG0 = A2W_PASSWORD | 52 | 0x555000;
146
147 A2W_PLLC_CORE0 = A2W_PASSWORD | 2;
148
149 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |
150 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |
151 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET | CM_PLLC_LOADCORE0_SET;
152
153 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |
154 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |
155 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;
156
157 CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |
158 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |
159 CM_PLLC_HOLDCORE1_SET;
160
161 CM_VPUCTL = CM_PASSWORD | CM_VPUCTL_FRAC_SET | CM_SRC_OSC | CM_VPUCTL_GATE_SET;
162 CM_VPUDIV = CM_PASSWORD | (4 << 12);
163 CM_VPUCTL = CM_PASSWORD | CM_SRC_PLLC_CORE0 | CM_VPUCTL_GATE_SET;
164 CM_VPUCTL = CM_PASSWORD | CM_SRC_PLLC_CORE0 | CM_VPUCTL_GATE_SET | 0x10; /* ENAB */
165
166 CM_TIMERDIV = CM_PASSWORD | (19 << 12) | 819;
167 CM_TIMERCTL = CM_PASSWORD | CM_SRC_OSC | 0x10;
168 }
169
170 extern void sdram_init();
171 extern void arm_init();
172 extern void monitor_start();
173
174 void print_crap() {
175 printf("TB_BOOT_OPT = 0x%X\n", TB_BOOT_OPT);
176 }
177
178 int _main(unsigned int cpuid, unsigned int load_address) {
179 switch_vpu_to_pllc();
180
181 led_init();
182 uart_init();
183
184 for(;;) {
185 printf(
186 "=========================================================\n"
187 "::\n"
188 ":: kFW for bcm2708, Copyright 2016, Kristina Brooks. \n"
189 "::\n"
190 ":: BUILDATE : %s %s \n"
191 ":: BUILDSTYLE: %s \n"
192 "::\n"
193 "=========================================================\n",
194 __DATE__, __TIME__,
195 "OPENSOURCE"
196 );
197 }
198
199 printf("CPUID = 0x%X\n", cpuid);
200 printf("LoadAddr = 0x%X\n", load_address);
201
202 print_crap();
203
204 g_CPUID = cpuid;
205
206 /* bring up SDRAM */
207 sdram_init();
208 printf("SDRAM initialization completed successfully!\n");
209
210 /* bring up ARM */
211 arm_init();
212
213 /* start vpu monitor */
214 monitor_start();
215
216 panic("main exiting!");
217 }
218
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