misc cleanup
[rpi-open-firmware.git] / sdram.c
1 /*=============================================================================
2 Copyright (C) 2016-2017 Authors of rpi-open-firmware
3 Copyright (C) 2016 Julian Brown
4 All rights reserved.
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 FILE DESCRIPTION
17 VideoCoreIV SDRAM initialization code.
18
19 =============================================================================*/
20
21 #include <lib/runtime.h>
22 #include <hardware.h>
23
24 /*
25 Registers
26 =========
27
28 SC: AC Timing (Page 202)
29 SB: ???
30 SD: AC Timing (Page 202)
31 SE: AC Timing (Page 202)
32
33 PT1:
34 Minimum Idle time after first CKE assertion
35 Minimum CKE low time after completion of power ramp
36 PT2:
37 DAI Duration
38 */
39
40 extern uint32_t g_CPUID;
41
42 #define MR_REQUEST_SUCCESS(x) ((SD_MR_TIMEOUT_SET & x) != SD_MR_TIMEOUT_SET)
43 #define MR_GET_RDATA(x) ((x & SD_MR_RDATA_SET) >> SD_MR_RDATA_LSB)
44
45 #define SIP_DEBUG(x) x
46 #define SCLKU_DEBUG(x) //SIP_DEBUG(x)
47
48 #define BIST_pvt 0x20
49 #define BIST_reset 0x10
50
51 #define PVT_calibrate_request 0x1
52
53 #define logf(fmt, ...) printf("[SDRAM:%s]: " fmt, __FUNCTION__, ##__VA_ARGS__);
54
55 uint32_t g_RAMSize = RAM_SIZE_UNKNOWN;
56
57 #define MR8_DENSITY_SHIFT 0x2
58 #define MR8_DENSITY_MASK (0xF << 0x2)
59
60 static unsigned lpddr2_size(uint32_t mr) {
61 switch (mr) {
62 case 0x58:
63 return RAM_SIZE_1GB;
64 case 0x18:
65 return RAM_SIZE_512MB;
66 case 0x14:
67 return RAM_SIZE_256MB;
68 case 0x10:
69 return RAM_SIZE_128MB;
70 default:
71 return RAM_SIZE_UNKNOWN;
72 }
73 }
74
75 const char* size_to_string[] = {
76 "1GB",
77 "512MB",
78 "256MB",
79 "128MB",
80 "UNKNOWN"
81 };
82
83 /*****************************************************************************
84 * Guts
85 *****************************************************************************/
86
87 ALWAYS_INLINE inline void clkman_update_begin() {
88 CM_SDCCTL |= CM_PASSWORD | CM_SDCCTL_UPDATE_SET;
89 SCLKU_DEBUG(logf("waiting for ACCPT (%X) ...\n", CM_SDCCTL));
90 for (;;) if (CM_SDCCTL & CM_SDCCTL_ACCPT_SET) break;
91 SCLKU_DEBUG(logf("ACCPT received! (%X)\n", CM_SDCCTL));
92 }
93
94 ALWAYS_INLINE inline void clkman_update_end() {
95 CM_SDCCTL = CM_PASSWORD | (CM_SDCCTL & CM_SDCCTL_UPDATE_CLR);
96 SCLKU_DEBUG(logf("waiting for ACCPT clear (%X) ...\n", CM_SDCCTL));
97 for (;;) if ((CM_SDCCTL & CM_SDCCTL_ACCPT_SET) == 0) break;
98 SCLKU_DEBUG(logf("ACCPT cleared! (%X)\n", CM_SDCCTL));
99 }
100
101 ALWAYS_INLINE void reset_phy_dll() {
102 SIP_DEBUG(logf("resetting aphy and dphy dlls ...\n", __FUNCTION__));
103
104 /* politely tell sdc that we'll be messing with address lines */
105 APHY_CSR_PHY_BIST_CNTRL_SPR = 0x30;
106
107 DPHY_CSR_GLBL_DQ_DLL_RESET = 0x1;
108 APHY_CSR_GLBL_ADDR_DLL_RESET = 0x1;
109
110 /* stall ... */
111 SD_CS;
112 SD_CS;
113 SD_CS;
114 SD_CS;
115
116 DPHY_CSR_GLBL_DQ_DLL_RESET = 0x0;
117 APHY_CSR_GLBL_ADDR_DLL_RESET = 0x0;
118
119 SIP_DEBUG(logf("waiting for dphy master dll to lock ...\n", __FUNCTION__));
120 for (;;) if ((DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT & 0xFFFF) == 0xFFFF) break;
121 SIP_DEBUG(logf("dphy master dll locked!\n", __FUNCTION__));
122 }
123
124 typedef struct {
125 uint32_t max_freq;
126 uint32_t RL;
127 uint32_t tRPab;
128 uint32_t tRPpb;
129 uint32_t tRCD;
130 uint32_t tWR;
131 uint32_t tRASmin;
132 uint32_t tRRD;
133 uint32_t tWTR;
134 uint32_t tXSR;
135 uint32_t tXP;
136 uint32_t tRFCab;
137 uint32_t tRTP;
138 uint32_t tCKE;
139 uint32_t tCKESR;
140 uint32_t tDQSCKMAXx2;
141 uint32_t tRASmax;
142 uint32_t tFAW;
143 uint32_t tRC;
144 uint32_t tREFI;
145
146 uint32_t tINIT1;
147 uint32_t tINIT3;
148 uint32_t tINIT5;
149
150 uint32_t rowbits;
151 uint32_t colbits;
152 uint32_t banklow;
153 } lpddr2_timings_t;
154
155 // 7.8 / (1.0 / 400)
156
157 lpddr2_timings_t g_InitSdramParameters = {
158 /* SA (us) */
159 .tREFI = 3113, //Refresh rate: 3113 * (1.0 / 400) = 7.78us
160 /* SC (ns) */
161 .tRFCab = 50,
162 .tRRD = 2,
163 .tWR = 7,
164 .tWTR = 4,
165 /* SD (ns) */
166 .tRPab = 7,
167 .tRC = 24,
168 .tXP = 1,
169 .tRASmin = 15,
170 .tRPpb = 6,
171 .tRCD = 6,
172 /* SE (ns) */
173 .tFAW = 18,
174 .tRTP = 1,
175 .tXSR = 54,
176 /* PT */
177 .tINIT1 = 40, // Minimum CKE low time after completion of power ramp: 40 * (1.0 / 0.4) = 100ns
178 .tINIT3 = 79800, // Minimum Idle time after first CKE assertion: 79800 * (1.0 / 400) = 199.5us ~ 200us
179 .tINIT5 = 3990, //Max DAI: 3990* (1.0 / 400) = 9.9us ~ 10us
180 /* SB */
181 .rowbits = 2,
182 .colbits = 1,
183 .banklow = 2
184 };
185
186 void reset_with_timing(lpddr2_timings_t* T) {
187 uint32_t ctrl = 0x4;
188
189 SD_CS = (SD_CS & ~(SD_CS_DEL_KEEP_SET|SD_CS_DPD_SET|SD_CS_RESTRT_SET)) | SD_CS_STBY_SET;
190
191 /* wait for SDRAM controller to go down */
192 SIP_DEBUG(logf("waiting for SDRAM controller to go down (%X) ...\n", SD_CS));
193 for (;;) if ((SD_CS & SD_CS_SDUP_SET) == 0) break;
194 SIP_DEBUG(logf("SDRAM controller down!\n"));
195
196 /* disable SDRAM clock */
197 clkman_update_begin();
198 CM_SDCCTL = (CM_SDCCTL & ~(CM_SDCCTL_ENAB_SET|CM_SDCCTL_CTRL_SET)) | CM_PASSWORD;
199 clkman_update_end();
200
201 SIP_DEBUG(logf("SDRAM clock disabled!\n"));
202
203 /*
204 * Migrate over to master PLL.
205 */
206
207 APHY_CSR_DDR_PLL_PWRDWN = 0;
208 APHY_CSR_DDR_PLL_GLOBAL_RESET = 0;
209 APHY_CSR_DDR_PLL_POST_DIV_RESET = 0;
210
211 /* 400MHz */
212 APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0 = (1 << 16) | 0x53;
213 APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1 = 0;
214 APHY_CSR_DDR_PLL_MDIV_VALUE = 0;
215
216 APHY_CSR_DDR_PLL_GLOBAL_RESET = 1;
217
218 SIP_DEBUG(logf("waiting for master ddr pll to lock ...\n"));
219 for (;;) if (APHY_CSR_DDR_PLL_LOCK_STATUS & (1 << 16)) break;
220 SIP_DEBUG(logf("master ddr pll locked!\n"));
221
222 APHY_CSR_DDR_PLL_POST_DIV_RESET = 1;
223
224 clkman_update_begin();
225 CM_SDCCTL = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (CM_SDCCTL & CM_SDCCTL_CTRL_CLR);
226 clkman_update_end();
227
228 SD_SA =
229 (T->tREFI << SD_SA_RFSH_T_LSB)
230 | SD_SA_PGEHLDE_SET
231 | SD_SA_CLKSTOP_SET
232 | SD_SA_POWSAVE_SET
233 | 0x3214;
234
235 SD_SB =
236 SD_SB_REORDER_SET
237 | (T->banklow << SD_SB_BANKLOW_LSB)
238 | SD_SB_EIGHTBANK_SET
239 | (T->rowbits << SD_SB_ROWBITS_LSB)
240 | (T->colbits << SD_SB_COLBITS_LSB);
241
242 logf("SDRAM Addressing Mode: Bank=%d Row=%d Col=%d SB=0x%X\n", T->banklow, T->rowbits, T->colbits, SD_SB);
243
244 SD_SC =
245 (T->tRFCab << SD_SC_T_RFC_LSB)
246 | (T->tRRD << SD_SC_T_RRD_LSB)
247 | (T->tWR << SD_SC_T_WR_LSB)
248 | (T->tWTR << SD_SC_T_WTR_LSB)
249 | (3 << SD_SC_WL_LSB);
250
251 SD_SD =
252 (T->tRPab << SD_SD_T_RPab_LSB)
253 | (T->tRC << SD_SD_T_RC_LSB)
254 | (T->tXP << SD_SD_T_XP_LSB)
255 | (T->tRASmin << SD_SD_T_RAS_LSB)
256 | (T->tRPpb << SD_SD_T_RPpb_LSB)
257 | (T->tRCD << SD_SD_T_RCD_LSB);
258
259 SD_SE =
260 (1 << SD_SE_RL_EN_LSB)
261 | (4 << SD_SE_RL_LSB)
262 | (T->tFAW << SD_SE_T_FAW_LSB)
263 | (T->tRTP << SD_SE_T_RTP_LSB)
264 | (T->tXSR << SD_SE_T_XSR_LSB);
265
266 SD_PT1 =
267 (T->tINIT3 << SD_PT1_T_INIT3_LSB)
268 | (T->tINIT1 << SD_PT1_T_INIT1_LSB);
269
270 SD_PT2 =
271 T->tINIT5 << SD_PT2_T_INIT5_LSB;
272
273 SD_MRT =
274 0x3 << SD_MRT_T_MRW_LSB;
275
276 reset_phy_dll();
277
278 /* wait for address line pll to come back */
279 SIP_DEBUG(logf("waiting for address dll to lock ...\n"));
280 for (;;) if (APHY_CSR_GLBL_ADR_DLL_LOCK_STAT == 3) break;
281 SIP_DEBUG(logf("address dll locked!\n"));
282
283 /* tell sdc we're done messing with address lines */
284 APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0;
285
286 /* woo, turn on sdram! */
287 SD_CS =
288 (((4 << SD_CS_ASHDN_T_LSB)
289 | SD_CS_STATEN_SET
290 | SD_CS_EN_SET)
291 & ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET;
292 }
293
294 unsigned int read_mr(unsigned int addr) {
295 while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
296 SD_MR = addr & 0xFF;
297 unsigned int mrr;
298 while (((mrr = SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
299 return mrr;
300 }
301
302 unsigned int write_mr(unsigned int addr, unsigned int data, bool wait) {
303 while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
304
305 SD_MR = (addr & 0xFF) | ((data & 0xFF) << 8) | SD_MR_RW_SET;
306
307 if (wait) {
308 unsigned int mrr;
309 while (((mrr = SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
310
311 if (mrr & SD_MR_TIMEOUT_SET)
312 panic("MR write timed out (addr=%d data=0x%X)", addr, data);
313
314 return mrr;
315 } else {
316 return 0;
317 }
318 }
319
320 void reset_phy() {
321 logf("%s: resetting SDRAM PHY ...\n", __FUNCTION__);
322
323 /* reset PHYC */
324 SD_PHYC = SD_PHYC_PHYRST_SET;
325 udelay(64);
326 SD_PHYC = 0;
327
328 logf("%s: resetting DPHY CTRL ...\n", __FUNCTION__);
329
330 DPHY_CSR_DQ_PHY_MISC_CTRL = 0x7;
331 DPHY_CSR_DQ_PAD_MISC_CTRL = 0x0;
332 DPHY_CSR_BOOT_READ_DQS_GATE_CTRL = 0x11;
333
334 reset_phy_dll();
335
336 APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0;
337 }
338
339 static void switch_to_cprman_clock(unsigned int source, unsigned int div) {
340 CM_SDCDIV = CM_PASSWORD | (div << CM_SDCDIV_DIV_LSB);
341 CM_SDCCTL = CM_PASSWORD | (CM_SDCCTL & CM_SDCCTL_SRC_CLR) | source;
342 CM_SDCCTL |= CM_PASSWORD | CM_SDCCTL_ENAB_SET;
343
344 logf("switching sdram to cprman clock (src=%d, div=%d), waiting for busy (%X) ...\n", source, div, CM_SDCCTL);
345
346 for (;;) if (CM_SDCCTL & CM_SDCCTL_BUSY_SET) break;
347
348 logf("busy set, switch complete!\n");
349 }
350
351 static void init_clkman() {
352 uint32_t ctrl = 0;
353
354 clkman_update_begin();
355 CM_SDCCTL = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (CM_SDCCTL & CM_SDCCTL_CTRL_CLR);
356 clkman_update_end();
357 }
358
359 #define CALL_INIT_CLKMAN init_clkman();
360
361
362 /*****************************************************************************
363 * Calibration
364 *****************************************************************************/
365
366 static void calibrate_pvt_early() {
367 /* some hw revisions require different slews */
368 bool st = ((g_CPUID >> 4) & 0xFFF) == 0x14;
369 uint32_t dq_slew = (st ? 2 : 3);
370
371 /* i don't get it, the spec says do not use this register */
372 write_mr(0xFF, 0, true);
373 /* RL = 6 / WL = 3 */
374 write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, true);
375
376 APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL = 0x333;
377 DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = (dq_slew << 8) | (dq_slew << 4) | 3;
378
379 logf("DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = 0x%X\n", DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL);
380
381 /* tell sdc we want to calibrate */
382 APHY_CSR_PHY_BIST_CNTRL_SPR = BIST_pvt;
383
384 /* pvt compensation */
385 APHY_CSR_ADDR_PVT_COMP_CTRL = PVT_calibrate_request;
386 logf("waiting for address PVT calibration ...\n");
387 for (;;) if (APHY_CSR_ADDR_PVT_COMP_STATUS & 2) break;
388
389 DPHY_CSR_DQ_PVT_COMP_CTRL = PVT_calibrate_request;
390 logf("waiting for data PVT calibration ...\n");
391 for (;;) if (DPHY_CSR_DQ_PVT_COMP_STATUS & 2) break;
392
393 /* tell sdc we're done calibrating */
394 APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0;
395
396 /* send calibration command */
397 uint32_t old_mrt = SD_MRT;
398 SD_MRT = 20;
399 logf("waiting for SDRAM calibration command ...\n");
400 SD_MR = LPDDR2_MR_CALIBRATION | (0xFF << 8) | SD_MR_RW_SET | SD_MR_HI_Z_SET;
401 while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
402 SD_MRT = old_mrt;
403
404 write_mr(LPDDR2_MR_IO_CONFIG, st ? 3 : 2, false);
405 }
406
407
408 /*****************************************************************************
409 * Late init
410 *****************************************************************************/
411
412 static void init_late() {
413 }
414
415 /*****************************************************************************
416 * Self-test
417 *****************************************************************************/
418
419 #define RT_BASE 0xC0000000
420
421 #define RT_PAT0 0xAAAAAAAA
422 #define RT_PAT1 0xFF00AA00
423 #define RT_PAT2 0x99999999
424
425 #define RT_ASSERT(i_, expected) \
426 if (ram[(i_)] != expected) { \
427 logf("ERROR: At 0x%X, was expecting 0x%X from read, got 0x%X instead!\n", \
428 (uint32_t)&ram[(i_)], \
429 expected, \
430 ram[(i_)]); \
431 panic("SDRAM self test failed!"); \
432 }
433
434 static void selftest_at(uint32_t addr) {
435 volatile uint32_t* ram = (volatile uint32_t*)addr;
436
437 logf("Testing region at 0x%X ...\n", addr);
438
439 for (int i = 0; i < 0x1000; i += 4) {
440 ram[i] = RT_PAT0;
441 ram[i + 1] = RT_PAT1;
442 ram[i + 2] = RT_PAT2;
443 ram[i + 3] = RT_PAT0;
444 }
445
446 for (int i = 0; i < 0x1000; i += 4) {
447 RT_ASSERT(i, RT_PAT0);
448 RT_ASSERT(i + 1, RT_PAT1);
449 RT_ASSERT(i + 2, RT_PAT2);
450 RT_ASSERT(i + 3, RT_PAT0);
451 }
452 }
453
454 static void selftest() {
455 logf("Starting self test ...\n");
456
457 selftest_at(RT_BASE);
458
459 if (g_RAMSize == RAM_SIZE_256MB || g_RAMSize == RAM_SIZE_512MB || g_RAMSize == RAM_SIZE_1GB) {
460 selftest_at(RT_BASE + 0xFF00000);
461 }
462 if (g_RAMSize == RAM_SIZE_512MB || g_RAMSize == RAM_SIZE_1GB) {
463 selftest_at(RT_BASE + 0x1FF00000);
464 }
465 if (g_RAMSize == RAM_SIZE_1GB) {
466 selftest_at(RT_BASE + 0x2FF00000);
467 selftest_at(RT_BASE + 0x3FF00000);
468 }
469
470 logf("Self test successful!\n");
471 }
472
473 #undef RT_ASSERT
474
475 void sdram_init() {
476 uint32_t vendor_id, bc;
477
478 logf("(0) SD_CS = 0x%X\n", SD_CS);
479
480 PM_SMPS = PM_PASSWORD | 0x1;
481 A2W_SMPS_LDO1 = A2W_PASSWORD | 0x40000;
482 A2W_SMPS_LDO0 = A2W_PASSWORD | 0x0;
483
484 A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_DDREN_SET;
485
486 /*
487 * STEP 1:
488 * configure the low-frequency PLL and enable SDC and perform
489 * the calibration sequence.
490 */
491
492 switch_to_cprman_clock(CM_SRC_OSC, 1);
493
494 CALL_INIT_CLKMAN;
495
496 reset_phy();
497
498 /* magic values */
499 SD_SA = 0x006E3395;
500 SD_SB = 0x0F9;
501 SD_SC = 0x6000431;
502 SD_SD = 0x10000011;
503 SD_SE = 0x10106000;
504 SD_PT1 = 0x0AF002;
505 SD_PT2 = 0x8C;
506 SD_MRT = 0x3;
507 SD_CS = 0x200042;
508
509 /* wait for SDRAM controller */
510 logf("waiting for SDUP (%X) ...\n", SD_CS);
511 for (;;) if (SD_CS & SD_CS_SDUP_SET) break;
512 logf("SDRAM controller has arrived! (%X)\n", SD_CS);
513
514 /* RL = 6 / WL = 3 */
515 write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, false);
516 calibrate_pvt_early();
517
518 /* identify installed memory */
519 vendor_id = read_mr(LPDDR2_MR_MANUFACTURER_ID);
520 if (!MR_REQUEST_SUCCESS(vendor_id)) {
521 panic("vendor id memory register read timed out");
522 }
523 vendor_id = MR_GET_RDATA(vendor_id);
524
525 bc = read_mr(LPDDR2_MR_METRICS);
526 if (!MR_REQUEST_SUCCESS(bc)) {
527 panic("basic configuration memory register read timed out");
528 }
529 bc = MR_GET_RDATA(bc);
530
531 g_RAMSize = lpddr2_size(bc);
532
533 logf("SDRAM Type: %s LPDDR2 (BC=0x%X, vendor %d)\n",
534 size_to_string[g_RAMSize],
535 bc,
536 vendor_id);
537
538 if (g_RAMSize == RAM_SIZE_UNKNOWN)
539 panic("unknown ram size (MR8 response was 0x%X)", bc);
540
541 /*
542 * STEP 2:
543 * after calibration, enable high-freq SDRAM PLL. because we're
544 * running from cache, we can freely mess with SDRAM clock without
545 * any issues, removing the need to copy the SDRAM late init stuff
546 * to bootrom ram. if later code that's running from SDRAM wants to
547 * mess with SDRAM clock it would need to do that.
548 */
549
550 if (g_RAMSize == RAM_SIZE_1GB) {
551 g_InitSdramParameters.colbits = 3;
552 g_InitSdramParameters.rowbits = 3;
553 g_InitSdramParameters.banklow = 3;
554 } else if (g_RAMSize == RAM_SIZE_512MB) {
555 g_InitSdramParameters.colbits = 2;
556 }
557
558 reset_with_timing(&g_InitSdramParameters);
559 init_late();
560 selftest();
561 }
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