1f7df8979049151aba95af0454915d46fda325b6
[rpi-open-firmware.git] / sdram.c
1 /*=============================================================================
2 Copyright (C) 2016-2017 Authors of rpi-open-firmware
3 Copyright (C) 2016 Julian Brown
4 All rights reserved.
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 FILE DESCRIPTION
17 VideoCoreIV SDRAM initialization code.
18
19 =============================================================================*/
20
21 #include <lib/runtime.h>
22 #include <hardware.h>
23
24 /*
25 Registers
26 =========
27
28 SC: AC Timing (Page 202)
29 SB: ???
30 SD: AC Timing (Page 202)
31 SE: AC Timing (Page 202)
32
33 PT1:
34 Minimum Idle time after first CKE assertion
35 Minimum CKE low time after completion of power ramp
36 PT2:
37 DAI Duration
38 */
39
40 extern uint32_t g_CPUID;
41
42 #define MR_REQUEST_SUCCESS(x) ((SD_MR_TIMEOUT_SET & x) != SD_MR_TIMEOUT_SET)
43 #define MR_GET_RDATA(x) ((x & SD_MR_RDATA_SET) >> SD_MR_RDATA_LSB)
44
45 #define SIP_DEBUG(x) x
46 #define SCLKU_DEBUG(x) //SIP_DEBUG(x)
47
48 #define BIST_pvt 0x20
49 #define BIST_reset 0x10
50
51 #define PVT_calibrate_request 0x1
52
53 #define logf(fmt, ...) printf("[SDRAM:%s]: " fmt, __FUNCTION__, ##__VA_ARGS__);
54
55 unsigned g_RAMSize = RAM_SIZE_UNKNOWN;
56
57 static const char* lpddr2_manufacturer_name(uint32_t mr) {
58 switch (mr) {
59 case 1: return "Samsung";
60 case 2: return "Qimonda";
61 case 3: return "Elpida";
62 case 4: return "Etron";
63 case 5: return "Nanya";
64 case 6: return "Hynix";
65 default: return "Unknown";
66 }
67 }
68
69 #define MR8_DENSITY_SHIFT 0x2
70 #define MR8_DENSITY_MASK (0xF << 0x2)
71
72 static unsigned lpddr2_size(uint32_t mr) {
73 switch (mr) {
74 case 0x58: return RAM_SIZE_1GB;
75 case 0x18: return RAM_SIZE_512MB;
76 case 0x14: return RAM_SIZE_256MB;
77 case 0x10: return RAM_SIZE_128MB;
78 default: return RAM_SIZE_UNKNOWN;
79 }
80 }
81
82 const char* size_to_string[] = {
83 "1GB",
84 "512MB",
85 "256MB",
86 "128MB",
87 "UNKNOWN"
88 };
89
90 /*****************************************************************************
91 * Guts
92 *****************************************************************************/
93
94 ALWAYS_INLINE inline void clkman_update_begin() {
95 CM_SDCCTL |= CM_PASSWORD | CM_SDCCTL_UPDATE_SET;
96 SCLKU_DEBUG(logf("waiting for ACCPT (%X) ...\n", CM_SDCCTL));
97 for (;;) if (CM_SDCCTL & CM_SDCCTL_ACCPT_SET) break;
98 SCLKU_DEBUG(logf("ACCPT received! (%X)\n", CM_SDCCTL));
99 }
100
101 ALWAYS_INLINE inline void clkman_update_end() {
102 CM_SDCCTL = CM_PASSWORD | (CM_SDCCTL & CM_SDCCTL_UPDATE_CLR);
103 SCLKU_DEBUG(logf("waiting for ACCPT clear (%X) ...\n", CM_SDCCTL));
104 for (;;) if ((CM_SDCCTL & CM_SDCCTL_ACCPT_SET) == 0) break;
105 SCLKU_DEBUG(logf("ACCPT cleared! (%X)\n", CM_SDCCTL));
106 }
107
108 ALWAYS_INLINE void reset_phy_dll() {
109 SIP_DEBUG(logf("resetting aphy and dphy dlls ...\n", __FUNCTION__));
110
111 /* politely tell sdc that we'll be messing with address lines */
112 APHY_CSR_PHY_BIST_CNTRL_SPR = 0x30;
113
114 DPHY_CSR_GLBL_DQ_DLL_RESET = 0x1;
115 APHY_CSR_GLBL_ADDR_DLL_RESET = 0x1;
116
117 /* stall ... */
118 SD_CS;
119 SD_CS;
120 SD_CS;
121 SD_CS;
122
123 DPHY_CSR_GLBL_DQ_DLL_RESET = 0x0;
124 APHY_CSR_GLBL_ADDR_DLL_RESET = 0x0;
125
126 SIP_DEBUG(logf("waiting for dphy master dll to lock ...\n", __FUNCTION__));
127 for (;;) if ((DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT & 0xFFFF) == 0xFFFF) break;
128 SIP_DEBUG(logf("dphy master dll locked!\n", __FUNCTION__));
129 }
130
131 typedef struct {
132 uint32_t max_freq;
133 uint32_t RL;
134 uint32_t tRPab;
135 uint32_t tRPpb;
136 uint32_t tRCD;
137 uint32_t tWR;
138 uint32_t tRASmin;
139 uint32_t tRRD;
140 uint32_t tWTR;
141 uint32_t tXSR;
142 uint32_t tXP;
143 uint32_t tRFCab;
144 uint32_t tRTP;
145 uint32_t tCKE;
146 uint32_t tCKESR;
147 uint32_t tDQSCKMAXx2;
148 uint32_t tRASmax;
149 uint32_t tFAW;
150 uint32_t tRC;
151 uint32_t tREFI;
152
153 uint32_t tINIT1;
154 uint32_t tINIT3;
155 uint32_t tINIT5;
156
157 uint32_t rowbits;
158 uint32_t colbits;
159 uint32_t banklow;
160 } lpddr2_timings_t;
161
162 // 7.8 / (1.0 / 400)
163
164 lpddr2_timings_t g_InitSdramParameters = {
165 /* SA (us) */
166 .tREFI = 3113, //Refresh rate: 3113 * (1.0 / 400) = 7.78us
167 /* SC (ns) */
168 .tRFCab = 50,
169 .tRRD = 2,
170 .tWR = 7,
171 .tWTR = 4,
172 /* SD (ns) */
173 .tRPab = 7,
174 .tRC = 24,
175 .tXP = 1,
176 .tRASmin = 15,
177 .tRPpb = 6,
178 .tRCD = 6,
179 /* SE (ns) */
180 .tFAW = 18,
181 .tRTP = 1,
182 .tXSR = 54,
183 /* PT */
184 .tINIT1 = 40, // Minimum CKE low time after completion of power ramp: 40 * (1.0 / 0.4) = 100ns
185 .tINIT3 = 79800, // Minimum Idle time after first CKE assertion: 79800 * (1.0 / 400) = 199.5us ~ 200us
186 .tINIT5 = 3990, //Max DAI: 3990* (1.0 / 400) = 9.9us ~ 10us
187 /* SB */
188 .rowbits = 2,
189 .colbits = 1,
190 .banklow = 2
191 };
192
193 void reset_with_timing(lpddr2_timings_t* T) {
194 uint32_t ctrl = 0x4;
195
196 SD_CS = (SD_CS & ~(SD_CS_DEL_KEEP_SET|SD_CS_DPD_SET|SD_CS_RESTRT_SET)) | SD_CS_STBY_SET;
197
198 /* wait for SDRAM controller to go down */
199 SIP_DEBUG(logf("waiting for SDRAM controller to go down (%X) ...\n", SD_CS));
200 for (;;) if ((SD_CS & SD_CS_SDUP_SET) == 0) break;
201 SIP_DEBUG(logf("SDRAM controller down!\n"));
202
203 /* disable SDRAM clock */
204 clkman_update_begin();
205 CM_SDCCTL = (CM_SDCCTL & ~(CM_SDCCTL_ENAB_SET|CM_SDCCTL_CTRL_SET)) | CM_PASSWORD;
206 clkman_update_end();
207
208 SIP_DEBUG(logf("SDRAM clock disabled!\n"));
209
210 /*
211 * Migrate over to master PLL.
212 */
213
214 APHY_CSR_DDR_PLL_PWRDWN = 0;
215 APHY_CSR_DDR_PLL_GLOBAL_RESET = 0;
216 APHY_CSR_DDR_PLL_POST_DIV_RESET = 0;
217
218 /* 400MHz */
219 APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0 = (1 << 16) | 0x53;
220 APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1 = 0;
221 APHY_CSR_DDR_PLL_MDIV_VALUE = 0;
222
223 APHY_CSR_DDR_PLL_GLOBAL_RESET = 1;
224
225 SIP_DEBUG(logf("waiting for master ddr pll to lock ...\n"));
226 for (;;) if (APHY_CSR_DDR_PLL_LOCK_STATUS & (1 << 16)) break;
227 SIP_DEBUG(logf("master ddr pll locked!\n"));
228
229 APHY_CSR_DDR_PLL_POST_DIV_RESET = 1;
230
231 clkman_update_begin();
232 CM_SDCCTL = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (CM_SDCCTL & CM_SDCCTL_CTRL_CLR);
233 clkman_update_end();
234
235 SD_SA =
236 (T->tREFI << SD_SA_RFSH_T_LSB)
237 | SD_SA_PGEHLDE_SET
238 | SD_SA_CLKSTOP_SET
239 | SD_SA_POWSAVE_SET
240 | 0x3214;
241
242 SD_SB =
243 SD_SB_REORDER_SET
244 | (T->banklow << SD_SB_BANKLOW_LSB)
245 | SD_SB_EIGHTBANK_SET
246 | (T->rowbits << SD_SB_ROWBITS_LSB)
247 | (T->colbits << SD_SB_COLBITS_LSB);
248
249 logf("SDRAM Addressing Mode: Bank=%d Row=%d Col=%d SB=0x%X\n", T->banklow, T->rowbits, T->colbits, SD_SB);
250
251 SD_SC =
252 (T->tRFCab << SD_SC_T_RFC_LSB)
253 | (T->tRRD << SD_SC_T_RRD_LSB)
254 | (T->tWR << SD_SC_T_WR_LSB)
255 | (T->tWTR << SD_SC_T_WTR_LSB)
256 | (3 << SD_SC_WL_LSB);
257
258 SD_SD =
259 (T->tRPab << SD_SD_T_RPab_LSB)
260 | (T->tRC << SD_SD_T_RC_LSB)
261 | (T->tXP << SD_SD_T_XP_LSB)
262 | (T->tRASmin << SD_SD_T_RAS_LSB)
263 | (T->tRPpb << SD_SD_T_RPpb_LSB)
264 | (T->tRCD << SD_SD_T_RCD_LSB);
265
266 SD_SE =
267 (1 << SD_SE_RL_EN_LSB)
268 | (4 << SD_SE_RL_LSB)
269 | (T->tFAW << SD_SE_T_FAW_LSB)
270 | (T->tRTP << SD_SE_T_RTP_LSB)
271 | (T->tXSR << SD_SE_T_XSR_LSB);
272
273 SD_PT1 =
274 (T->tINIT3 << SD_PT1_T_INIT3_LSB)
275 | (T->tINIT1 << SD_PT1_T_INIT1_LSB);
276
277 SD_PT2 =
278 T->tINIT5 << SD_PT2_T_INIT5_LSB;
279
280 SD_MRT =
281 0x3 << SD_MRT_T_MRW_LSB;
282
283 reset_phy_dll();
284
285 /* wait for address line pll to come back */
286 SIP_DEBUG(logf("waiting for address dll to lock ...\n"));
287 for (;;) if (APHY_CSR_GLBL_ADR_DLL_LOCK_STAT == 3) break;
288 SIP_DEBUG(logf("address dll locked!\n"));
289
290 /* tell sdc we're done messing with address lines */
291 APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0;
292
293 /* woo, turn on sdram! */
294 SD_CS =
295 (((4 << SD_CS_ASHDN_T_LSB)
296 | SD_CS_STATEN_SET
297 | SD_CS_EN_SET)
298 & ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET;
299 }
300
301 unsigned int read_mr(unsigned int addr) {
302 while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
303 SD_MR = addr & 0xFF;
304 unsigned int mrr;
305 while (((mrr = SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
306 return mrr;
307 }
308
309 unsigned int write_mr(unsigned int addr, unsigned int data, bool wait) {
310 while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
311
312 SD_MR = (addr & 0xFF) | ((data & 0xFF) << 8) | SD_MR_RW_SET;
313
314 if (wait) {
315 unsigned int mrr;
316 while (((mrr = SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
317
318 if (mrr & SD_MR_TIMEOUT_SET)
319 panic("MR write timed out (addr=%d data=0x%X)", addr, data);
320
321 return mrr;
322 }
323 else {
324 return 0;
325 }
326 }
327
328 void reset_phy() {
329 logf("%s: resetting SDRAM PHY ...\n", __FUNCTION__);
330
331 /* reset PHYC */
332 SD_PHYC = SD_PHYC_PHYRST_SET;
333 udelay(64);
334 SD_PHYC = 0;
335
336 logf("%s: resetting DPHY CTRL ...\n", __FUNCTION__);
337
338 DPHY_CSR_DQ_PHY_MISC_CTRL = 0x7;
339 DPHY_CSR_DQ_PAD_MISC_CTRL = 0x0;
340 DPHY_CSR_BOOT_READ_DQS_GATE_CTRL = 0x11;
341
342 reset_phy_dll();
343
344 APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0;
345 }
346
347 static void switch_to_cprman_clock(unsigned int source, unsigned int div) {
348 CM_SDCDIV = CM_PASSWORD | (div << CM_SDCDIV_DIV_LSB);
349 CM_SDCCTL = CM_PASSWORD | (CM_SDCCTL & CM_SDCCTL_SRC_CLR) | source;
350 CM_SDCCTL |= CM_PASSWORD | CM_SDCCTL_ENAB_SET;
351
352 logf("switching sdram to cprman clock (src=%d, div=%d), waiting for busy (%X) ...\n", source, div, CM_SDCCTL);
353
354 for (;;) if (CM_SDCCTL & CM_SDCCTL_BUSY_SET) break;
355
356 logf("busy set, switch complete!\n");
357 }
358
359 static void init_clkman()
360 {
361 uint32_t ctrl = 0;
362
363 clkman_update_begin();
364 CM_SDCCTL = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (CM_SDCCTL & CM_SDCCTL_CTRL_CLR);
365 clkman_update_end();
366 }
367
368 #define CALL_INIT_CLKMAN init_clkman();
369
370
371 /*****************************************************************************
372 * Calibration
373 *****************************************************************************/
374
375 static void calibrate_pvt_early() {
376 /* some hw revisions require different slews */
377 bool st = ((g_CPUID >> 4) & 0xFFF) == 0x14;
378 uint32_t dq_slew = (st ? 2 : 3);
379
380 /* i don't get it, the spec says do not use this register */
381 write_mr(0xFF, 0, true);
382 /* RL = 6 / WL = 3 */
383 write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, true);
384
385 APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL = 0x333;
386 DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = (dq_slew << 8) | (dq_slew << 4) | 3;
387
388 logf("DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = 0x%X\n", DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL);
389
390 /* tell sdc we want to calibrate */
391 APHY_CSR_PHY_BIST_CNTRL_SPR = BIST_pvt;
392
393 /* pvt compensation */
394 APHY_CSR_ADDR_PVT_COMP_CTRL = PVT_calibrate_request;
395 logf("waiting for address PVT calibration ...\n");
396 for (;;) if (APHY_CSR_ADDR_PVT_COMP_STATUS & 2) break;
397
398 DPHY_CSR_DQ_PVT_COMP_CTRL = PVT_calibrate_request;
399 logf("waiting for data PVT calibration ...\n");
400 for (;;) if (DPHY_CSR_DQ_PVT_COMP_STATUS & 2) break;
401
402 /* tell sdc we're done calibrating */
403 APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0;
404
405 /* send calibration command */
406 uint32_t old_mrt = SD_MRT;
407 SD_MRT = 20;
408 logf("waiting for SDRAM calibration command ...\n");
409 SD_MR = LPDDR2_MR_CALIBRATION | (0xFF << 8) | SD_MR_RW_SET | SD_MR_HI_Z_SET;
410 while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
411 SD_MRT = old_mrt;
412
413 write_mr(LPDDR2_MR_IO_CONFIG, st ? 3 : 2, false);
414 }
415
416
417 /*****************************************************************************
418 * Late init
419 *****************************************************************************/
420
421 static void init_late() {
422 }
423
424 /*****************************************************************************
425 * Self-test
426 *****************************************************************************/
427
428 #define RT_BASE 0xC0000000
429
430 #define RT_PAT0 0xAAAAAAAA
431 #define RT_PAT1 0xFF00AA00
432 #define RT_PAT2 0x99999999
433
434 #define RT_ASSERT(i_, expected) \
435 if (ram[(i_)] != expected) { \
436 logf("ERROR: At 0x%X, was expecting 0x%X from read, got 0x%X instead!\n", \
437 (uint32_t)&ram[(i_)], \
438 expected, \
439 ram[(i_)]); \
440 panic("SDRAM self test failed!"); \
441 }
442
443 static void selftest_at(uint32_t addr) {
444 volatile uint32_t* ram = (volatile uint32_t*)addr;
445
446 logf("Testing region at 0x%X ...\n", addr);
447
448 for (int i = 0; i < 0x1000; i += 4) {
449 ram[i] = RT_PAT0;
450 ram[i + 1] = RT_PAT1;
451 ram[i + 2] = RT_PAT2;
452 ram[i + 3] = RT_PAT0;
453 }
454
455 for (int i = 0; i < 0x1000; i += 4) {
456 RT_ASSERT(i, RT_PAT0);
457 RT_ASSERT(i + 1, RT_PAT1);
458 RT_ASSERT(i + 2, RT_PAT2);
459 RT_ASSERT(i + 3, RT_PAT0);
460 }
461 }
462
463 static void selftest()
464 {
465 logf("Starting self test ...\n");
466
467 selftest_at(RT_BASE);
468
469 if (g_RAMSize == RAM_SIZE_256MB || g_RAMSize == RAM_SIZE_512MB || g_RAMSize == RAM_SIZE_1GB) {
470 selftest_at(RT_BASE + 0xFF00000);
471 }
472 if (g_RAMSize == RAM_SIZE_512MB || g_RAMSize == RAM_SIZE_1GB) {
473 selftest_at(RT_BASE + 0x1FF00000);
474 }
475 if (g_RAMSize == RAM_SIZE_1GB) {
476 selftest_at(RT_BASE + 0x2FF00000);
477 selftest_at(RT_BASE + 0x3FF00000);
478 }
479
480 logf("Self test successful!\n");
481 }
482
483 #undef RT_ASSERT
484
485 void sdram_init() {
486 uint32_t vendor_id, bc;
487
488 logf("(0) SD_CS = 0x%X\n", SD_CS);
489
490 PM_SMPS = PM_PASSWORD | 0x1;
491 A2W_SMPS_LDO1 = A2W_PASSWORD | 0x40000;
492 A2W_SMPS_LDO0 = A2W_PASSWORD | 0x0;
493
494 A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_DDREN_SET;
495
496 /*
497 * STEP 1:
498 * configure the low-frequency PLL and enable SDC and perform
499 * the calibration sequence.
500 */
501
502 switch_to_cprman_clock(CM_SRC_OSC, 1);
503
504 CALL_INIT_CLKMAN;
505
506 reset_phy();
507
508 /* magic values */
509 SD_SA = 0x006E3395;
510 SD_SB = 0x0F9;
511 SD_SC = 0x6000431;
512 SD_SD = 0x10000011;
513 SD_SE = 0x10106000;
514 SD_PT1 = 0x0AF002;
515 SD_PT2 = 0x8C;
516 SD_MRT = 0x3;
517 SD_CS = 0x200042;
518
519 /* wait for SDRAM controller */
520 logf("waiting for SDUP (%X) ...\n", SD_CS);
521 for (;;) if (SD_CS & SD_CS_SDUP_SET) break;
522 logf("SDRAM controller has arrived! (%X)\n", SD_CS);
523
524 /* RL = 6 / WL = 3 */
525 write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, false);
526 calibrate_pvt_early();
527
528 /* identify installed memory */
529 vendor_id = read_mr(LPDDR2_MR_MANUFACTURER_ID);
530 if (!MR_REQUEST_SUCCESS(vendor_id)) {
531 panic("vendor id memory register read timed out");
532 }
533 vendor_id = MR_GET_RDATA(vendor_id);
534
535 bc = read_mr(LPDDR2_MR_METRICS);
536 if (!MR_REQUEST_SUCCESS(bc)) {
537 panic("basic configuration memory register read timed out");
538 }
539 bc = MR_GET_RDATA(bc);
540
541 g_RAMSize = lpddr2_size(bc);
542
543 logf("SDRAM Type: %s %s LPDDR2 (BC=0x%X)\n",
544 lpddr2_manufacturer_name(vendor_id),
545 size_to_string[g_RAMSize],
546 bc);
547
548 if (g_RAMSize == RAM_SIZE_UNKNOWN)
549 panic("unknown ram size (MR8 response was 0x%X)", bc);
550
551 /*
552 * STEP 2:
553 * after calibration, enable high-freq SDRAM PLL. because we're
554 * running from cache, we can freely mess with SDRAM clock without
555 * any issues, removing the need to copy the SDRAM late init stuff
556 * to bootrom ram. if later code that's running from SDRAM wants to
557 * mess with SDRAM clock it would need to do that.
558 */
559
560 if (g_RAMSize == RAM_SIZE_1GB) {
561 logf("*** USING LOW tREFI (~7.8us) FOR 1GB, YOUR RAM MAY LEAK!!!!\n");
562
563 g_InitSdramParameters.colbits = 3;
564 g_InitSdramParameters.rowbits = 3;
565 g_InitSdramParameters.banklow = 3;
566 }
567 else if (g_RAMSize == RAM_SIZE_512MB) {
568 logf("*** USING LOW tREFI (~7.8us) FOR 512MB, YOUR RAM MAY LEAK!!!!\n");
569
570 g_InitSdramParameters.colbits = 2;
571 }
572
573 reset_with_timing(&g_InitSdramParameters);
574 init_late();
575 selftest();
576 }
577
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