1 /*=============================================================================
2 Copyright (C) 2016-2017 Authors of rpi-open-firmware
3 Copyright (C) 2016 Julian Brown
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
17 VideoCoreIV SDRAM initialization code.
19 =============================================================================*/
29 SC: AC Timing (Page 202)
31 SD: AC Timing (Page 202)
32 SE: AC Timing (Page 202)
35 Minimum Idle time after first CKE assertion
36 Minimum CKE low time after completion of power ramp
41 extern uint32_t g_CPUID
;
43 #define MR_REQUEST_SUCCESS(x) ((SD_MR_TIMEOUT_SET & x) != SD_MR_TIMEOUT_SET)
44 #define MR_GET_RDATA(x) ((x & SD_MR_RDATA_SET) >> SD_MR_RDATA_LSB)
46 #define SIP_DEBUG(x) x
47 #define SCLKU_DEBUG(x) //SIP_DEBUG(x)
50 #define BIST_reset 0x10
52 #define PVT_calibrate_request 0x1
54 #define logf(fmt, ...) printf("[SDRAM:%s]: " fmt, __FUNCTION__, ##__VA_ARGS__);
56 unsigned g_RAMSize
= RAM_SIZE_UNKNOWN
;
58 static const char* lpddr2_manufacturer_name(uint32_t mr
) {
60 case 1: return "Samsung";
61 case 2: return "Qimonda";
62 case 3: return "Elpida";
63 case 4: return "Etron";
64 case 5: return "Nanya";
65 case 6: return "Hynix";
66 default: return "Unknown";
70 #define MR8_DENSITY_SHIFT 0x2
71 #define MR8_DENSITY_MASK (0xF << 0x2)
73 static unsigned lpddr2_size(uint32_t mr
) {
75 case 0x58: return RAM_SIZE_1GB
;
76 case 0x18: return RAM_SIZE_512MB
;
77 case 0x14: return RAM_SIZE_256MB
;
78 case 0x10: return RAM_SIZE_128MB
;
79 default: return RAM_SIZE_UNKNOWN
;
83 const char* size_to_string
[] = {
91 /*****************************************************************************
93 *****************************************************************************/
95 ALWAYS_INLINE
inline void clkman_update_begin() {
96 CM_SDCCTL
|= CM_PASSWORD
| CM_SDCCTL_UPDATE_SET
;
97 SCLKU_DEBUG(logf("waiting for ACCPT (%X) ...\n", CM_SDCCTL
));
98 for (;;) if (CM_SDCCTL
& CM_SDCCTL_ACCPT_SET
) break;
99 SCLKU_DEBUG(logf("ACCPT received! (%X)\n", CM_SDCCTL
));
102 ALWAYS_INLINE
inline void clkman_update_end() {
103 CM_SDCCTL
= CM_PASSWORD
| (CM_SDCCTL
& CM_SDCCTL_UPDATE_CLR
);
104 SCLKU_DEBUG(logf("waiting for ACCPT clear (%X) ...\n", CM_SDCCTL
));
105 for (;;) if ((CM_SDCCTL
& CM_SDCCTL_ACCPT_SET
) == 0) break;
106 SCLKU_DEBUG(logf("ACCPT cleared! (%X)\n", CM_SDCCTL
));
109 ALWAYS_INLINE
void reset_phy_dll() {
110 SIP_DEBUG(logf("resetting aphy and dphy dlls ...\n", __FUNCTION__
));
112 /* politely tell sdc that we'll be messing with address lines */
113 APHY_CSR_PHY_BIST_CNTRL_SPR
= 0x30;
115 DPHY_CSR_GLBL_DQ_DLL_RESET
= 0x1;
116 APHY_CSR_GLBL_ADDR_DLL_RESET
= 0x1;
124 DPHY_CSR_GLBL_DQ_DLL_RESET
= 0x0;
125 APHY_CSR_GLBL_ADDR_DLL_RESET
= 0x0;
127 SIP_DEBUG(logf("waiting for dphy master dll to lock ...\n", __FUNCTION__
));
128 for (;;) if ((DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT
& 0xFFFF) == 0xFFFF) break;
129 SIP_DEBUG(logf("dphy master dll locked!\n", __FUNCTION__
));
148 uint32_t tDQSCKMAXx2
;
165 lpddr2_timings_t g_InitSdramParameters
= {
167 .tREFI
= 3113, //Refresh rate: 3113 * (1.0 / 400) = 7.78us
185 .tINIT1
= 40, // Minimum CKE low time after completion of power ramp: 40 * (1.0 / 0.4) = 100ns
186 .tINIT3
= 79800, // Minimum Idle time after first CKE assertion: 79800 * (1.0 / 400) = 199.5us ~ 200us
187 .tINIT5
= 3990, //Max DAI: 3990* (1.0 / 400) = 9.9us ~ 10us
194 void reset_with_timing(lpddr2_timings_t
* T
) {
197 SD_CS
= (SD_CS
& ~(SD_CS_DEL_KEEP_SET
|SD_CS_DPD_SET
|SD_CS_RESTRT_SET
)) | SD_CS_STBY_SET
;
199 /* wait for SDRAM controller to go down */
200 SIP_DEBUG(logf("waiting for SDRAM controller to go down (%X) ...\n", SD_CS
));
201 for (;;) if ((SD_CS
& SD_CS_SDUP_SET
) == 0) break;
202 SIP_DEBUG(logf("SDRAM controller down!\n"));
204 /* disable SDRAM clock */
205 clkman_update_begin();
206 CM_SDCCTL
= (CM_SDCCTL
& ~(CM_SDCCTL_ENAB_SET
|CM_SDCCTL_CTRL_SET
)) | CM_PASSWORD
;
209 SIP_DEBUG(logf("SDRAM clock disabled!\n"));
212 * Migrate over to master PLL.
215 APHY_CSR_DDR_PLL_PWRDWN
= 0;
216 APHY_CSR_DDR_PLL_GLOBAL_RESET
= 0;
217 APHY_CSR_DDR_PLL_POST_DIV_RESET
= 0;
220 APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0
= (1 << 16) | 0x53;
221 APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1
= 0;
222 APHY_CSR_DDR_PLL_MDIV_VALUE
= 0;
224 APHY_CSR_DDR_PLL_GLOBAL_RESET
= 1;
226 SIP_DEBUG(logf("waiting for master ddr pll to lock ...\n"));
227 for (;;) if (APHY_CSR_DDR_PLL_LOCK_STATUS
& (1 << 16)) break;
228 SIP_DEBUG(logf("master ddr pll locked!\n"));
230 APHY_CSR_DDR_PLL_POST_DIV_RESET
= 1;
232 clkman_update_begin();
233 CM_SDCCTL
= CM_PASSWORD
| (ctrl
<< CM_SDCCTL_CTRL_LSB
) | (CM_SDCCTL
& CM_SDCCTL_CTRL_CLR
);
237 (T
->tREFI
<< SD_SA_RFSH_T_LSB
)
245 | (T
->banklow
<< SD_SB_BANKLOW_LSB
)
246 | SD_SB_EIGHTBANK_SET
247 | (T
->rowbits
<< SD_SB_ROWBITS_LSB
)
248 | (T
->colbits
<< SD_SB_COLBITS_LSB
);
250 logf("SDRAM Addressing Mode: Bank=%d Row=%d Col=%d SB=0x%X\n", T
->banklow
, T
->rowbits
, T
->colbits
, SD_SB
);
253 (T
->tRFCab
<< SD_SC_T_RFC_LSB
)
254 | (T
->tRRD
<< SD_SC_T_RRD_LSB
)
255 | (T
->tWR
<< SD_SC_T_WR_LSB
)
256 | (T
->tWTR
<< SD_SC_T_WTR_LSB
)
257 | (3 << SD_SC_WL_LSB
);
260 (T
->tRPab
<< SD_SD_T_RPab_LSB
)
261 | (T
->tRC
<< SD_SD_T_RC_LSB
)
262 | (T
->tXP
<< SD_SD_T_XP_LSB
)
263 | (T
->tRASmin
<< SD_SD_T_RAS_LSB
)
264 | (T
->tRPpb
<< SD_SD_T_RPpb_LSB
)
265 | (T
->tRCD
<< SD_SD_T_RCD_LSB
);
268 (1 << SD_SE_RL_EN_LSB
)
269 | (4 << SD_SE_RL_LSB
)
270 | (T
->tFAW
<< SD_SE_T_FAW_LSB
)
271 | (T
->tRTP
<< SD_SE_T_RTP_LSB
)
272 | (T
->tXSR
<< SD_SE_T_XSR_LSB
);
275 (T
->tINIT3
<< SD_PT1_T_INIT3_LSB
)
276 | (T
->tINIT1
<< SD_PT1_T_INIT1_LSB
);
279 T
->tINIT5
<< SD_PT2_T_INIT5_LSB
;
282 0x3 << SD_MRT_T_MRW_LSB
;
286 /* wait for address line pll to come back */
287 SIP_DEBUG(logf("waiting for address dll to lock ...\n"));
288 for (;;) if (APHY_CSR_GLBL_ADR_DLL_LOCK_STAT
== 3) break;
289 SIP_DEBUG(logf("address dll locked!\n"));
291 /* tell sdc we're done messing with address lines */
292 APHY_CSR_PHY_BIST_CNTRL_SPR
= 0x0;
294 /* woo, turn on sdram! */
296 (((4 << SD_CS_ASHDN_T_LSB
)
299 & ~(SD_CS_STOP_SET
|SD_CS_STBY_SET
)) | SD_CS_RESTRT_SET
;
302 unsigned int read_mr(unsigned int addr
) {
303 while ((SD_MR
& SD_MR_DONE_SET
) != SD_MR_DONE_SET
) {}
306 while (((mrr
= SD_MR
) & SD_MR_DONE_SET
) != SD_MR_DONE_SET
) {}
310 unsigned int write_mr(unsigned int addr
, unsigned int data
, bool wait
) {
311 while ((SD_MR
& SD_MR_DONE_SET
) != SD_MR_DONE_SET
) {}
313 SD_MR
= (addr
& 0xFF) | ((data
& 0xFF) << 8) | SD_MR_RW_SET
;
317 while (((mrr
= SD_MR
) & SD_MR_DONE_SET
) != SD_MR_DONE_SET
) {}
319 if (mrr
& SD_MR_TIMEOUT_SET
)
320 panic("MR write timed out (addr=%d data=0x%X)", addr
, data
);
330 logf("%s: resetting SDRAM PHY ...\n", __FUNCTION__
);
333 SD_PHYC
= SD_PHYC_PHYRST_SET
;
337 logf("%s: resetting DPHY CTRL ...\n", __FUNCTION__
);
339 DPHY_CSR_DQ_PHY_MISC_CTRL
= 0x7;
340 DPHY_CSR_DQ_PAD_MISC_CTRL
= 0x0;
341 DPHY_CSR_BOOT_READ_DQS_GATE_CTRL
= 0x11;
345 APHY_CSR_PHY_BIST_CNTRL_SPR
= 0x0;
348 static void switch_to_cprman_clock(unsigned int source
, unsigned int div
) {
349 CM_SDCDIV
= CM_PASSWORD
| (div
<< CM_SDCDIV_DIV_LSB
);
350 CM_SDCCTL
= CM_PASSWORD
| (CM_SDCCTL
& CM_SDCCTL_SRC_CLR
) | source
;
351 CM_SDCCTL
|= CM_PASSWORD
| CM_SDCCTL_ENAB_SET
;
353 logf("switching sdram to cprman clock (src=%d, div=%d), waiting for busy (%X) ...\n", source
, div
, CM_SDCCTL
);
355 for (;;) if (CM_SDCCTL
& CM_SDCCTL_BUSY_SET
) break;
357 logf("busy set, switch complete!\n");
360 static void init_clkman()
364 clkman_update_begin();
365 CM_SDCCTL
= CM_PASSWORD
| (ctrl
<< CM_SDCCTL_CTRL_LSB
) | (CM_SDCCTL
& CM_SDCCTL_CTRL_CLR
);
369 #define CALL_INIT_CLKMAN init_clkman();
372 /*****************************************************************************
374 *****************************************************************************/
376 static void calibrate_pvt_early() {
377 /* some hw revisions require different slews */
378 bool st
= ((g_CPUID
>> 4) & 0xFFF) == 0x14;
379 uint32_t dq_slew
= (st
? 2 : 3);
381 /* i don't get it, the spec says do not use this register */
382 write_mr(0xFF, 0, true);
383 /* RL = 6 / WL = 3 */
384 write_mr(LPDDR2_MR_DEVICE_FEATURE_2
, 4, true);
386 APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL
= 0x333;
387 DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL
= (dq_slew
<< 8) | (dq_slew
<< 4) | 3;
389 logf("DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = 0x%X\n", DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL
);
391 /* tell sdc we want to calibrate */
392 APHY_CSR_PHY_BIST_CNTRL_SPR
= BIST_pvt
;
394 /* pvt compensation */
395 APHY_CSR_ADDR_PVT_COMP_CTRL
= PVT_calibrate_request
;
396 logf("waiting for address PVT calibration ...\n");
397 for (;;) if (APHY_CSR_ADDR_PVT_COMP_STATUS
& 2) break;
399 DPHY_CSR_DQ_PVT_COMP_CTRL
= PVT_calibrate_request
;
400 logf("waiting for data PVT calibration ...\n");
401 for (;;) if (DPHY_CSR_DQ_PVT_COMP_STATUS
& 2) break;
403 /* tell sdc we're done calibrating */
404 APHY_CSR_PHY_BIST_CNTRL_SPR
= 0x0;
406 /* send calibration command */
407 uint32_t old_mrt
= SD_MRT
;
409 logf("waiting for SDRAM calibration command ...\n");
410 SD_MR
= LPDDR2_MR_CALIBRATION
| (0xFF << 8) | SD_MR_RW_SET
| SD_MR_HI_Z_SET
;
411 while ((SD_MR
& SD_MR_DONE_SET
) != SD_MR_DONE_SET
) {}
414 write_mr(LPDDR2_MR_IO_CONFIG
, st
? 3 : 2, false);
418 /*****************************************************************************
420 *****************************************************************************/
422 static void init_late() {
425 /*****************************************************************************
427 *****************************************************************************/
429 #define RT_BASE 0xC0000000
431 #define RT_PAT0 0xAAAAAAAA
432 #define RT_PAT1 0xFF00AA00
433 #define RT_PAT2 0x99999999
435 #define RT_ASSERT(i_, expected) \
436 if (ram[(i_)] != expected) { \
437 logf("ERROR: At 0x%X, was expecting 0x%X from read, got 0x%X instead!\n", \
438 (uint32_t)&ram[(i_)], \
441 panic("SDRAM self test failed!"); \
444 static void selftest_at(uint32_t addr
) {
445 volatile uint32_t* ram
= (volatile uint32_t*)addr
;
447 logf("Testing region at 0x%X ...\n", addr
);
449 for (int i
= 0; i
< 0x1000; i
+= 4) {
451 ram
[i
+ 1] = RT_PAT1
;
452 ram
[i
+ 2] = RT_PAT2
;
453 ram
[i
+ 3] = RT_PAT0
;
456 for (int i
= 0; i
< 0x1000; i
+= 4) {
457 RT_ASSERT(i
, RT_PAT0
);
458 RT_ASSERT(i
+ 1, RT_PAT1
);
459 RT_ASSERT(i
+ 2, RT_PAT2
);
460 RT_ASSERT(i
+ 3, RT_PAT0
);
464 static void selftest()
466 logf("Starting self test ...\n");
468 selftest_at(RT_BASE
);
470 if (g_RAMSize
== RAM_SIZE_256MB
|| g_RAMSize
== RAM_SIZE_512MB
|| g_RAMSize
== RAM_SIZE_1GB
) {
471 selftest_at(RT_BASE
+ 0xFF00000);
473 if (g_RAMSize
== RAM_SIZE_512MB
|| g_RAMSize
== RAM_SIZE_1GB
) {
474 selftest_at(RT_BASE
+ 0x1FF00000);
476 if (g_RAMSize
== RAM_SIZE_1GB
) {
477 selftest_at(RT_BASE
+ 0x2FF00000);
478 selftest_at(RT_BASE
+ 0x3FF00000);
481 logf("Self test successful!\n");
487 uint32_t vendor_id
, bc
;
489 logf("(0) SD_CS = 0x%X\n", SD_CS
);
491 PM_SMPS
= PM_PASSWORD
| 0x1;
492 A2W_SMPS_LDO1
= A2W_PASSWORD
| 0x40000;
493 A2W_SMPS_LDO0
= A2W_PASSWORD
| 0x0;
495 A2W_XOSC_CTRL
|= A2W_PASSWORD
| A2W_XOSC_CTRL_DDREN_SET
;
499 * configure the low-frequency PLL and enable SDC and perform
500 * the calibration sequence.
503 switch_to_cprman_clock(CM_SRC_OSC
, 1);
520 /* wait for SDRAM controller */
521 logf("waiting for SDUP (%X) ...\n", SD_CS
);
522 for (;;) if (SD_CS
& SD_CS_SDUP_SET
) break;
523 logf("SDRAM controller has arrived! (%X)\n", SD_CS
);
525 /* RL = 6 / WL = 3 */
526 write_mr(LPDDR2_MR_DEVICE_FEATURE_2
, 4, false);
527 calibrate_pvt_early();
529 /* identify installed memory */
530 vendor_id
= read_mr(LPDDR2_MR_MANUFACTURER_ID
);
531 if (!MR_REQUEST_SUCCESS(vendor_id
)) {
532 panic("vendor id memory register read timed out");
534 vendor_id
= MR_GET_RDATA(vendor_id
);
536 bc
= read_mr(LPDDR2_MR_METRICS
);
537 if (!MR_REQUEST_SUCCESS(bc
)) {
538 panic("basic configuration memory register read timed out");
540 bc
= MR_GET_RDATA(bc
);
542 g_RAMSize
= lpddr2_size(bc
);
544 logf("SDRAM Type: %s %s LPDDR2 (BC=0x%X)\n",
545 lpddr2_manufacturer_name(vendor_id
),
546 size_to_string
[g_RAMSize
],
549 if (g_RAMSize
== RAM_SIZE_UNKNOWN
)
550 panic("unknown ram size (MR8 response was 0x%X)", bc
);
554 * after calibration, enable high-freq SDRAM PLL. because we're
555 * running from cache, we can freely mess with SDRAM clock without
556 * any issues, removing the need to copy the SDRAM late init stuff
557 * to bootrom ram. if later code that's running from SDRAM wants to
558 * mess with SDRAM clock it would need to do that.
561 if (g_RAMSize
== RAM_SIZE_1GB
) {
562 logf("*** USING LOW tREFI (~7.8us) FOR 1GB, YOUR RAM MAY LEAK!!!!\n");
564 g_InitSdramParameters
.colbits
= 3;
565 g_InitSdramParameters
.rowbits
= 3;
566 g_InitSdramParameters
.banklow
= 3;
568 else if (g_RAMSize
== RAM_SIZE_512MB
) {
569 logf("*** USING LOW tREFI (~7.8us) FOR 512MB, YOUR RAM MAY LEAK!!!!\n");
571 g_InitSdramParameters
.colbits
= 2;
574 reset_with_timing(&g_InitSdramParameters
);