misc cleanup
[rpi-open-firmware.git] / start.s
1 /*=============================================================================
2 Copyright (C) 2016-2017 Authors of rpi-open-firmware
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 Entry.
17
18 A small explanation. The ROM loads bootcode.bin at 0x80000000 and jumps to
19 0x80000200. This region corresponds to L1/L2 cached IO and cache is never
20 evicted as long as we don't touch memory above that. This gives us 128KB
21 of memory at startup.
22
23 Exception names are from the public release from:
24 brcm_usrlib\dag\vmcsx\vcfw\rtos\none\rtos_none.c
25
26 =============================================================================*/
27
28 .text
29
30 empty_space:
31 .space 0x200
32
33 /* main entry point */
34
35 .globl _start
36 .align 2
37 _start:
38 version r0
39 mov r5, r0
40
41 /* vectors */
42 mov r3, #0x1B000
43 mov r1, r3
44
45 /*
46 * populate the exception vector table using PC relative labels
47 * so the code isnt position dependent
48 */
49 .macro RegExceptionHandler label, exception_number
50 lea r2, fleh_\label
51 st r2, (r1)
52 add r1, #4
53 .endm
54
55 RegExceptionHandler zero, #0
56 RegExceptionHandler misaligned, #1
57 RegExceptionHandler dividebyzero, #2
58 RegExceptionHandler undefinedinstruction, #3
59 RegExceptionHandler forbiddeninstruction, #4
60 RegExceptionHandler illegalmemory, #5
61 RegExceptionHandler buserror, #6
62 RegExceptionHandler floatingpoint, #7
63 RegExceptionHandler isp, #8
64 RegExceptionHandler dummy, #9
65 RegExceptionHandler icache, #10
66 RegExceptionHandler veccore, #11
67 RegExceptionHandler badl2alias, #12
68 RegExceptionHandler breakpoint, #13
69 RegExceptionHandler unknown, #14
70 RegExceptionHandler unknown, #15
71 RegExceptionHandler unknown, #16
72 RegExceptionHandler unknown, #17
73 RegExceptionHandler unknown, #18
74 RegExceptionHandler unknown, #19
75 RegExceptionHandler unknown, #20
76 RegExceptionHandler unknown, #21
77 RegExceptionHandler unknown, #22
78 RegExceptionHandler unknown, #23
79 RegExceptionHandler unknown, #24
80 RegExceptionHandler unknown, #25
81 RegExceptionHandler unknown, #26
82 RegExceptionHandler unknown, #27
83 RegExceptionHandler unknown, #28
84 RegExceptionHandler unknown, #29
85 RegExceptionHandler unknown, #30
86 RegExceptionHandler unknown, #31
87
88 add r1, r3, #128
89 lea r2, fleh_irq
90 add r4, r3, #572
91
92 L_setup_hw_irq:
93 st r2, (r1)
94 add r1, #4
95 ble r1, r4, L_setup_hw_irq
96
97 /*
98 * load the interrupt and normal stack pointers. these
99 * are chosen to be near the top of the available cache memory
100 */
101
102 mov r28, #0x1D000
103 mov sp, #0x1C000
104
105 /* jump to C code */
106 mov r0, r5
107 lea r1, _start
108
109 bl _main
110
111 /************************************************************
112 * Exception Handling
113 ************************************************************/
114
115 .macro SaveRegsLower
116 stm lr, (--sp)
117 stm r0-r5, (--sp)
118 .endm
119
120 .macro SaveRegsUpper
121 stm r6-r15, (--sp)
122 stm r16-r23, (--sp)
123 .endm
124
125 .macro SaveRegsAll
126 SaveRegsLower
127 SaveRegsUpper
128 .endm
129
130 fatal_exception:
131 SaveRegsUpper
132 mov r0, sp
133 b sleh_fatal
134
135 .macro ExceptionHandler label, exception_number
136 fleh_\label:
137 SaveRegsLower
138 mov r1, \exception_number
139 b fatal_exception
140 .endm
141
142 ExceptionHandler zero, #0
143 ExceptionHandler misaligned, #1
144 ExceptionHandler dividebyzero, #2
145 ExceptionHandler undefinedinstruction, #3
146 ExceptionHandler forbiddeninstruction, #4
147 ExceptionHandler illegalmemory, #5
148 ExceptionHandler buserror, #6
149 ExceptionHandler floatingpoint, #7
150 ExceptionHandler isp, #8
151 ExceptionHandler dummy, #9
152 ExceptionHandler icache, #10
153 ExceptionHandler veccore, #11
154 ExceptionHandler badl2alias, #12
155 ExceptionHandler breakpoint, #13
156 ExceptionHandler unknown, #14
157
158 fleh_irq:
159 SaveRegsAll
160
161 /* top of savearea */
162 mov r0, sp
163 mov r1, r29
164 bl sleh_irq
165
166 return_from_exception:
167 ldm r16-r23, (sp++)
168 ldm r6-r15, (sp++)
169 ldm r0-r5, (sp++)
170 ld lr, (sp++)
171 rti
172
173 /* include chainloader */
174
175 .align 2
176 .globl L_arm_code_start
177 L_arm_code_start:
178
179 .incbin "arm_chainloader/build/arm_chainloader.bin"
180
181 .globl L_arm_code_end
182 L_arm_code_end:
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