2e3e035c9f3176d5e0417fe346b1266f55c42cfb
[rpi-open-firmware.git] / start.s
1 /*=============================================================================
2 Copyright (C) 2016 Kristina Brooks
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 Entry.
17
18 A small explanation. The ROM loads bootcode.bin at 0x80000000 and jumps to
19 0x80000200. This region corresponds to L1/L2 cached IO and cache is never
20 evicted as long as we don't touch memory above that. This gives us 128KB
21 of memory at startup.
22
23 Exception names are from the public release from:
24 brcm_usrlib\dag\vmcsx\vcfw\rtos\none\rtos_none.c
25
26 =============================================================================*/
27
28
29 .text
30
31 empty_space:
32 .space 0x200
33
34 .include "ghetto.s"
35
36 /* main entry point */
37
38 .globl _start
39 .align 2
40 _start:
41 version r0
42 mov r5, r0
43
44 /* vectors */
45 mov r3, #0x1B000
46 mov r1, r3
47
48 /*
49 * populate the exception vector table using PC relative labels
50 * so the code isnt position dependent
51 */
52 .macro RegExceptionHandler label, exception_number
53 lea r2, fleh_\label
54 st r2, (r1)
55 add r1, #4
56 .endm
57
58
59 RegExceptionHandler zero, #0
60 RegExceptionHandler misaligned, #1
61 RegExceptionHandler dividebyzero, #2
62 RegExceptionHandler undefinedinstruction, #3
63 RegExceptionHandler forbiddeninstruction, #4
64 RegExceptionHandler illegalmemory, #5
65 RegExceptionHandler buserror, #6
66 RegExceptionHandler floatingpoint, #7
67 RegExceptionHandler isp, #8
68 RegExceptionHandler dummy, #9
69 RegExceptionHandler icache, #10
70 RegExceptionHandler veccore, #11
71 RegExceptionHandler badl2alias, #12
72 RegExceptionHandler breakpoint, #13
73 RegExceptionHandler unknown, #14
74
75 //add r1, r3, #252
76 add r1, r3, #128
77 lea r2, fleh_irq
78 //mov r4, #492
79 add r4, r3, #492
80
81 L_setup_hw_irq:
82 st r2, (r1)
83 add r1, #4
84 ble r1, r4, L_setup_hw_irq
85
86 /*
87 * load the interrupt and normal stack pointers. these
88 * are chosen to be near the top of the available cache memory
89 */
90
91 mov r28, #0x1D000
92 mov sp, #0x1C000
93
94 /* set interrupt vector bases */
95 mov r0, #IC0_VADDR
96 st r3, (r0)
97 mov r0, #IC1_VADDR
98 st r3, (r0)
99
100 /* unmask ARM interrupts */
101 mov r0, #(IC0_BASE + 0x10)
102 mov r1, #(IC1_BASE + 0x10)
103 mov r2, 0xFFFFFFFF
104 mov r3, #(IC0_BASE + 0x10 + 0x20)
105
106 unmask_all:
107 st r2, (r0)
108 st r2, (r1)
109 add r0, 4
110 add r1, 4
111 ble r0, r3, unmask_all
112
113 /* enable interrupts */
114 ei
115
116 /* jump to C code */
117 mov r0, r5
118 lea r1, _start
119
120 bl _main
121
122 /************************************************************
123 * Debug
124 ************************************************************/
125
126 blinker:
127 mov r1, #GPFSEL1
128 ld r0, (r1)
129 and r0, #(~(7<<18))
130 or r0, #(1<<18)
131 st r0, (r1)
132 mov r1, #GPSET0
133 mov r2, #GPCLR0
134 mov r3, #(1<<16)
135 loop:
136 st r3, (r1)
137 mov r0, #0
138 delayloop1:
139 add r0, #1
140 cmp r0, #0x100000
141 bne delayloop1
142 st r3, (r2)
143 mov r0, #0
144 delayloop2:
145 add r0, #1
146 cmp r0, #0x100000
147 bne delayloop2
148 b loop
149
150 /************************************************************
151 * Exception Handling
152 ************************************************************/
153
154 .macro SaveRegsLower
155 stm lr, (--sp)
156 stm r0-r5, (--sp)
157 .endm
158
159 .macro SaveRegsUpper
160 stm r6-r15, (--sp)
161 stm r16-r23, (--sp)
162 .endm
163
164 .macro SaveRegsAll
165 SaveRegsLower
166 SaveRegsUpper
167 .endm
168
169 fatal_exception:
170 SaveRegsUpper
171 mov r0, sp
172 b sleh_fatal
173
174 .macro ExceptionHandler label, exception_number
175 fleh_\label:
176 SaveRegsLower
177 mov r1, \exception_number
178 b fatal_exception
179 .endm
180
181 ExceptionHandler zero, #0
182 ExceptionHandler misaligned, #1
183 ExceptionHandler dividebyzero, #2
184 ExceptionHandler undefinedinstruction, #3
185 ExceptionHandler forbiddeninstruction, #4
186 ExceptionHandler illegalmemory, #5
187 ExceptionHandler buserror, #6
188 ExceptionHandler floatingpoint, #7
189 ExceptionHandler isp, #8
190 ExceptionHandler dummy, #9
191 ExceptionHandler icache, #10
192 ExceptionHandler veccore, #11
193 ExceptionHandler badl2alias, #12
194 ExceptionHandler breakpoint, #13
195 ExceptionHandler unknown, #14
196
197 fleh_irq:
198 SaveRegsAll
199
200 /* top of savearea */
201 mov r0, sp
202 bl sleh_irq
203
204 return_from_exception:
205 ldm r16-r23, (sp++)
206 ldm r6-r15, (sp++)
207 ldm r0-r5, (sp++)
208 ld lr, (sp++)
209 rti
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