Determine precisely where interrupts came from
[rpi-open-firmware.git] / start.s
1 /*=============================================================================
2 Copyright (C) 2016-2017 Authors of rpi-open-firmware
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 Entry.
17
18 A small explanation. The ROM loads bootcode.bin at 0x80000000 and jumps to
19 0x80000200. This region corresponds to L1/L2 cached IO and cache is never
20 evicted as long as we don't touch memory above that. This gives us 128KB
21 of memory at startup.
22
23 Exception names are from the public release from:
24 brcm_usrlib\dag\vmcsx\vcfw\rtos\none\rtos_none.c
25
26 =============================================================================*/
27
28 .text
29
30 empty_space:
31 .space 0x200
32
33 /* MMIO-mapped registers for the interrupt table */
34
35 .set IC0_BASE, 0x7e002000
36 .set IC0_VADDR, 0x7e002030
37
38 .set IC1_BASE, 0x7e002800
39 .set IC1_VADDR, 0x7e002830
40
41 /* main entry point */
42
43 .globl _start
44 .align 2
45 _start:
46 version r0
47 mov r5, r0
48
49 /* vectors */
50 mov r3, #0x1B000
51 mov r1, r3
52
53 /*
54 * populate the exception vector table using PC relative labels
55 * so the code isnt position dependent
56 */
57 .macro RegExceptionHandler label, exception_number
58 lea r2, fleh_\label
59 st r2, (r1)
60 add r1, #4
61 .endm
62
63 RegExceptionHandler zero, #0
64 RegExceptionHandler misaligned, #1
65 RegExceptionHandler dividebyzero, #2
66 RegExceptionHandler undefinedinstruction, #3
67 RegExceptionHandler forbiddeninstruction, #4
68 RegExceptionHandler illegalmemory, #5
69 RegExceptionHandler buserror, #6
70 RegExceptionHandler floatingpoint, #7
71 RegExceptionHandler isp, #8
72 RegExceptionHandler dummy, #9
73 RegExceptionHandler icache, #10
74 RegExceptionHandler veccore, #11
75 RegExceptionHandler badl2alias, #12
76 RegExceptionHandler breakpoint, #13
77 RegExceptionHandler unknown, #14
78 RegExceptionHandler unknown, #15
79 RegExceptionHandler unknown, #16
80 RegExceptionHandler unknown, #17
81 RegExceptionHandler unknown, #18
82 RegExceptionHandler unknown, #19
83 RegExceptionHandler unknown, #20
84 RegExceptionHandler unknown, #21
85 RegExceptionHandler unknown, #22
86 RegExceptionHandler unknown, #23
87 RegExceptionHandler unknown, #24
88 RegExceptionHandler unknown, #25
89 RegExceptionHandler unknown, #26
90 RegExceptionHandler unknown, #27
91 RegExceptionHandler unknown, #28
92 RegExceptionHandler unknown, #29
93 RegExceptionHandler unknown, #30
94 RegExceptionHandler unknown, #31
95
96 add r1, r3, #128
97 lea r2, fleh_irq
98 add r4, r3, #572
99
100 L_setup_hw_irq:
101 st r2, (r1)
102 add r1, #4
103 ble r1, r4, L_setup_hw_irq
104
105 /*
106 * load the interrupt and normal stack pointers. these
107 * are chosen to be near the top of the available cache memory
108 */
109
110 mov r28, #0x1D000
111 mov sp, #0x1C000
112
113 /* mask interrupts */
114 mov r0, #(IC0_BASE + 0x10)
115 mov r1, #(IC1_BASE + 0x10)
116 mov r2, 0x00000000
117 mov r3, #(IC0_BASE + 0x10 + 0x20)
118
119 mask_all:
120 st r2, (r0)
121 st r2, (r1)
122 add r0, 4
123 add r1, 4
124 ble r0, r3, mask_all
125
126 /* set interrupt vector bases */
127 mov r3, #0x1B000
128 mov r0, #IC0_VADDR
129 st r3, (r0)
130 mov r0, #IC1_VADDR
131 st r3, (r0)
132
133 /* enable interrupts */
134 ei
135
136 /* jump to C code */
137 mov r0, r5
138 lea r1, _start
139
140 bl _main
141
142 /************************************************************
143 * Exception Handling
144 ************************************************************/
145
146 .macro SaveRegsLower
147 stm lr, (--sp)
148 stm r0-r5, (--sp)
149 .endm
150
151 .macro SaveRegsUpper
152 stm r6-r15, (--sp)
153 stm r16-r23, (--sp)
154 .endm
155
156 .macro SaveRegsAll
157 SaveRegsLower
158 SaveRegsUpper
159 .endm
160
161 fatal_exception:
162 SaveRegsUpper
163 mov r0, sp
164 b sleh_fatal
165
166 .macro ExceptionHandler label, exception_number
167 fleh_\label:
168 SaveRegsLower
169 mov r1, \exception_number
170 b fatal_exception
171 .endm
172
173 ExceptionHandler zero, #0
174 ExceptionHandler misaligned, #1
175 ExceptionHandler dividebyzero, #2
176 ExceptionHandler undefinedinstruction, #3
177 ExceptionHandler forbiddeninstruction, #4
178 ExceptionHandler illegalmemory, #5
179 ExceptionHandler buserror, #6
180 ExceptionHandler floatingpoint, #7
181 ExceptionHandler isp, #8
182 ExceptionHandler dummy, #9
183 ExceptionHandler icache, #10
184 ExceptionHandler veccore, #11
185 ExceptionHandler badl2alias, #12
186 ExceptionHandler breakpoint, #13
187 ExceptionHandler unknown, #14
188
189 fleh_irq:
190 SaveRegsAll
191
192 /* top of savearea */
193 mov r0, sp
194 mov r1, r29
195 bl sleh_irq
196
197 return_from_exception:
198 ldm r16-r23, (sp++)
199 ldm r6-r15, (sp++)
200 ldm r0-r5, (sp++)
201 ld lr, (sp++)
202 rti
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