b78ac64dddf2b8192c030f944757d5f52c172e18
[rpi-open-firmware.git] / start.s
1 /*=============================================================================
2 Copyright (C) 2016-2017 Authors of rpi-open-firmware
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 Entry.
17
18 A small explanation. The ROM loads bootcode.bin at 0x80000000 and jumps to
19 0x80000200. This region corresponds to L1/L2 cached IO and cache is never
20 evicted as long as we don't touch memory above that. This gives us 128KB
21 of memory at startup.
22
23 Exception names are from the public release from:
24 brcm_usrlib\dag\vmcsx\vcfw\rtos\none\rtos_none.c
25
26 =============================================================================*/
27
28 .text
29
30 empty_space:
31 .space 0x200
32
33 .include "ghetto.s"
34
35 /* main entry point */
36
37 .globl _start
38 .align 2
39 _start:
40 version r0
41 mov r5, r0
42
43 /* vectors */
44 mov r3, #0x1B000
45 mov r1, r3
46
47 /*
48 * populate the exception vector table using PC relative labels
49 * so the code isnt position dependent
50 */
51 .macro RegExceptionHandler label, exception_number
52 lea r2, fleh_\label
53 st r2, (r1)
54 add r1, #4
55 .endm
56
57 RegExceptionHandler zero, #0
58 RegExceptionHandler misaligned, #1
59 RegExceptionHandler dividebyzero, #2
60 RegExceptionHandler undefinedinstruction, #3
61 RegExceptionHandler forbiddeninstruction, #4
62 RegExceptionHandler illegalmemory, #5
63 RegExceptionHandler buserror, #6
64 RegExceptionHandler floatingpoint, #7
65 RegExceptionHandler isp, #8
66 RegExceptionHandler dummy, #9
67 RegExceptionHandler icache, #10
68 RegExceptionHandler veccore, #11
69 RegExceptionHandler badl2alias, #12
70 RegExceptionHandler breakpoint, #13
71 RegExceptionHandler unknown, #14
72 RegExceptionHandler unknown, #15
73 RegExceptionHandler unknown, #16
74 RegExceptionHandler unknown, #17
75 RegExceptionHandler unknown, #18
76 RegExceptionHandler unknown, #19
77 RegExceptionHandler unknown, #20
78 RegExceptionHandler unknown, #21
79 RegExceptionHandler unknown, #22
80 RegExceptionHandler unknown, #23
81 RegExceptionHandler unknown, #24
82 RegExceptionHandler unknown, #25
83 RegExceptionHandler unknown, #26
84 RegExceptionHandler unknown, #27
85 RegExceptionHandler unknown, #28
86 RegExceptionHandler unknown, #29
87 RegExceptionHandler unknown, #30
88 RegExceptionHandler unknown, #31
89
90 add r1, r3, #128
91 lea r2, fleh_irq
92 add r4, r3, #572
93
94 L_setup_hw_irq:
95 st r2, (r1)
96 add r1, #4
97 ble r1, r4, L_setup_hw_irq
98
99 /*
100 * load the interrupt and normal stack pointers. these
101 * are chosen to be near the top of the available cache memory
102 */
103
104 mov r28, #0x1D000
105 mov sp, #0x1C000
106
107 /* unmask ARM interrupts */
108 mov r0, #(IC0_BASE + 0x10)
109 mov r1, #(IC1_BASE + 0x10)
110 mov r2, 0x11111111
111 mov r3, #(IC0_BASE + 0x10 + 0x10)
112
113 unmask_all:
114 st r2, (r0)
115 st r2, (r1)
116 add r0, 4
117 add r1, 4
118 ble r0, r3, unmask_all
119
120 /* set interrupt vector bases */
121 mov r3, #0x1B000
122 mov r0, #IC0_VADDR
123 st r3, (r0)
124 mov r0, #IC1_VADDR
125 st r3, (r0)
126
127 /* enable interrupts */
128 ei
129
130 /* jump to C code */
131 mov r0, r5
132 lea r1, _start
133
134 bl _main
135
136 /************************************************************
137 * Debug
138 ************************************************************/
139
140 blinker:
141 mov r1, #GPFSEL1
142 ld r0, (r1)
143 and r0, #(~(7<<18))
144 or r0, #(1<<18)
145 st r0, (r1)
146 mov r1, #GPSET0
147 mov r2, #GPCLR0
148 mov r3, #(1<<16)
149 loop:
150 st r3, (r1)
151 mov r0, #0
152 delayloop1:
153 add r0, #1
154 cmp r0, #0x100000
155 bne delayloop1
156 st r3, (r2)
157 mov r0, #0
158 delayloop2:
159 add r0, #1
160 cmp r0, #0x100000
161 bne delayloop2
162 b loop
163
164 /************************************************************
165 * Exception Handling
166 ************************************************************/
167
168 .macro SaveRegsLower
169 stm lr, (--sp)
170 stm r0-r5, (--sp)
171 .endm
172
173 .macro SaveRegsUpper
174 stm r6-r15, (--sp)
175 stm r16-r23, (--sp)
176 .endm
177
178 .macro SaveRegsAll
179 SaveRegsLower
180 SaveRegsUpper
181 .endm
182
183 fatal_exception:
184 SaveRegsUpper
185 mov r0, sp
186 b sleh_fatal
187
188 .macro ExceptionHandler label, exception_number
189 fleh_\label:
190 SaveRegsLower
191 mov r1, \exception_number
192 b fatal_exception
193 .endm
194
195 ExceptionHandler zero, #0
196 ExceptionHandler misaligned, #1
197 ExceptionHandler dividebyzero, #2
198 ExceptionHandler undefinedinstruction, #3
199 ExceptionHandler forbiddeninstruction, #4
200 ExceptionHandler illegalmemory, #5
201 ExceptionHandler buserror, #6
202 ExceptionHandler floatingpoint, #7
203 ExceptionHandler isp, #8
204 ExceptionHandler dummy, #9
205 ExceptionHandler icache, #10
206 ExceptionHandler veccore, #11
207 ExceptionHandler badl2alias, #12
208 ExceptionHandler breakpoint, #13
209 ExceptionHandler unknown, #14
210
211 fleh_irq:
212 SaveRegsAll
213
214 /* top of savearea */
215 mov r0, sp
216 mov r1, r29
217 bl sleh_irq
218
219 return_from_exception:
220 ldm r16-r23, (sp++)
221 ldm r6-r15, (sp++)
222 ldm r0-r5, (sp++)
223 ld lr, (sp++)
224 rti
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