Fix merge conflict
[rpi-open-firmware.git] / start.s
1 /*=============================================================================
2 Copyright (C) 2016 Kristina Brooks
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 Entry.
17
18 A small explanation. The ROM loads bootcode.bin at 0x80000000 and jumps to
19 0x80000200. This region corresponds to L1/L2 cached IO and cache is never
20 evicted as long as we don't touch memory above that. This gives us 128KB
21 of memory at startup.
22
23 Exception names are from the public release from:
24 brcm_usrlib\dag\vmcsx\vcfw\rtos\none\rtos_none.c
25
26 =============================================================================*/
27
28
29 .text
30
31 empty_space:
32 .space 0x200
33
34 .include "ghetto.s"
35
36 /* main entry point */
37
38 .globl _start
39 .align 2
40 _start:
41 version r0
42 mov r5, r0
43
44 /* vectors */
45 mov r3, #0x1B000
46 mov r1, r3
47
48 /*
49 * populate the exception vector table using PC relative labels
50 * so the code isnt position dependent
51 */
52 .macro RegExceptionHandler label, exception_number
53 lea r2, fleh_\label
54 st r2, (r1)
55 add r1, #4
56 .endm
57
58
59 RegExceptionHandler zero, #0
60 RegExceptionHandler misaligned, #1
61 RegExceptionHandler dividebyzero, #2
62 RegExceptionHandler undefinedinstruction, #3
63 RegExceptionHandler forbiddeninstruction, #4
64 RegExceptionHandler illegalmemory, #5
65 RegExceptionHandler buserror, #6
66 RegExceptionHandler floatingpoint, #7
67 RegExceptionHandler isp, #8
68 RegExceptionHandler dummy, #9
69 RegExceptionHandler icache, #10
70 RegExceptionHandler veccore, #11
71 RegExceptionHandler badl2alias, #12
72 RegExceptionHandler breakpoint, #13
73 RegExceptionHandler unknown, #14
74 RegExceptionHandler unknown, #15
75 RegExceptionHandler unknown, #16
76 RegExceptionHandler unknown, #17
77 RegExceptionHandler unknown, #18
78 RegExceptionHandler unknown, #19
79 RegExceptionHandler unknown, #20
80 RegExceptionHandler unknown, #21
81 RegExceptionHandler unknown, #22
82 RegExceptionHandler unknown, #23
83 RegExceptionHandler unknown, #24
84 RegExceptionHandler unknown, #25
85 RegExceptionHandler unknown, #26
86 RegExceptionHandler unknown, #27
87 RegExceptionHandler unknown, #28
88 RegExceptionHandler unknown, #29
89 RegExceptionHandler unknown, #30
90 RegExceptionHandler unknown, #31
91
92 //add r1, r3, #252
93 add r1, r3, #128
94 lea r2, fleh_irq
95 //mov r4, #492
96 add r4, r3, #492
97
98 L_setup_hw_irq:
99 st r2, (r1)
100 add r1, #4
101 ble r1, r4, L_setup_hw_irq
102
103 /*
104 * load the interrupt and normal stack pointers. these
105 * are chosen to be near the top of the available cache memory
106 */
107
108 mov r28, #0x1D000
109 mov sp, #0x1C000
110
111 /* unmask ARM interrupts */
112 mov r0, #(IC0_BASE + 0x10)
113 mov r1, #(IC1_BASE + 0x10)
114 mov r2, 0x11111111
115 mov r3, #(IC0_BASE + 0x10 + 0x20)
116
117 unmask_all:
118 st r2, (r0)
119 st r2, (r1)
120 add r0, 4
121 add r1, 4
122 ble r0, r3, unmask_all
123
124 /* set interrupt vector bases */
125 mov r3, #0x1B000
126 mov r0, #IC0_VADDR
127 st r3, (r0)
128 mov r0, #IC1_VADDR
129 st r3, (r0)
130
131
132 /* enable interrupts */
133 ei
134
135 /* jump to C code */
136 mov r0, r5
137 lea r1, _start
138
139 bl _main
140
141 /************************************************************
142 * Debug
143 ************************************************************/
144
145 blinker:
146 mov r1, #GPFSEL1
147 ld r0, (r1)
148 and r0, #(~(7<<18))
149 or r0, #(1<<18)
150 st r0, (r1)
151 mov r1, #GPSET0
152 mov r2, #GPCLR0
153 mov r3, #(1<<16)
154 loop:
155 st r3, (r1)
156 mov r0, #0
157 delayloop1:
158 add r0, #1
159 cmp r0, #0x100000
160 bne delayloop1
161 st r3, (r2)
162 mov r0, #0
163 delayloop2:
164 add r0, #1
165 cmp r0, #0x100000
166 bne delayloop2
167 b loop
168
169 /************************************************************
170 * Exception Handling
171 ************************************************************/
172
173 .macro SaveRegsLower
174 stm lr, (--sp)
175 stm r0-r5, (--sp)
176 .endm
177
178 .macro SaveRegsUpper
179 stm r6-r15, (--sp)
180 stm r16-r23, (--sp)
181 .endm
182
183 .macro SaveRegsAll
184 SaveRegsLower
185 SaveRegsUpper
186 .endm
187
188 fatal_exception:
189 SaveRegsUpper
190 mov r0, sp
191 b sleh_fatal
192
193 .macro ExceptionHandler label, exception_number
194 fleh_\label:
195 SaveRegsLower
196 mov r1, \exception_number
197 b fatal_exception
198 .endm
199
200 ExceptionHandler zero, #0
201 ExceptionHandler misaligned, #1
202 ExceptionHandler dividebyzero, #2
203 ExceptionHandler undefinedinstruction, #3
204 ExceptionHandler forbiddeninstruction, #4
205 ExceptionHandler illegalmemory, #5
206 ExceptionHandler buserror, #6
207 ExceptionHandler floatingpoint, #7
208 ExceptionHandler isp, #8
209 ExceptionHandler dummy, #9
210 ExceptionHandler icache, #10
211 ExceptionHandler veccore, #11
212 ExceptionHandler badl2alias, #12
213 ExceptionHandler breakpoint, #13
214 ExceptionHandler unknown, #14
215
216 fleh_irq:
217 SaveRegsAll
218
219 /* top of savearea */
220 mov r0, sp
221 bl sleh_irq
222
223 return_from_exception:
224 ldm r16-r23, (sp++)
225 ldm r6-r15, (sp++)
226 ldm r0-r5, (sp++)
227 ld lr, (sp++)
228 rti
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