vc4: fix traps, add ic source detection and dispatch, add proper handler for mbox...
[rpi-open-firmware.git] / start.s
1 /*=============================================================================
2 Copyright (C) 2016 Kristina Brooks
3 All rights reserved.
4
5 This program is free software; you can redistribute it and/or
6 modify it under the terms of the GNU General Public License
7 as published by the Free Software Foundation; either version 2
8 of the License, or (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 FILE DESCRIPTION
16 Entry.
17
18 A small explanation. The ROM loads bootcode.bin at 0x80000000 and jumps to
19 0x80000200. This region corresponds to L1/L2 cached IO and cache is never
20 evicted as long as we don't touch memory above that. This gives us 128KB
21 of memory at startup.
22
23 Exception names are from the public release from:
24 brcm_usrlib\dag\vmcsx\vcfw\rtos\none\rtos_none.c
25
26 =============================================================================*/
27
28 .text
29
30 empty_space:
31 .space 0x200
32
33 .include "ghetto.s"
34
35 /* main entry point */
36
37 .globl _start
38 .align 2
39 _start:
40 version r0
41 mov r5, r0
42
43 /* vectors */
44 mov r3, #0x1B000
45 mov r1, r3
46
47 /*
48 * populate the exception vector table using PC relative labels
49 * so the code isnt position dependent
50 */
51 .macro RegExceptionHandler label, exception_number
52 lea r2, fleh_\label
53 st r2, (r1)
54 add r1, #4
55 .endm
56
57 RegExceptionHandler zero, #0
58 RegExceptionHandler misaligned, #1
59 RegExceptionHandler dividebyzero, #2
60 RegExceptionHandler undefinedinstruction, #3
61 RegExceptionHandler forbiddeninstruction, #4
62 RegExceptionHandler illegalmemory, #5
63 RegExceptionHandler buserror, #6
64 RegExceptionHandler floatingpoint, #7
65 RegExceptionHandler isp, #8
66 RegExceptionHandler dummy, #9
67 RegExceptionHandler icache, #10
68 RegExceptionHandler veccore, #11
69 RegExceptionHandler badl2alias, #12
70 RegExceptionHandler breakpoint, #13
71 RegExceptionHandler unknown, #14
72 RegExceptionHandler unknown, #15
73 RegExceptionHandler unknown, #16
74 RegExceptionHandler unknown, #17
75 RegExceptionHandler unknown, #18
76 RegExceptionHandler unknown, #19
77 RegExceptionHandler unknown, #20
78 RegExceptionHandler unknown, #21
79 RegExceptionHandler unknown, #22
80 RegExceptionHandler unknown, #23
81 RegExceptionHandler unknown, #24
82 RegExceptionHandler unknown, #25
83 RegExceptionHandler unknown, #26
84 RegExceptionHandler unknown, #27
85 RegExceptionHandler unknown, #28
86 RegExceptionHandler unknown, #29
87 RegExceptionHandler unknown, #30
88 RegExceptionHandler unknown, #31
89
90 //add r1, r3, #252
91 add r1, r3, #128
92 lea r2, fleh_irq
93 //mov r4, #492
94 add r4, r3, #492
95
96 L_setup_hw_irq:
97 st r2, (r1)
98 add r1, #4
99 ble r1, r4, L_setup_hw_irq
100
101 /*
102 * load the interrupt and normal stack pointers. these
103 * are chosen to be near the top of the available cache memory
104 */
105
106 mov r28, #0x1D000
107 mov sp, #0x1C000
108
109 /* unmask ARM interrupts */
110 mov r0, #(IC0_BASE + 0x10)
111 mov r1, #(IC1_BASE + 0x10)
112 mov r2, 0x11111111
113 mov r3, #(IC0_BASE + 0x10 + 0x20)
114
115 unmask_all:
116 st r2, (r0)
117 st r2, (r1)
118 add r0, 4
119 add r1, 4
120 ble r0, r3, unmask_all
121
122 /* set interrupt vector bases */
123 mov r3, #0x1B000
124 mov r0, #IC0_VADDR
125 st r3, (r0)
126 mov r0, #IC1_VADDR
127 st r3, (r0)
128
129 /* enable interrupts */
130 ei
131
132 /* jump to C code */
133 mov r0, r5
134 lea r1, _start
135
136 bl _main
137
138 /************************************************************
139 * Debug
140 ************************************************************/
141
142 blinker:
143 mov r1, #GPFSEL1
144 ld r0, (r1)
145 and r0, #(~(7<<18))
146 or r0, #(1<<18)
147 st r0, (r1)
148 mov r1, #GPSET0
149 mov r2, #GPCLR0
150 mov r3, #(1<<16)
151 loop:
152 st r3, (r1)
153 mov r0, #0
154 delayloop1:
155 add r0, #1
156 cmp r0, #0x100000
157 bne delayloop1
158 st r3, (r2)
159 mov r0, #0
160 delayloop2:
161 add r0, #1
162 cmp r0, #0x100000
163 bne delayloop2
164 b loop
165
166 /************************************************************
167 * Exception Handling
168 ************************************************************/
169
170 .macro SaveRegsLower
171 stm lr, (--sp)
172 stm r0-r5, (--sp)
173 .endm
174
175 .macro SaveRegsUpper
176 stm r6-r15, (--sp)
177 stm r16-r23, (--sp)
178 .endm
179
180 .macro SaveRegsAll
181 SaveRegsLower
182 SaveRegsUpper
183 .endm
184
185 fatal_exception:
186 SaveRegsUpper
187 mov r0, sp
188 b sleh_fatal
189
190 .macro ExceptionHandler label, exception_number
191 fleh_\label:
192 SaveRegsLower
193 mov r1, \exception_number
194 b fatal_exception
195 .endm
196
197 ExceptionHandler zero, #0
198 ExceptionHandler misaligned, #1
199 ExceptionHandler dividebyzero, #2
200 ExceptionHandler undefinedinstruction, #3
201 ExceptionHandler forbiddeninstruction, #4
202 ExceptionHandler illegalmemory, #5
203 ExceptionHandler buserror, #6
204 ExceptionHandler floatingpoint, #7
205 ExceptionHandler isp, #8
206 ExceptionHandler dummy, #9
207 ExceptionHandler icache, #10
208 ExceptionHandler veccore, #11
209 ExceptionHandler badl2alias, #12
210 ExceptionHandler breakpoint, #13
211 ExceptionHandler unknown, #14
212
213 fleh_irq:
214 SaveRegsAll
215
216 /* top of savearea */
217 mov r0, sp
218 mov r1, r29
219 bl sleh_irq
220
221 return_from_exception:
222 ldm r16-r23, (sp++)
223 ldm r6-r15, (sp++)
224 ldm r0-r5, (sp++)
225 ld lr, (sp++)
226 rti
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