add preliminary clock code that's expected to be set up by fw, gut old arm loader...
[rpi-open-firmware.git] / romstage.c
index ab2fa67..fd88544 100644 (file)
@@ -1,5 +1,5 @@
 /*=============================================================================\r
-Copyright (C) 2016 Kristina Brooks\r
+Copyright (C) 2016-2017 Authors of rpi-open-firmware\r
 All rights reserved.\r
 \r
 This program is free software; you can redistribute it and/or\r
@@ -17,7 +17,7 @@ VideoCoreIV first stage bootloader.
 \r
 =============================================================================*/\r
 \r
-#include <common.h>\r
+#include <lib/runtime.h>\r
 #include <hardware.h>\r
 \r
 uint32_t g_CPUID;\r
@@ -41,9 +41,8 @@ uint32_t g_CPUID;
 #define UART_ITOP   (UART_BASE+0x88)\r
 #define UART_TDR    (UART_BASE+0x8C)\r
 \r
-void uart_putc(unsigned int ch)\r
-{\r
-       while(UART_MSR & 0x20) break;\r
+void uart_putc(unsigned int ch) {\r
+       while(UART_MSR & 0x20);\r
        UART_RBRTHRDLL = ch;\r
 }\r
 \r
@@ -51,28 +50,26 @@ void uart_init(void) {
        unsigned int ra = GP_FSEL1;\r
        ra &= ~(7 << 12);\r
        ra |= 4 << 12;\r
+       ra &= ~(7 << 15);\r
+       ra |= 4 << 15;\r
        GP_FSEL1 = ra;\r
 \r
-        CM_UARTCTL = CM_PASSWORD | CM_SRC_OSC | CM_UARTCTL_FRAC_SET;\r
-        udelay(150);\r
-        CM_UARTDIV = CM_PASSWORD | 0x6666;\r
-        udelay(150);\r
-        CM_UARTCTL |= CM_UARTCTL_ENAB_SET;\r
-        udelay(150);\r
-        \r
-        mmio_write32(UART_CR, 0);\r
+       mmio_write32(UART_CR, 0);\r
 \r
-        GP_PUD = 0;\r
+       GP_PUD = 0;\r
        udelay(150);\r
        GP_PUDCLK0 = (1 << 14) | (1 << 15);\r
        udelay(150);\r
        GP_PUDCLK0 = 0;\r
 \r
-        mmio_write32(UART_IBRD, 1);\r
-        mmio_write32(UART_FBRD, 40);\r
-        mmio_write32(UART_ICR, 0x7FF);\r
-        mmio_write32(UART_LCRH, 0x70);\r
-        mmio_write32(UART_CR, 0x301);\r
+       CM_UARTDIV = CM_PASSWORD | 0x6666;\r
+       CM_UARTCTL = CM_PASSWORD | CM_SRC_OSC | CM_UARTCTL_FRAC_SET | CM_UARTCTL_ENAB_SET;\r
+\r
+       mmio_write32(UART_ICR, 0x7FF);\r
+       mmio_write32(UART_IBRD, 1);\r
+       mmio_write32(UART_FBRD, 40);\r
+       mmio_write32(UART_LCRH, 0x70);\r
+       mmio_write32(UART_CR, 0x301);\r
 }\r
 \r
 void led_init(void) {\r
@@ -113,7 +110,7 @@ void switch_vpu_to_pllc() {
 \r
        A2W_PLLC_FRAC = A2W_PASSWORD | 87380;\r
        A2W_PLLC_CTRL = A2W_PASSWORD | 52 | 0x1000;\r
-       \r
+\r
        A2W_PLLC_ANA3 = A2W_PASSWORD | 0x100;\r
        A2W_PLLC_ANA2 = A2W_PASSWORD | 0x0;\r
        A2W_PLLC_ANA1 = A2W_PASSWORD | 0x144000;\r
@@ -123,8 +120,8 @@ void switch_vpu_to_pllc() {
 \r
        /* hold all */\r
        CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |\r
-               CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
-               CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;\r
+                 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
+                 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;\r
 \r
        A2W_PLLC_DIG3 = A2W_PASSWORD | 0x0;\r
        A2W_PLLC_DIG2 = A2W_PASSWORD | 0x400000;\r
@@ -141,16 +138,16 @@ void switch_vpu_to_pllc() {
        A2W_PLLC_CORE0 = A2W_PASSWORD | 2;\r
 \r
        CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |\r
-               CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
-               CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET | CM_PLLC_LOADCORE0_SET;\r
+                 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
+                 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET | CM_PLLC_LOADCORE0_SET;\r
 \r
        CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |\r
-               CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
-               CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;\r
+                 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
+                 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;\r
 \r
        CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |\r
-               CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
-               CM_PLLC_HOLDCORE1_SET;\r
+                 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
+                 CM_PLLC_HOLDCORE1_SET;\r
 \r
        CM_VPUCTL = CM_PASSWORD | CM_VPUCTL_FRAC_SET | CM_SRC_OSC | CM_VPUCTL_GATE_SET;\r
        CM_VPUDIV = CM_PASSWORD | (4 << 12);\r
@@ -164,6 +161,7 @@ void switch_vpu_to_pllc() {
 extern void sdram_init();\r
 extern void arm_init();\r
 extern void monitor_start();\r
+extern void PEStartPlatform();\r
 \r
 void print_crap() {\r
        printf("TB_BOOT_OPT = 0x%X\n", TB_BOOT_OPT);\r
@@ -175,34 +173,33 @@ int _main(unsigned int cpuid, unsigned int load_address) {
        led_init();\r
        uart_init();\r
 \r
-        for(;;) {\r
        printf(\r
-               "=========================================================\n"\r
-               "::\n"\r
-               ":: kFW for bcm2708, Copyright 2016, Kristina Brooks. \n"\r
-               "::\n"\r
-               ":: BUILDATE  : %s %s \n"\r
-               ":: BUILDSTYLE: %s \n"\r
-               "::\n"\r
-               "=========================================================\n",\r
-               __DATE__, __TIME__,\r
-               "OPENSOURCE"\r
+           "==================================================================\n"\r
+           "::\n"\r
+           ":: kFW for bcm270x, Copyright 2016-2017 rpi-open-firmware authors \n"\r
+           "::\n"\r
+           ":: BUILDATE  : %s %s \n"\r
+           ":: BUILDSTYLE: %s \n"\r
+           "::\n"\r
+           "==================================================================\n",\r
+           __DATE__, __TIME__,\r
+           "OPENSOURCE"\r
        );\r
 \r
        printf("CPUID    = 0x%X\n", cpuid);\r
        printf("LoadAddr = 0x%X\n", load_address);\r
 \r
        print_crap();\r
-        }\r
 \r
        g_CPUID = cpuid;\r
 \r
+       __cxx_init();\r
+\r
        /* bring up SDRAM */\r
        sdram_init();\r
        printf("SDRAM initialization completed successfully!\n");\r
 \r
-       /* bring up ARM */\r
-       arm_init();\r
+       PEStartPlatform();\r
 \r
        /* start vpu monitor */\r
        monitor_start();\r
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