Remove SDRAM manufacturer name code
[rpi-open-firmware.git] / sdram.c
diff --git a/sdram.c b/sdram.c
index 1f7df89..0d34893 100644 (file)
--- a/sdram.c
+++ b/sdram.c
@@ -33,7 +33,7 @@ VideoCoreIV SDRAM initialization code.
  PT1:\r
        Minimum Idle time after first CKE assertion\r
        Minimum CKE low time after completion of power ramp\r
- PT2: \r
+ PT2:\r
        DAI Duration\r
  */\r
 \r
@@ -52,30 +52,23 @@ extern uint32_t g_CPUID;
 \r
 #define logf(fmt, ...) printf("[SDRAM:%s]: " fmt, __FUNCTION__, ##__VA_ARGS__);\r
 \r
-unsigned g_RAMSize = RAM_SIZE_UNKNOWN;\r
-\r
-static const char* lpddr2_manufacturer_name(uint32_t mr) {\r
-       switch (mr) {\r
-               case 1: return "Samsung";\r
-               case 2: return "Qimonda";\r
-               case 3: return "Elpida";\r
-               case 4: return "Etron";\r
-               case 5: return "Nanya";\r
-               case 6: return "Hynix";\r
-               default: return "Unknown";\r
-       }\r
-}\r
+uint32_t g_RAMSize = RAM_SIZE_UNKNOWN;\r
 \r
 #define MR8_DENSITY_SHIFT      0x2\r
 #define MR8_DENSITY_MASK       (0xF << 0x2)\r
 \r
 static unsigned lpddr2_size(uint32_t mr) {\r
        switch (mr) {\r
-               case 0x58: return RAM_SIZE_1GB;\r
-               case 0x18: return RAM_SIZE_512MB;\r
-               case 0x14: return RAM_SIZE_256MB;\r
-               case 0x10: return RAM_SIZE_128MB;\r
-               default: return RAM_SIZE_UNKNOWN;\r
+       case 0x58:\r
+               return RAM_SIZE_1GB;\r
+       case 0x18:\r
+               return RAM_SIZE_512MB;\r
+       case 0x14:\r
+               return RAM_SIZE_256MB;\r
+       case 0x10:\r
+               return RAM_SIZE_128MB;\r
+       default:\r
+               return RAM_SIZE_UNKNOWN;\r
        }\r
 }\r
 \r
@@ -113,13 +106,13 @@ ALWAYS_INLINE void reset_phy_dll() {
 \r
        DPHY_CSR_GLBL_DQ_DLL_RESET = 0x1;\r
        APHY_CSR_GLBL_ADDR_DLL_RESET = 0x1;\r
-       \r
+\r
        /* stall ... */\r
        SD_CS;\r
        SD_CS;\r
        SD_CS;\r
        SD_CS;\r
-       \r
+\r
        DPHY_CSR_GLBL_DQ_DLL_RESET = 0x0;\r
        APHY_CSR_GLBL_ADDR_DLL_RESET = 0x0;\r
 \r
@@ -233,52 +226,52 @@ void reset_with_timing(lpddr2_timings_t* T) {
        clkman_update_end();\r
 \r
        SD_SA =\r
-               (T->tREFI << SD_SA_RFSH_T_LSB)\r
-                       | SD_SA_PGEHLDE_SET\r
-                       | SD_SA_CLKSTOP_SET\r
-                       | SD_SA_POWSAVE_SET\r
-                       | 0x3214;\r
+           (T->tREFI << SD_SA_RFSH_T_LSB)\r
+           | SD_SA_PGEHLDE_SET\r
+           | SD_SA_CLKSTOP_SET\r
+           | SD_SA_POWSAVE_SET\r
+           | 0x3214;\r
 \r
        SD_SB =\r
-               SD_SB_REORDER_SET\r
-                       | (T->banklow << SD_SB_BANKLOW_LSB)\r
-                       | SD_SB_EIGHTBANK_SET\r
-                       | (T->rowbits << SD_SB_ROWBITS_LSB)\r
-                       | (T->colbits << SD_SB_COLBITS_LSB);\r
+           SD_SB_REORDER_SET\r
+           | (T->banklow << SD_SB_BANKLOW_LSB)\r
+           | SD_SB_EIGHTBANK_SET\r
+           | (T->rowbits << SD_SB_ROWBITS_LSB)\r
+           | (T->colbits << SD_SB_COLBITS_LSB);\r
 \r
        logf("SDRAM Addressing Mode: Bank=%d Row=%d Col=%d SB=0x%X\n", T->banklow, T->rowbits, T->colbits, SD_SB);\r
 \r
        SD_SC =\r
-               (T->tRFCab << SD_SC_T_RFC_LSB)\r
-                       | (T->tRRD << SD_SC_T_RRD_LSB)\r
-                       | (T->tWR << SD_SC_T_WR_LSB)\r
-                       | (T->tWTR << SD_SC_T_WTR_LSB)\r
-                       | (3 << SD_SC_WL_LSB);\r
+           (T->tRFCab << SD_SC_T_RFC_LSB)\r
+           | (T->tRRD << SD_SC_T_RRD_LSB)\r
+           | (T->tWR << SD_SC_T_WR_LSB)\r
+           | (T->tWTR << SD_SC_T_WTR_LSB)\r
+           | (3 << SD_SC_WL_LSB);\r
 \r
        SD_SD =\r
-               (T->tRPab << SD_SD_T_RPab_LSB)\r
-                       | (T->tRC << SD_SD_T_RC_LSB)\r
-                       | (T->tXP << SD_SD_T_XP_LSB)\r
-                       | (T->tRASmin << SD_SD_T_RAS_LSB)\r
-                       | (T->tRPpb << SD_SD_T_RPpb_LSB)\r
-                       | (T->tRCD << SD_SD_T_RCD_LSB);\r
+           (T->tRPab << SD_SD_T_RPab_LSB)\r
+           | (T->tRC << SD_SD_T_RC_LSB)\r
+           | (T->tXP << SD_SD_T_XP_LSB)\r
+           | (T->tRASmin << SD_SD_T_RAS_LSB)\r
+           | (T->tRPpb << SD_SD_T_RPpb_LSB)\r
+           | (T->tRCD << SD_SD_T_RCD_LSB);\r
 \r
        SD_SE =\r
-               (1 << SD_SE_RL_EN_LSB)\r
-                       | (4 << SD_SE_RL_LSB)\r
-                       | (T->tFAW << SD_SE_T_FAW_LSB)\r
-                       | (T->tRTP << SD_SE_T_RTP_LSB)\r
-                       | (T->tXSR << SD_SE_T_XSR_LSB);\r
+           (1 << SD_SE_RL_EN_LSB)\r
+           | (4 << SD_SE_RL_LSB)\r
+           | (T->tFAW << SD_SE_T_FAW_LSB)\r
+           | (T->tRTP << SD_SE_T_RTP_LSB)\r
+           | (T->tXSR << SD_SE_T_XSR_LSB);\r
 \r
        SD_PT1 =\r
-               (T->tINIT3 << SD_PT1_T_INIT3_LSB)\r
-                       | (T->tINIT1 << SD_PT1_T_INIT1_LSB);\r
+           (T->tINIT3 << SD_PT1_T_INIT3_LSB)\r
+           | (T->tINIT1 << SD_PT1_T_INIT1_LSB);\r
 \r
        SD_PT2 =\r
-               T->tINIT5 << SD_PT2_T_INIT5_LSB;\r
+           T->tINIT5 << SD_PT2_T_INIT5_LSB;\r
 \r
        SD_MRT =\r
-               0x3 << SD_MRT_T_MRW_LSB;\r
+           0x3 << SD_MRT_T_MRW_LSB;\r
 \r
        reset_phy_dll();\r
 \r
@@ -292,10 +285,10 @@ void reset_with_timing(lpddr2_timings_t* T) {
 \r
        /* woo, turn on sdram! */\r
        SD_CS =\r
-               (((4 << SD_CS_ASHDN_T_LSB)\r
-                       | SD_CS_STATEN_SET\r
-                       | SD_CS_EN_SET)\r
-               & ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET;\r
+           (((4 << SD_CS_ASHDN_T_LSB)\r
+             | SD_CS_STATEN_SET\r
+             | SD_CS_EN_SET)\r
+            & ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET;\r
 }\r
 \r
 unsigned int read_mr(unsigned int addr) {\r
@@ -310,7 +303,7 @@ unsigned int write_mr(unsigned int addr, unsigned int data, bool wait) {
        while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}\r
 \r
        SD_MR = (addr & 0xFF) | ((data & 0xFF) << 8) | SD_MR_RW_SET;\r
-       \r
+\r
        if (wait) {\r
                unsigned int mrr;\r
                while (((mrr = SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}\r
@@ -319,8 +312,7 @@ unsigned int write_mr(unsigned int addr, unsigned int data, bool wait) {
                        panic("MR write timed out (addr=%d data=0x%X)", addr, data);\r
 \r
                return mrr;\r
-       }\r
-       else {\r
+       } else {\r
                return 0;\r
        }\r
 }\r
@@ -356,8 +348,7 @@ static void switch_to_cprman_clock(unsigned int source, unsigned int div) {
        logf("busy set, switch complete!\n");\r
 }\r
 \r
-static void init_clkman()\r
-{\r
+static void init_clkman() {\r
        uint32_t ctrl = 0;\r
 \r
        clkman_update_begin();\r
@@ -365,7 +356,7 @@ static void init_clkman()
        clkman_update_end();\r
 }\r
 \r
-       #define CALL_INIT_CLKMAN init_clkman();\r
+#define CALL_INIT_CLKMAN init_clkman();\r
 \r
 \r
 /*****************************************************************************\r
@@ -460,8 +451,7 @@ static void selftest_at(uint32_t addr) {
        }\r
 }\r
 \r
-static void selftest()\r
-{\r
+static void selftest() {\r
        logf("Starting self test ...\n");\r
 \r
        selftest_at(RT_BASE);\r
@@ -490,7 +480,7 @@ void sdram_init() {
        PM_SMPS = PM_PASSWORD | 0x1;\r
        A2W_SMPS_LDO1 = A2W_PASSWORD | 0x40000;\r
        A2W_SMPS_LDO0 = A2W_PASSWORD | 0x0;\r
-       \r
+\r
        A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_DDREN_SET;\r
 \r
        /*\r
@@ -511,7 +501,7 @@ void sdram_init() {
        SD_SC = 0x6000431;\r
        SD_SD = 0x10000011;\r
        SD_SE = 0x10106000;\r
-       SD_PT1 = 0x0AF002; \r
+       SD_PT1 = 0x0AF002;\r
        SD_PT2 = 0x8C;\r
        SD_MRT = 0x3;\r
        SD_CS = 0x200042;\r
@@ -520,7 +510,7 @@ void sdram_init() {
        logf("waiting for SDUP (%X) ...\n", SD_CS);\r
        for (;;) if (SD_CS & SD_CS_SDUP_SET) break;\r
        logf("SDRAM controller has arrived! (%X)\n", SD_CS);\r
-       \r
+\r
        /* RL = 6 / WL = 3 */\r
        write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, false);\r
        calibrate_pvt_early();\r
@@ -540,10 +530,10 @@ void sdram_init() {
 \r
        g_RAMSize = lpddr2_size(bc);\r
 \r
-       logf("SDRAM Type: %s %s LPDDR2 (BC=0x%X)\n",\r
-               lpddr2_manufacturer_name(vendor_id),\r
-               size_to_string[g_RAMSize],\r
-               bc);\r
+       logf("SDRAM Type: %s LPDDR2 (BC=0x%X, vendor %d)\n",\r
+            size_to_string[g_RAMSize],\r
+            bc,\r
+            vendor_id);\r
 \r
        if (g_RAMSize == RAM_SIZE_UNKNOWN)\r
                panic("unknown ram size (MR8 response was 0x%X)", bc);\r
@@ -558,15 +548,10 @@ void sdram_init() {
         */\r
 \r
        if (g_RAMSize == RAM_SIZE_1GB) {\r
-               logf("*** USING LOW tREFI (~7.8us) FOR 1GB, YOUR RAM MAY LEAK!!!!\n");\r
-\r
                g_InitSdramParameters.colbits = 3;\r
                g_InitSdramParameters.rowbits = 3;\r
                g_InitSdramParameters.banklow = 3;\r
-       }\r
-       else if (g_RAMSize == RAM_SIZE_512MB) {\r
-               logf("*** USING LOW tREFI (~7.8us) FOR 512MB, YOUR RAM MAY LEAK!!!!\n");\r
-\r
+       } else if (g_RAMSize == RAM_SIZE_512MB) {\r
                g_InitSdramParameters.colbits = 2;\r
        }\r
 \r
@@ -574,4 +559,3 @@ void sdram_init() {
        init_late();\r
        selftest();\r
 }\r
-\r
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