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[rpi-open-firmware.git] / start.s
diff --git a/start.s b/start.s
old mode 100755 (executable)
new mode 100644 (file)
index 8beda47..2e3e035
--- a/start.s
+++ b/start.s
@@ -38,23 +38,24 @@ empty_space:
 .globl _start
 .align 2
 _start:
-       mov r0, cpuid
+        version r0
        mov r5, r0
 
-       # get addr of the exception vector table
-       lea r1, __INTERRUPT_VECTORS
-       mov r3, r1
+       /* vectors */
+       mov r3, #0x1B000
+       mov r1, r3
 
        /*
         * populate the exception vector table using PC relative labels
         * so the code isnt position dependent
         */
 .macro RegExceptionHandler label, exception_number
-       lea r2, Exc_\label
+       lea r2, fleh_\label
        st r2, (r1)
        add r1, #4
 .endm
 
+
        RegExceptionHandler zero, #0
        RegExceptionHandler misaligned, #1
        RegExceptionHandler dividebyzero, #2
@@ -71,6 +72,17 @@ _start:
        RegExceptionHandler breakpoint, #13
        RegExceptionHandler unknown, #14
 
+       //add r1, r3, #252
+        add r1, r3, #128
+       lea r2, fleh_irq
+       //mov r4, #492
+        add r4, r3, #492
+
+L_setup_hw_irq:
+       st r2, (r1)
+        add r1, #4
+       ble r1, r4, L_setup_hw_irq
+
        /*
         * load the interrupt and normal stack pointers. these
         * are chosen to be near the top of the available cache memory
@@ -85,12 +97,26 @@ _start:
        mov r0, #IC1_VADDR
        st r3, (r0)
 
+        /* unmask ARM interrupts */
+        mov r0, #(IC0_BASE + 0x10)
+        mov r1, #(IC1_BASE + 0x10)
+        mov r2, 0xFFFFFFFF
+        mov r3, #(IC0_BASE + 0x10 + 0x20)
+
+    unmask_all:
+        st r2, (r0)
+        st r2, (r1)
+        add r0, 4
+        add r1, 4
+        ble r0, r3, unmask_all
+
+        /* enable interrupts */
+       ei
+
        /* jump to C code */
        mov r0, r5
        lea r1, _start
 
-       ei
-
        bl _main
 
 /************************************************************
@@ -125,17 +151,31 @@ delayloop2:
  * Exception Handling
  ************************************************************/
 
-_sleh_generic_gate:
-       # get faulting PC
-       ld r1, 4(sp)
-       # call the C exception handler
-       b sleh_fatal
+.macro SaveRegsLower 
+        stm lr, (--sp)
+       stm r0-r5, (--sp)
+.endm
+
+.macro SaveRegsUpper
+       stm r6-r15, (--sp)
+       stm r16-r23, (--sp)
+.endm
+
+.macro SaveRegsAll
+       SaveRegsLower
+       SaveRegsUpper
+.endm
 
+fatal_exception:
+       SaveRegsUpper
+       mov r0, sp
+       b sleh_fatal
 
 .macro ExceptionHandler label, exception_number
-Exc_\label:
-       mov r0, \exception_number
-       b _sleh_generic_gate
+fleh_\label:
+       SaveRegsLower
+       mov r1, \exception_number
+       b fatal_exception
 .endm
 
        ExceptionHandler zero, #0
@@ -154,12 +194,16 @@ Exc_\label:
        ExceptionHandler breakpoint, #13
        ExceptionHandler unknown, #14
 
-/************************************************************
- * ISRs
- ************************************************************/
+fleh_irq:
+       SaveRegsAll
+
+       /* top of savearea */
+       mov r0, sp
+       bl sleh_irq
 
-.align 4
-__INTERRUPT_VECTORS:
-       # 31 slots, 4 byte each for processor exceptions. patched to have the correct
-       # exception handler routines at runtime to allow the code to be loaded anywhere
-       .space 124, 0
+return_from_exception:
+       ldm r16-r23, (sp++)
+       ldm r6-r15, (sp++)
+       ldm r0-r5, (sp++)
+       ld lr, (sp++)
+       rti
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