unified VC4 and ARM runtime code (including C++ runtime), updated some minor bits

[rpi-open-firmware.git] / start.s

diff --git a/start.s b/start.s
index f8c2951..6db9c7c 100644 (file)
--- a/start.s
+++ b/start.s
@@ -1,5 +1,5 @@
 /*=============================================================================
-Copyright (C) 2016 Kristina Brooks
+Copyright (C) 2016-2017 Authors of rpi-open-firmware
 All rights reserved.
 
 This program is free software; you can redistribute it and/or
@@ -25,20 +25,25 @@ Exception names are from the public release from:
 
 =============================================================================*/
 
-
 .text
 
 empty_space:
        .space 0x200
 
-.include "ghetto.s"
+/* MMIO-mapped registers for the interrupt table */
+
+.set IC0_BASE, 0x7e002000
+.set IC0_VADDR, 0x7e002030
+
+.set IC1_BASE, 0x7e002800
+.set IC1_VADDR, 0x7e002830
 
 /* main entry point */
 
 .globl _start
 .align 2
 _start:
-        version r0
+       version r0
        mov r5, r0
 
        /* vectors */
@@ -55,7 +60,6 @@ _start:
        add r1, #4
 .endm
 
-
        RegExceptionHandler zero, #0
        RegExceptionHandler misaligned, #1
        RegExceptionHandler dividebyzero, #2
@@ -71,13 +75,31 @@ _start:
        RegExceptionHandler badl2alias, #12
        RegExceptionHandler breakpoint, #13
        RegExceptionHandler unknown, #14
-
-       add r1, r3, #252
+       RegExceptionHandler unknown, #15
+       RegExceptionHandler unknown, #16
+       RegExceptionHandler unknown, #17
+       RegExceptionHandler unknown, #18
+       RegExceptionHandler unknown, #19
+       RegExceptionHandler unknown, #20
+       RegExceptionHandler unknown, #21
+       RegExceptionHandler unknown, #22
+       RegExceptionHandler unknown, #23
+       RegExceptionHandler unknown, #24
+       RegExceptionHandler unknown, #25
+       RegExceptionHandler unknown, #26
+       RegExceptionHandler unknown, #27
+       RegExceptionHandler unknown, #28
+       RegExceptionHandler unknown, #29
+       RegExceptionHandler unknown, #30
+       RegExceptionHandler unknown, #31
+
+       add r1, r3, #128
        lea r2, fleh_irq
-       mov r4, #492
+       add r4, r3, #572
 
 L_setup_hw_irq:
-       st r2, (r1++)
+       st r2, (r1)
+       add r1, #4
        ble r1, r4, L_setup_hw_irq
 
        /*
@@ -88,54 +110,42 @@ L_setup_hw_irq:
        mov r28, #0x1D000 
        mov sp, #0x1C000
 
+       /* unmask ARM interrupts */
+       mov r0, #(IC0_BASE + 0x10)
+       mov r1, #(IC1_BASE + 0x10)
+       mov r2, 0x11111111
+       mov r3, #(IC0_BASE + 0x10 + 0x10)
+
+unmask_all:
+       st r2, (r0)
+       st r2, (r1)
+       add r0, 4
+       add r1, 4
+       ble r0, r3, unmask_all
+ 
        /* set interrupt vector bases */
+       mov r3, #0x1B000
        mov r0, #IC0_VADDR
        st r3, (r0)
        mov r0, #IC1_VADDR
        st r3, (r0)
 
+       /* enable interrupts */
+       ei
+
        /* jump to C code */
        mov r0, r5
        lea r1, _start
 
-       ei
-
        bl _main
 
-/************************************************************
- * Debug
- ************************************************************/
-
-blinker:
-       mov r1, #GPFSEL1
-       ld r0, (r1)
-       and r0, #(~(7<<18))
-       or r0, #(1<<18)
-       st r0, (r1)
-       mov r1, #GPSET0
-       mov r2, #GPCLR0
-       mov r3, #(1<<16)
-loop:
-       st r3, (r1)
-       mov r0, #0
-delayloop1:
-       add r0, #1
-       cmp r0, #0x100000
-       bne delayloop1
-       st r3, (r2)
-       mov r0, #0
-delayloop2:
-       add r0, #1
-       cmp r0, #0x100000
-       bne delayloop2
-       b loop
-
 /************************************************************
  * Exception Handling
  ************************************************************/
 
 .macro SaveRegsLower 
-       stm r0-r5, lr, (--sp)
+       stm lr, (--sp)
+       stm r0-r5, (--sp)
 .endm
 
 .macro SaveRegsUpper
@@ -181,11 +191,12 @@ fleh_irq:
 
        /* top of savearea */
        mov r0, sp
+       mov r1, r29
        bl sleh_irq
 
 return_from_exception:
        ldm r16-r23, (sp++)
        ldm r6-r15, (sp++)
-       ldm r0-r15, (sp++)
+       ldm r0-r5, (sp++)
        ld lr, (sp++)
        rti