Move Broadcom headers into a seperate folder.
authorAlyssa Rosenzweig <alyssa@rosenzweig.io>
Fri, 6 Jan 2017 06:48:01 +0000 (22:48 -0800)
committerAlyssa Rosenzweig <alyssa@rosenzweig.io>
Fri, 6 Jan 2017 06:48:01 +0000 (22:48 -0800)
This change simplifies licensing questions, in addition to simplifying
tools like astyle which should only affect our codebase.

228 files changed:
bcm2708_chip/README.txt [deleted file]
bcm2708_chip/apb_arbiter_control.h [deleted file]
bcm2708_chip/apb_async_bridge_ctrl.h [deleted file]
bcm2708_chip/arm_control.h [deleted file]
bcm2708_chip/aux_io.h [deleted file]
bcm2708_chip/ave_in.h [deleted file]
bcm2708_chip/ave_out.h [deleted file]
bcm2708_chip/axi_dma0.h [deleted file]
bcm2708_chip/axi_dma1.h [deleted file]
bcm2708_chip/axi_dma15.h [deleted file]
bcm2708_chip/axi_dma2.h [deleted file]
bcm2708_chip/axi_dma3.h [deleted file]
bcm2708_chip/axi_dma4.h [deleted file]
bcm2708_chip/axi_dma5.h [deleted file]
bcm2708_chip/axi_dma6.h [deleted file]
bcm2708_chip/axi_dma7.h [deleted file]
bcm2708_chip/axi_dma8.h [deleted file]
bcm2708_chip/axi_dma_lite10.h [deleted file]
bcm2708_chip/axi_dma_lite11.h [deleted file]
bcm2708_chip/axi_dma_lite12.h [deleted file]
bcm2708_chip/axi_dma_lite13.h [deleted file]
bcm2708_chip/axi_dma_lite14.h [deleted file]
bcm2708_chip/axi_dma_lite7.h [deleted file]
bcm2708_chip/axi_dma_lite8.h [deleted file]
bcm2708_chip/axi_dma_lite9.h [deleted file]
bcm2708_chip/axi_dma_top.h [deleted file]
bcm2708_chip/axi_performance0.h [deleted file]
bcm2708_chip/axi_performance1.h [deleted file]
bcm2708_chip/cam0.h [deleted file]
bcm2708_chip/cam0_a0.h [deleted file]
bcm2708_chip/cam1.h [deleted file]
bcm2708_chip/cam1_a0.h [deleted file]
bcm2708_chip/camccp.h [deleted file]
bcm2708_chip/ccp2tx.h [deleted file]
bcm2708_chip/ccp2tx_a0.h [deleted file]
bcm2708_chip/cdp.h [deleted file]
bcm2708_chip/clkman_image.h [deleted file]
bcm2708_chip/cpg.h [deleted file]
bcm2708_chip/cpi.h [deleted file]
bcm2708_chip/cpr_apb2wtap.h [deleted file]
bcm2708_chip/cpr_apb2wtap_a0.h [deleted file]
bcm2708_chip/cpr_clkman.h [deleted file]
bcm2708_chip/cpr_clkman_a0.h [deleted file]
bcm2708_chip/cpr_powman.h [deleted file]
bcm2708_chip/cpr_powman_a0.h [deleted file]
bcm2708_chip/cryptohw.h [deleted file]
bcm2708_chip/csi2.h [deleted file]
bcm2708_chip/dpi.h [deleted file]
bcm2708_chip/dsi.h [deleted file]
bcm2708_chip/dsi4.h [deleted file]
bcm2708_chip/emmc.h [deleted file]
bcm2708_chip/flow_config.tcl [deleted file]
bcm2708_chip/fpga_microblaze.h [deleted file]
bcm2708_chip/fpga_peripheral.h [deleted file]
bcm2708_chip/gpio.h [deleted file]
bcm2708_chip/h264.h [deleted file]
bcm2708_chip/hardware.h [deleted file]
bcm2708_chip/hdcp.h [deleted file]
bcm2708_chip/hdmi.h [deleted file]
bcm2708_chip/hdmicore.h [deleted file]
bcm2708_chip/hvs.h [deleted file]
bcm2708_chip/i2c0.h [deleted file]
bcm2708_chip/i2c1.h [deleted file]
bcm2708_chip/i2c2.h [deleted file]
bcm2708_chip/i2c_spi_slv.h [deleted file]
bcm2708_chip/intctrl0.h [deleted file]
bcm2708_chip/intctrl1.h [deleted file]
bcm2708_chip/isp.h [deleted file]
bcm2708_chip/israel_bg_dctram.h [deleted file]
bcm2708_chip/israel_bg_instr.h [deleted file]
bcm2708_chip/israel_dsp_registers.h [deleted file]
bcm2708_chip/jpeg_top.h [deleted file]
bcm2708_chip/l2_cache_ctrl.h [deleted file]
bcm2708_chip/mphi.h [deleted file]
bcm2708_chip/multicore_sync.h [deleted file]
bcm2708_chip/nexus_uba.h [deleted file]
bcm2708_chip/otp.h [deleted file]
bcm2708_chip/pcm.h [deleted file]
bcm2708_chip/perfmon.h [deleted file]
bcm2708_chip/peri_image_arb_ctrl.h [deleted file]
bcm2708_chip/pixel_valve0.h [deleted file]
bcm2708_chip/pixel_valve1.h [deleted file]
bcm2708_chip/pixel_valve2.h [deleted file]
bcm2708_chip/pwm.h [deleted file]
bcm2708_chip/register_map.h [deleted file]
bcm2708_chip/register_map_macros.h [deleted file]
bcm2708_chip/rng.h [deleted file]
bcm2708_chip/rng_a0.h [deleted file]
bcm2708_chip/rnghw.h [deleted file]
bcm2708_chip/sdc_addr_front.h [deleted file]
bcm2708_chip/sdc_ctrl.h [deleted file]
bcm2708_chip/sdc_dq_front.h [deleted file]
bcm2708_chip/sdhost.h [deleted file]
bcm2708_chip/slimbus.h [deleted file]
bcm2708_chip/slimbus_a0.h [deleted file]
bcm2708_chip/smi.h [deleted file]
bcm2708_chip/spi_master.h [deleted file]
bcm2708_chip/sv_chip_regmap.h [deleted file]
bcm2708_chip/system_arbiter_ctrl.h [deleted file]
bcm2708_chip/tectl.h [deleted file]
bcm2708_chip/tectl_a0.h [deleted file]
bcm2708_chip/tempsens.h [deleted file]
bcm2708_chip/testbus.h [deleted file]
bcm2708_chip/thread_ctrl.h [deleted file]
bcm2708_chip/timer.h [deleted file]
bcm2708_chip/txp.h [deleted file]
bcm2708_chip/uart.h [deleted file]
bcm2708_chip/usb.h [deleted file]
bcm2708_chip/v3d.h [deleted file]
bcm2708_chip/vcodec.h [deleted file]
bcm2708_chip/vec.h [deleted file]
bcm2708_chip/vpu_arb_ctrl.h [deleted file]
bcm2708_chip/vpu_l1_cache_ctrl.h [deleted file]
broadcom/bcm2708_chip/README.txt [new file with mode: 0644]
broadcom/bcm2708_chip/apb_arbiter_control.h [new file with mode: 0644]
broadcom/bcm2708_chip/apb_async_bridge_ctrl.h [new file with mode: 0644]
broadcom/bcm2708_chip/arm_control.h [new file with mode: 0644]
broadcom/bcm2708_chip/aux_io.h [new file with mode: 0644]
broadcom/bcm2708_chip/ave_in.h [new file with mode: 0644]
broadcom/bcm2708_chip/ave_out.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma0.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma1.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma15.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma2.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma3.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma4.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma5.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma6.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma7.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma8.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma_lite10.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma_lite11.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma_lite12.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma_lite13.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma_lite14.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma_lite7.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma_lite8.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma_lite9.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_dma_top.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_performance0.h [new file with mode: 0644]
broadcom/bcm2708_chip/axi_performance1.h [new file with mode: 0644]
broadcom/bcm2708_chip/cam0.h [new file with mode: 0644]
broadcom/bcm2708_chip/cam0_a0.h [new file with mode: 0644]
broadcom/bcm2708_chip/cam1.h [new file with mode: 0644]
broadcom/bcm2708_chip/cam1_a0.h [new file with mode: 0644]
broadcom/bcm2708_chip/camccp.h [new file with mode: 0644]
broadcom/bcm2708_chip/ccp2tx.h [new file with mode: 0644]
broadcom/bcm2708_chip/ccp2tx_a0.h [new file with mode: 0644]
broadcom/bcm2708_chip/cdp.h [new file with mode: 0644]
broadcom/bcm2708_chip/clkman_image.h [new file with mode: 0644]
broadcom/bcm2708_chip/cpg.h [new file with mode: 0644]
broadcom/bcm2708_chip/cpi.h [new file with mode: 0644]
broadcom/bcm2708_chip/cpr_apb2wtap.h [new file with mode: 0644]
broadcom/bcm2708_chip/cpr_apb2wtap_a0.h [new file with mode: 0644]
broadcom/bcm2708_chip/cpr_clkman.h [new file with mode: 0644]
broadcom/bcm2708_chip/cpr_clkman_a0.h [new file with mode: 0644]
broadcom/bcm2708_chip/cpr_powman.h [new file with mode: 0644]
broadcom/bcm2708_chip/cpr_powman_a0.h [new file with mode: 0644]
broadcom/bcm2708_chip/cryptohw.h [new file with mode: 0644]
broadcom/bcm2708_chip/csi2.h [new file with mode: 0644]
broadcom/bcm2708_chip/dpi.h [new file with mode: 0644]
broadcom/bcm2708_chip/dsi.h [new file with mode: 0644]
broadcom/bcm2708_chip/dsi4.h [new file with mode: 0644]
broadcom/bcm2708_chip/emmc.h [new file with mode: 0644]
broadcom/bcm2708_chip/flow_config.tcl [new file with mode: 0644]
broadcom/bcm2708_chip/fpga_microblaze.h [new file with mode: 0644]
broadcom/bcm2708_chip/fpga_peripheral.h [new file with mode: 0644]
broadcom/bcm2708_chip/gpio.h [new file with mode: 0644]
broadcom/bcm2708_chip/h264.h [new file with mode: 0644]
broadcom/bcm2708_chip/hardware.h [new file with mode: 0644]
broadcom/bcm2708_chip/hdcp.h [new file with mode: 0644]
broadcom/bcm2708_chip/hdmi.h [new file with mode: 0644]
broadcom/bcm2708_chip/hdmicore.h [new file with mode: 0644]
broadcom/bcm2708_chip/hvs.h [new file with mode: 0644]
broadcom/bcm2708_chip/i2c0.h [new file with mode: 0644]
broadcom/bcm2708_chip/i2c1.h [new file with mode: 0644]
broadcom/bcm2708_chip/i2c2.h [new file with mode: 0644]
broadcom/bcm2708_chip/i2c_spi_slv.h [new file with mode: 0644]
broadcom/bcm2708_chip/intctrl0.h [new file with mode: 0644]
broadcom/bcm2708_chip/intctrl1.h [new file with mode: 0644]
broadcom/bcm2708_chip/isp.h [new file with mode: 0644]
broadcom/bcm2708_chip/israel_bg_dctram.h [new file with mode: 0644]
broadcom/bcm2708_chip/israel_bg_instr.h [new file with mode: 0644]
broadcom/bcm2708_chip/israel_dsp_registers.h [new file with mode: 0644]
broadcom/bcm2708_chip/jpeg_top.h [new file with mode: 0644]
broadcom/bcm2708_chip/l2_cache_ctrl.h [new file with mode: 0644]
broadcom/bcm2708_chip/mphi.h [new file with mode: 0644]
broadcom/bcm2708_chip/multicore_sync.h [new file with mode: 0644]
broadcom/bcm2708_chip/nexus_uba.h [new file with mode: 0644]
broadcom/bcm2708_chip/otp.h [new file with mode: 0644]
broadcom/bcm2708_chip/pcm.h [new file with mode: 0644]
broadcom/bcm2708_chip/perfmon.h [new file with mode: 0644]
broadcom/bcm2708_chip/peri_image_arb_ctrl.h [new file with mode: 0644]
broadcom/bcm2708_chip/pixel_valve0.h [new file with mode: 0644]
broadcom/bcm2708_chip/pixel_valve1.h [new file with mode: 0644]
broadcom/bcm2708_chip/pixel_valve2.h [new file with mode: 0644]
broadcom/bcm2708_chip/pwm.h [new file with mode: 0644]
broadcom/bcm2708_chip/register_map.h [new file with mode: 0644]
broadcom/bcm2708_chip/register_map_macros.h [new file with mode: 0644]
broadcom/bcm2708_chip/rng.h [new file with mode: 0644]
broadcom/bcm2708_chip/rng_a0.h [new file with mode: 0644]
broadcom/bcm2708_chip/rnghw.h [new file with mode: 0644]
broadcom/bcm2708_chip/sdc_addr_front.h [new file with mode: 0644]
broadcom/bcm2708_chip/sdc_ctrl.h [new file with mode: 0644]
broadcom/bcm2708_chip/sdc_dq_front.h [new file with mode: 0644]
broadcom/bcm2708_chip/sdhost.h [new file with mode: 0644]
broadcom/bcm2708_chip/slimbus.h [new file with mode: 0644]
broadcom/bcm2708_chip/slimbus_a0.h [new file with mode: 0644]
broadcom/bcm2708_chip/smi.h [new file with mode: 0644]
broadcom/bcm2708_chip/spi_master.h [new file with mode: 0644]
broadcom/bcm2708_chip/sv_chip_regmap.h [new file with mode: 0644]
broadcom/bcm2708_chip/system_arbiter_ctrl.h [new file with mode: 0644]
broadcom/bcm2708_chip/tectl.h [new file with mode: 0644]
broadcom/bcm2708_chip/tectl_a0.h [new file with mode: 0644]
broadcom/bcm2708_chip/tempsens.h [new file with mode: 0644]
broadcom/bcm2708_chip/testbus.h [new file with mode: 0644]
broadcom/bcm2708_chip/thread_ctrl.h [new file with mode: 0644]
broadcom/bcm2708_chip/timer.h [new file with mode: 0644]
broadcom/bcm2708_chip/txp.h [new file with mode: 0644]
broadcom/bcm2708_chip/uart.h [new file with mode: 0644]
broadcom/bcm2708_chip/usb.h [new file with mode: 0644]
broadcom/bcm2708_chip/v3d.h [new file with mode: 0644]
broadcom/bcm2708_chip/vcodec.h [new file with mode: 0644]
broadcom/bcm2708_chip/vec.h [new file with mode: 0644]
broadcom/bcm2708_chip/vpu_arb_ctrl.h [new file with mode: 0644]
broadcom/bcm2708_chip/vpu_l1_cache_ctrl.h [new file with mode: 0644]
broadcom/hardware_vc4.h [new file with mode: 0644]
hardware_vc4.h [deleted file]

diff --git a/bcm2708_chip/README.txt b/bcm2708_chip/README.txt
deleted file mode 100644 (file)
index 50d048b..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-This dir contains all the register map files for the design
-The bulk of it is created with the create_regs script  (run create_regs)  which
-parses the *_regs files in the hdl dirs and creates the individual files
-
-The top level file is chip/hdl/bcm2708_regs.tcl which defines the contents
-and off sets of the chip level memory map.
-
-Create regs then searches the dir tree for each object mentioned in bcm2708_regs.tcl
-and locates its   "object_regs.tcl"  file
-
-It then generates all the .h .inc ... files.
-
-These are then all lumped together in a  register_map.h  register_map.inc etc file
-
-
-
-The general procedure to modify this is
-
-
-
-check out all of chip/verification/code/vcinclude
-run create_regs  in this dir
-revert all unchanged files in  vcinclude
-check the modified ones and checkl them in if they are ok.
-
-
-Note:
-If create regs cant find a _regs.tcl file it will crash
-If it finds two files with the same name it will crash
diff --git a/bcm2708_chip/apb_arbiter_control.h b/bcm2708_chip/apb_arbiter_control.h
deleted file mode 100644 (file)
index a0f04fa..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-// This file was generated by the create_regs script
-#define ACR_BASE                                                 0x7e80a000
-#define ACR_APB_ID                                               0x61726272
-#define ACR_control                                              HW_REGISTER_RW( 0x7e80a000 ) 
-   #define ACR_control_MASK                                      0x0000ffff
-   #define ACR_control_WIDTH                                     16
-   #define ACR_control_RESET                                     0000000000
diff --git a/bcm2708_chip/apb_async_bridge_ctrl.h b/bcm2708_chip/apb_async_bridge_ctrl.h
deleted file mode 100644 (file)
index 339f473..0000000
+++ /dev/null
@@ -1,245 +0,0 @@
-// This file was generated by the create_regs script
-#define ASB_BASE                                                 0x7e00a000
-#define ASB_APB_ID                                               0x62726467
-#define ASB_AXI_BRDG_VERSION                                     HW_REGISTER_RW( 0x7e00a000 ) 
-   #define ASB_AXI_BRDG_VERSION_MASK                             0x000000ff
-   #define ASB_AXI_BRDG_VERSION_WIDTH                            8
-   #define ASB_AXI_BRDG_VERSION_RESET                            0000000000
-#define ASB_CPR_CTRL                                             HW_REGISTER_RW( 0x7e00a004 ) 
-   #define ASB_CPR_CTRL_MASK                                     0x00ffffff
-   #define ASB_CPR_CTRL_WIDTH                                    24
-   #define ASB_CPR_CTRL_RESET                                    0x00000007
-      #define ASB_CPR_CTRL_CLR_REQ_BITS                          0:0
-      #define ASB_CPR_CTRL_CLR_REQ_SET                           0x00000001
-      #define ASB_CPR_CTRL_CLR_REQ_CLR                           0xfffffffe
-      #define ASB_CPR_CTRL_CLR_REQ_MSB                           0
-      #define ASB_CPR_CTRL_CLR_REQ_LSB                           0
-      #define ASB_CPR_CTRL_CLR_ACK_BITS                          1:1
-      #define ASB_CPR_CTRL_CLR_ACK_SET                           0x00000002
-      #define ASB_CPR_CTRL_CLR_ACK_CLR                           0xfffffffd
-      #define ASB_CPR_CTRL_CLR_ACK_MSB                           1
-      #define ASB_CPR_CTRL_CLR_ACK_LSB                           1
-      #define ASB_CPR_CTRL_EMPTY_BITS                            2:2
-      #define ASB_CPR_CTRL_EMPTY_SET                             0x00000004
-      #define ASB_CPR_CTRL_EMPTY_CLR                             0xfffffffb
-      #define ASB_CPR_CTRL_EMPTY_MSB                             2
-      #define ASB_CPR_CTRL_EMPTY_LSB                             2
-      #define ASB_CPR_CTRL_FULL_BITS                             3:3
-      #define ASB_CPR_CTRL_FULL_SET                              0x00000008
-      #define ASB_CPR_CTRL_FULL_CLR                              0xfffffff7
-      #define ASB_CPR_CTRL_FULL_MSB                              3
-      #define ASB_CPR_CTRL_FULL_LSB                              3
-      #define ASB_CPR_CTRL_RCOUNT_BITS                           13:4
-      #define ASB_CPR_CTRL_RCOUNT_SET                            0x00003ff0
-      #define ASB_CPR_CTRL_RCOUNT_CLR                            0xffffc00f
-      #define ASB_CPR_CTRL_RCOUNT_MSB                            13
-      #define ASB_CPR_CTRL_RCOUNT_LSB                            4
-      #define ASB_CPR_CTRL_WCOUNT_BITS                           23:14
-      #define ASB_CPR_CTRL_WCOUNT_SET                            0x00ffc000
-      #define ASB_CPR_CTRL_WCOUNT_CLR                            0xff003fff
-      #define ASB_CPR_CTRL_WCOUNT_MSB                            23
-      #define ASB_CPR_CTRL_WCOUNT_LSB                            14
-#define ASB_V3D_S_CTRL                                           HW_REGISTER_RW( 0x7e00a008 ) 
-   #define ASB_V3D_S_CTRL_MASK                                   0x00ffffff
-   #define ASB_V3D_S_CTRL_WIDTH                                  24
-   #define ASB_V3D_S_CTRL_RESET                                  0x00000007
-      #define ASB_V3D_S_CTRL_CLR_REQ_BITS                        0:0
-      #define ASB_V3D_S_CTRL_CLR_REQ_SET                         0x00000001
-      #define ASB_V3D_S_CTRL_CLR_REQ_CLR                         0xfffffffe
-      #define ASB_V3D_S_CTRL_CLR_REQ_MSB                         0
-      #define ASB_V3D_S_CTRL_CLR_REQ_LSB                         0
-      #define ASB_V3D_S_CTRL_CLR_ACK_BITS                        1:1
-      #define ASB_V3D_S_CTRL_CLR_ACK_SET                         0x00000002
-      #define ASB_V3D_S_CTRL_CLR_ACK_CLR                         0xfffffffd
-      #define ASB_V3D_S_CTRL_CLR_ACK_MSB                         1
-      #define ASB_V3D_S_CTRL_CLR_ACK_LSB                         1
-      #define ASB_V3D_S_CTRL_EMPTY_BITS                          2:2
-      #define ASB_V3D_S_CTRL_EMPTY_SET                           0x00000004
-      #define ASB_V3D_S_CTRL_EMPTY_CLR                           0xfffffffb
-      #define ASB_V3D_S_CTRL_EMPTY_MSB                           2
-      #define ASB_V3D_S_CTRL_EMPTY_LSB                           2
-      #define ASB_V3D_S_CTRL_FULL_BITS                           3:3
-      #define ASB_V3D_S_CTRL_FULL_SET                            0x00000008
-      #define ASB_V3D_S_CTRL_FULL_CLR                            0xfffffff7
-      #define ASB_V3D_S_CTRL_FULL_MSB                            3
-      #define ASB_V3D_S_CTRL_FULL_LSB                            3
-      #define ASB_V3D_S_CTRL_RCOUNT_BITS                         13:4
-      #define ASB_V3D_S_CTRL_RCOUNT_SET                          0x00003ff0
-      #define ASB_V3D_S_CTRL_RCOUNT_CLR                          0xffffc00f
-      #define ASB_V3D_S_CTRL_RCOUNT_MSB                          13
-      #define ASB_V3D_S_CTRL_RCOUNT_LSB                          4
-      #define ASB_V3D_S_CTRL_WCOUNT_BITS                         23:14
-      #define ASB_V3D_S_CTRL_WCOUNT_SET                          0x00ffc000
-      #define ASB_V3D_S_CTRL_WCOUNT_CLR                          0xff003fff
-      #define ASB_V3D_S_CTRL_WCOUNT_MSB                          23
-      #define ASB_V3D_S_CTRL_WCOUNT_LSB                          14
-#define ASB_V3D_M_CTRL                                           HW_REGISTER_RW( 0x7e00a00c ) 
-   #define ASB_V3D_M_CTRL_MASK                                   0x00ffffff
-   #define ASB_V3D_M_CTRL_WIDTH                                  24
-   #define ASB_V3D_M_CTRL_RESET                                  0x00000007
-      #define ASB_V3D_M_CTRL_CLR_REQ_BITS                        0:0
-      #define ASB_V3D_M_CTRL_CLR_REQ_SET                         0x00000001
-      #define ASB_V3D_M_CTRL_CLR_REQ_CLR                         0xfffffffe
-      #define ASB_V3D_M_CTRL_CLR_REQ_MSB                         0
-      #define ASB_V3D_M_CTRL_CLR_REQ_LSB                         0
-      #define ASB_V3D_M_CTRL_CLR_ACK_BITS                        1:1
-      #define ASB_V3D_M_CTRL_CLR_ACK_SET                         0x00000002
-      #define ASB_V3D_M_CTRL_CLR_ACK_CLR                         0xfffffffd
-      #define ASB_V3D_M_CTRL_CLR_ACK_MSB                         1
-      #define ASB_V3D_M_CTRL_CLR_ACK_LSB                         1
-      #define ASB_V3D_M_CTRL_EMPTY_BITS                          2:2
-      #define ASB_V3D_M_CTRL_EMPTY_SET                           0x00000004
-      #define ASB_V3D_M_CTRL_EMPTY_CLR                           0xfffffffb
-      #define ASB_V3D_M_CTRL_EMPTY_MSB                           2
-      #define ASB_V3D_M_CTRL_EMPTY_LSB                           2
-      #define ASB_V3D_M_CTRL_FULL_BITS                           3:3
-      #define ASB_V3D_M_CTRL_FULL_SET                            0x00000008
-      #define ASB_V3D_M_CTRL_FULL_CLR                            0xfffffff7
-      #define ASB_V3D_M_CTRL_FULL_MSB                            3
-      #define ASB_V3D_M_CTRL_FULL_LSB                            3
-      #define ASB_V3D_M_CTRL_RCOUNT_BITS                         13:4
-      #define ASB_V3D_M_CTRL_RCOUNT_SET                          0x00003ff0
-      #define ASB_V3D_M_CTRL_RCOUNT_CLR                          0xffffc00f
-      #define ASB_V3D_M_CTRL_RCOUNT_MSB                          13
-      #define ASB_V3D_M_CTRL_RCOUNT_LSB                          4
-      #define ASB_V3D_M_CTRL_WCOUNT_BITS                         23:14
-      #define ASB_V3D_M_CTRL_WCOUNT_SET                          0x00ffc000
-      #define ASB_V3D_M_CTRL_WCOUNT_CLR                          0xff003fff
-      #define ASB_V3D_M_CTRL_WCOUNT_MSB                          23
-      #define ASB_V3D_M_CTRL_WCOUNT_LSB                          14
-#define ASB_ISP_S_CTRL                                           HW_REGISTER_RW( 0x7e00a010 ) 
-   #define ASB_ISP_S_CTRL_MASK                                   0x00ffffff
-   #define ASB_ISP_S_CTRL_WIDTH                                  24
-   #define ASB_ISP_S_CTRL_RESET                                  0x00000007
-      #define ASB_ISP_S_CTRL_CLR_REQ_BITS                        0:0
-      #define ASB_ISP_S_CTRL_CLR_REQ_SET                         0x00000001
-      #define ASB_ISP_S_CTRL_CLR_REQ_CLR                         0xfffffffe
-      #define ASB_ISP_S_CTRL_CLR_REQ_MSB                         0
-      #define ASB_ISP_S_CTRL_CLR_REQ_LSB                         0
-      #define ASB_ISP_S_CTRL_CLR_ACK_BITS                        1:1
-      #define ASB_ISP_S_CTRL_CLR_ACK_SET                         0x00000002
-      #define ASB_ISP_S_CTRL_CLR_ACK_CLR                         0xfffffffd
-      #define ASB_ISP_S_CTRL_CLR_ACK_MSB                         1
-      #define ASB_ISP_S_CTRL_CLR_ACK_LSB                         1
-      #define ASB_ISP_S_CTRL_EMPTY_BITS                          2:2
-      #define ASB_ISP_S_CTRL_EMPTY_SET                           0x00000004
-      #define ASB_ISP_S_CTRL_EMPTY_CLR                           0xfffffffb
-      #define ASB_ISP_S_CTRL_EMPTY_MSB                           2
-      #define ASB_ISP_S_CTRL_EMPTY_LSB                           2
-      #define ASB_ISP_S_CTRL_FULL_BITS                           3:3
-      #define ASB_ISP_S_CTRL_FULL_SET                            0x00000008
-      #define ASB_ISP_S_CTRL_FULL_CLR                            0xfffffff7
-      #define ASB_ISP_S_CTRL_FULL_MSB                            3
-      #define ASB_ISP_S_CTRL_FULL_LSB                            3
-      #define ASB_ISP_S_CTRL_RCOUNT_BITS                         13:4
-      #define ASB_ISP_S_CTRL_RCOUNT_SET                          0x00003ff0
-      #define ASB_ISP_S_CTRL_RCOUNT_CLR                          0xffffc00f
-      #define ASB_ISP_S_CTRL_RCOUNT_MSB                          13
-      #define ASB_ISP_S_CTRL_RCOUNT_LSB                          4
-      #define ASB_ISP_S_CTRL_WCOUNT_BITS                         23:14
-      #define ASB_ISP_S_CTRL_WCOUNT_SET                          0x00ffc000
-      #define ASB_ISP_S_CTRL_WCOUNT_CLR                          0xff003fff
-      #define ASB_ISP_S_CTRL_WCOUNT_MSB                          23
-      #define ASB_ISP_S_CTRL_WCOUNT_LSB                          14
-#define ASB_ISP_M_CTRL                                           HW_REGISTER_RW( 0x7e00a014 ) 
-   #define ASB_ISP_M_CTRL_MASK                                   0x00ffffff
-   #define ASB_ISP_M_CTRL_WIDTH                                  24
-   #define ASB_ISP_M_CTRL_RESET                                  0x00000007
-      #define ASB_ISP_M_CTRL_CLR_REQ_BITS                        0:0
-      #define ASB_ISP_M_CTRL_CLR_REQ_SET                         0x00000001
-      #define ASB_ISP_M_CTRL_CLR_REQ_CLR                         0xfffffffe
-      #define ASB_ISP_M_CTRL_CLR_REQ_MSB                         0
-      #define ASB_ISP_M_CTRL_CLR_REQ_LSB                         0
-      #define ASB_ISP_M_CTRL_CLR_ACK_BITS                        1:1
-      #define ASB_ISP_M_CTRL_CLR_ACK_SET                         0x00000002
-      #define ASB_ISP_M_CTRL_CLR_ACK_CLR                         0xfffffffd
-      #define ASB_ISP_M_CTRL_CLR_ACK_MSB                         1
-      #define ASB_ISP_M_CTRL_CLR_ACK_LSB                         1
-      #define ASB_ISP_M_CTRL_EMPTY_BITS                          2:2
-      #define ASB_ISP_M_CTRL_EMPTY_SET                           0x00000004
-      #define ASB_ISP_M_CTRL_EMPTY_CLR                           0xfffffffb
-      #define ASB_ISP_M_CTRL_EMPTY_MSB                           2
-      #define ASB_ISP_M_CTRL_EMPTY_LSB                           2
-      #define ASB_ISP_M_CTRL_FULL_BITS                           3:3
-      #define ASB_ISP_M_CTRL_FULL_SET                            0x00000008
-      #define ASB_ISP_M_CTRL_FULL_CLR                            0xfffffff7
-      #define ASB_ISP_M_CTRL_FULL_MSB                            3
-      #define ASB_ISP_M_CTRL_FULL_LSB                            3
-      #define ASB_ISP_M_CTRL_RCOUNT_BITS                         13:4
-      #define ASB_ISP_M_CTRL_RCOUNT_SET                          0x00003ff0
-      #define ASB_ISP_M_CTRL_RCOUNT_CLR                          0xffffc00f
-      #define ASB_ISP_M_CTRL_RCOUNT_MSB                          13
-      #define ASB_ISP_M_CTRL_RCOUNT_LSB                          4
-      #define ASB_ISP_M_CTRL_WCOUNT_BITS                         23:14
-      #define ASB_ISP_M_CTRL_WCOUNT_SET                          0x00ffc000
-      #define ASB_ISP_M_CTRL_WCOUNT_CLR                          0xff003fff
-      #define ASB_ISP_M_CTRL_WCOUNT_MSB                          23
-      #define ASB_ISP_M_CTRL_WCOUNT_LSB                          14
-#define ASB_H264_S_CTRL                                          HW_REGISTER_RW( 0x7e00a018 ) 
-   #define ASB_H264_S_CTRL_MASK                                  0x00ffffff
-   #define ASB_H264_S_CTRL_WIDTH                                 24
-   #define ASB_H264_S_CTRL_RESET                                 0x00000007
-      #define ASB_H264_S_CTRL_CLR_REQ_BITS                       0:0
-      #define ASB_H264_S_CTRL_CLR_REQ_SET                        0x00000001
-      #define ASB_H264_S_CTRL_CLR_REQ_CLR                        0xfffffffe
-      #define ASB_H264_S_CTRL_CLR_REQ_MSB                        0
-      #define ASB_H264_S_CTRL_CLR_REQ_LSB                        0
-      #define ASB_H264_S_CTRL_CLR_ACK_BITS                       1:1
-      #define ASB_H264_S_CTRL_CLR_ACK_SET                        0x00000002
-      #define ASB_H264_S_CTRL_CLR_ACK_CLR                        0xfffffffd
-      #define ASB_H264_S_CTRL_CLR_ACK_MSB                        1
-      #define ASB_H264_S_CTRL_CLR_ACK_LSB                        1
-      #define ASB_H264_S_CTRL_EMPTY_BITS                         2:2
-      #define ASB_H264_S_CTRL_EMPTY_SET                          0x00000004
-      #define ASB_H264_S_CTRL_EMPTY_CLR                          0xfffffffb
-      #define ASB_H264_S_CTRL_EMPTY_MSB                          2
-      #define ASB_H264_S_CTRL_EMPTY_LSB                          2
-      #define ASB_H264_S_CTRL_FULL_BITS                          3:3
-      #define ASB_H264_S_CTRL_FULL_SET                           0x00000008
-      #define ASB_H264_S_CTRL_FULL_CLR                           0xfffffff7
-      #define ASB_H264_S_CTRL_FULL_MSB                           3
-      #define ASB_H264_S_CTRL_FULL_LSB                           3
-      #define ASB_H264_S_CTRL_RCOUNT_BITS                        13:4
-      #define ASB_H264_S_CTRL_RCOUNT_SET                         0x00003ff0
-      #define ASB_H264_S_CTRL_RCOUNT_CLR                         0xffffc00f
-      #define ASB_H264_S_CTRL_RCOUNT_MSB                         13
-      #define ASB_H264_S_CTRL_RCOUNT_LSB                         4
-      #define ASB_H264_S_CTRL_WCOUNT_BITS                        23:14
-      #define ASB_H264_S_CTRL_WCOUNT_SET                         0x00ffc000
-      #define ASB_H264_S_CTRL_WCOUNT_CLR                         0xff003fff
-      #define ASB_H264_S_CTRL_WCOUNT_MSB                         23
-      #define ASB_H264_S_CTRL_WCOUNT_LSB                         14
-#define ASB_H264_M_CTRL                                          HW_REGISTER_RW( 0x7e00a01c ) 
-   #define ASB_H264_M_CTRL_MASK                                  0x00ffffff
-   #define ASB_H264_M_CTRL_WIDTH                                 24
-   #define ASB_H264_M_CTRL_RESET                                 0x00000007
-      #define ASB_H264_M_CTRL_CLR_REQ_BITS                       0:0
-      #define ASB_H264_M_CTRL_CLR_REQ_SET                        0x00000001
-      #define ASB_H264_M_CTRL_CLR_REQ_CLR                        0xfffffffe
-      #define ASB_H264_M_CTRL_CLR_REQ_MSB                        0
-      #define ASB_H264_M_CTRL_CLR_REQ_LSB                        0
-      #define ASB_H264_M_CTRL_CLR_ACK_BITS                       1:1
-      #define ASB_H264_M_CTRL_CLR_ACK_SET                        0x00000002
-      #define ASB_H264_M_CTRL_CLR_ACK_CLR                        0xfffffffd
-      #define ASB_H264_M_CTRL_CLR_ACK_MSB                        1
-      #define ASB_H264_M_CTRL_CLR_ACK_LSB                        1
-      #define ASB_H264_M_CTRL_EMPTY_BITS                         2:2
-      #define ASB_H264_M_CTRL_EMPTY_SET                          0x00000004
-      #define ASB_H264_M_CTRL_EMPTY_CLR                          0xfffffffb
-      #define ASB_H264_M_CTRL_EMPTY_MSB                          2
-      #define ASB_H264_M_CTRL_EMPTY_LSB                          2
-      #define ASB_H264_M_CTRL_FULL_BITS                          3:3
-      #define ASB_H264_M_CTRL_FULL_SET                           0x00000008
-      #define ASB_H264_M_CTRL_FULL_CLR                           0xfffffff7
-      #define ASB_H264_M_CTRL_FULL_MSB                           3
-      #define ASB_H264_M_CTRL_FULL_LSB                           3
-      #define ASB_H264_M_CTRL_RCOUNT_BITS                        13:4
-      #define ASB_H264_M_CTRL_RCOUNT_SET                         0x00003ff0
-      #define ASB_H264_M_CTRL_RCOUNT_CLR                         0xffffc00f
-      #define ASB_H264_M_CTRL_RCOUNT_MSB                         13
-      #define ASB_H264_M_CTRL_RCOUNT_LSB                         4
-      #define ASB_H264_M_CTRL_WCOUNT_BITS                        23:14
-      #define ASB_H264_M_CTRL_WCOUNT_SET                         0x00ffc000
-      #define ASB_H264_M_CTRL_WCOUNT_CLR                         0xff003fff
-      #define ASB_H264_M_CTRL_WCOUNT_MSB                         23
-      #define ASB_H264_M_CTRL_WCOUNT_LSB                         14
diff --git a/bcm2708_chip/arm_control.h b/bcm2708_chip/arm_control.h
deleted file mode 100644 (file)
index 8d249dc..0000000
+++ /dev/null
@@ -1,404 +0,0 @@
-//
-// Definitions and addresses forthe ARM CONTROL logic
-// This file is manually generated.
-//
-//
-
-#define ARM_BASE  0x7E00B000
-
-// Basic configuration
-#define ARM_CONTROL0  HW_REGISTER_RW(ARM_BASE+0x000)
-#define ARM_C0_SIZ128M   0x00000000
-#define ARM_C0_SIZ256M   0x00000001
-#define ARM_C0_SIZ512M   0x00000002
-#define ARM_C0_SIZ1G     0x00000003
-#define ARM_C0_BRESP0    0x00000000
-#define ARM_C0_BRESP1    0x00000004
-#define ARM_C0_BRESP2    0x00000008
-#define ARM_C0_BOOTHI    0x00000010
-#define ARM_C0_UNUSED05  0x00000020 // free
-#define ARM_C0_FULLPERI  0x00000040
-#define ARM_C0_UNUSED78  0x00000180 // free
-#define ARM_C0_JTAGMASK  0x00000E00
-#define ARM_C0_JTAGOFF   0x00000000
-#define ARM_C0_JTAGBASH  0x00000800 // Debug on GPIO off
-#define ARM_C0_JTAGGPIO  0x00000C00 // Debug on GPIO on
-#define ARM_C0_APROTMSK  0x0000F000
-#define ARM_C0_DBG0SYNC  0x00010000 // VPU0 halt sync
-#define ARM_C0_DBG1SYNC  0x00020000 // VPU1 halt sync
-#define ARM_C0_SWDBGREQ  0x00040000 // HW debug request
-#define ARM_C0_PASSHALT  0x00080000 // ARM halt passed to debugger
-#define ARM_C0_PRIO_PER  0x00F00000 // per priority mask
-#define ARM_C0_PRIO_L2   0x0F000000
-#define ARM_C0_PRIO_UC   0xF0000000
-
-#define ARM_C0_APROTPASS  0x0000A000 // Translate 1:1
-#define ARM_C0_APROTUSER  0x00000000 // Only user mode
-#define ARM_C0_APROTSYST  0x0000F000 // Only system mode
-
-
-#define ARM_CONTROL1  HW_REGISTER_RW(ARM_BASE+0x440)
-#define ARM_C1_TIMER     0x00000001 // re-route timer IRQ  to VC
-#define ARM_C1_MAIL      0x00000002 // re-route Mail IRQ   to VC
-#define ARM_C1_BELL0     0x00000004 // re-route Doorbell 0 to VC
-#define ARM_C1_BELL1     0x00000008 // re-route Doorbell 1 to VC
-#define ARM_C1_PERSON    0x00000100 // peripherals on
-#define ARM_C1_REQSTOP   0x00000200 // ASYNC bridge request stop
-
-#define ARM_STATUS    HW_REGISTER_RW(ARM_BASE+0x444)
-#define ARM_S_ACKSTOP    0x80000000 // Bridge stopped
-#define ARM_S_READPEND   0x000003FF // pending reads counter
-#define ARM_S_WRITPEND   0x000FFC00 // pending writes counter
-
-#define ARM_ERRHALT   HW_REGISTER_RW(ARM_BASE+0x448)
-#define ARM_EH_PERIBURST  0x00000001 // Burst write seen on peri bus
-#define ARM_EH_ILLADDRS1  0x00000002 // Address bits 25-27 error
-#define ARM_EH_ILLADDRS2  0x00000004 // Address bits 31-28 error
-#define ARM_EH_VPU0HALT   0x00000008 // VPU0 halted & in debug mode
-#define ARM_EH_VPU1HALT   0x00000010 // VPU1 halted & in debug mode
-#define ARM_EH_ARMHALT    0x00000020 // ARM in halted debug mode
-
-#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
-#define ARM_ID        HW_REGISTER_RW(ARM_BASE+0x44C)
-#define ARM_IDVAL        0x364D5241
-
-// Translation memory
-#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
-// 32 locations: 0x100.. 0x17F
-// 32 spare means we CAN go to 64 pages....
-
-
-// Interrupts
-#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200)        // Top IRQ bits
-#define ARM_I0_TIMER    0x00000001 // timer IRQ
-#define ARM_I0_MAIL     0x00000002 // Mail IRQ
-#define ARM_I0_BELL0    0x00000004 // Doorbell 0
-#define ARM_I0_BELL1    0x00000008 // Doorbell 1
-#define ARM_I0_BANK1    0x00000100 // Bank1 IRQ
-#define ARM_I0_BANK2    0x00000200 // Bank2 IRQ
-
-#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) // All bank1 IRQ bits
-// todo: all I1_interrupt sources
-#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) // All bank2 IRQ bits
-// todo: all I2_interrupt sources
-
-#define ARM_IRQ_FAST  HW_REGISTER_RW(ARM_BASE+0x20C) // FIQ control
-#define ARM_IF_INDEX    0x0000007F     // FIQ select
-#define ARM_IF_ENABLE   0x00000080     // FIQ enable
-#define ARM_IF_VCMASK   0x0000003F     // FIQ = (index from VC source)
-#define ARM_IF_TIMER    0x00000040     // FIQ = ARM timer
-#define ARM_IF_MAIL     0x00000041     // FIQ = ARM Mail
-#define ARM_IF_BELL0    0x00000042     // FIQ = ARM Doorbell 0
-#define ARM_IF_BELL1    0x00000043     // FIQ = ARM Doorbell 1
-#define ARM_IF_VP0HALT  0x00000044     // FIQ = VPU0 Halt seen
-#define ARM_IF_VP1HALT  0x00000045     // FIQ = VPU1 Halt seen
-#define ARM_IF_ILLEGAL  0x00000046     // FIQ = Illegal access seen
-
-#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) // Bank1 enable bits
-#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) // Bank2 enable bits
-#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) // ARM irqs enable bits
-#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) // Bank1 disable bits
-#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) // Bank2 disable bits
-#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) // ARM irqs disable bits
-#define ARM_IE_TIMER    0x00000001     // Timer IRQ
-#define ARM_IE_MAIL     0x00000002     // Mail IRQ
-#define ARM_IE_BELL0    0x00000004     // Doorbell 0
-#define ARM_IE_BELL1    0x00000008     // Doorbell 1
-#define ARM_IE_VP0HALT  0x00000010     // VPU0 Halt
-#define ARM_IE_VP1HALT  0x00000020     // VPU1 Halt
-#define ARM_IE_ILLEGAL  0x00000040     // Illegal access seen
-
-// Timer
-// For reg. fields see sp804 spec.
-#define ARM_T_LOAD    HW_REGISTER_RW(ARM_BASE+0x400)
-#define ARM_T_VALUE   HW_REGISTER_RW(ARM_BASE+0x404)
-#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
-#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
-#define ARM_T_RAWIRQ  HW_REGISTER_RW(ARM_BASE+0x410)
-#define ARM_T_MSKIRQ  HW_REGISTER_RW(ARM_BASE+0x414)
-#define ARM_T_RELOAD  HW_REGISTER_RW(ARM_BASE+0x418)
-#define ARM_T_PREDIV  HW_REGISTER_RW(ARM_BASE+0x41c)
-#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
-
-#define TIMER_CTRL_ONESHOT  (1 << 0)
-#define TIMER_CTRL_32BIT    (1 << 1)
-#define TIMER_CTRL_DIV1     (0 << 2)
-#define TIMER_CTRL_DIV16    (1 << 2)
-#define TIMER_CTRL_DIV256   (2 << 2)
-#define TIMER_CTRL_IE       (1 << 5)
-#define TIMER_CTRL_PERIODIC (1 << 6)
-#define TIMER_CTRL_ENABLE   (1 << 7)
-#define TIMER_CTRL_DBGHALT  (1 << 8)
-#define TIMER_CTRL_ENAFREE  (1 << 9)
-#define TIMER_CTRL_FREEDIV_SHIFT 16)
-#define TIMER_CTRL_FREEDIV_MASK  0xff
-
-//
-// Semaphores, Doorbells, Mailboxes
-#define ARM_SBM_OWN0  (ARM_BASE+0x800)
-#define ARM_SBM_OWN1  (ARM_BASE+0x900)
-#define ARM_SBM_OWN2  (ARM_BASE+0xA00)
-#define ARM_SBM_OWN3  (ARM_BASE+0xB00)
-
-//
-// MAILBOXES
-// Register flags are common across all
-// owner registers. See end of this section
-//=========================================
-// Semaphores, Doorbells, Mailboxes Owner 0
-//=========================================
-#define ARM_0_SEMS       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
-#define ARM_0_SEM0       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
-#define ARM_0_SEM1       HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
-#define ARM_0_SEM2       HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
-#define ARM_0_SEM3       HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
-#define ARM_0_SEM4       HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
-#define ARM_0_SEM5       HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
-#define ARM_0_SEM6       HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
-#define ARM_0_SEM7       HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
-#define ARM_0_BELL0      HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
-#define ARM_0_BELL1      HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
-#define ARM_0_BELL2      HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
-#define ARM_0_BELL3      HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
-// MAILBOX 0 access in Owner 0 area
-// Some addresses should ONLY be used by owner 0
-#define ARM_0_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  // .. 0x8C (4 locations)
-#define ARM_0_MAIL0_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  // .. 0x8C (4 locations) Normal read
-#define ARM_0_MAIL0_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0x90)  // none-pop read
-#define ARM_0_MAIL0_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0x94)  // Sender read (only LS 2 bits)
-#define ARM_0_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0x98)  // Status read
-#define ARM_0_MAIL0_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0x9C)  // Config read/write
-// MAILBOX 1 access in Owner 0 area
-// Owner 0 should only WRITE to this mailbox
-#define ARM_0_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0xA0)   // .. 0xAC (4 locations)
-//#define ARM_0_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) // DO NOT USE THIS !!!!!
-//#define ARM_0_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) // DO NOT USE THIS !!!!!
-//#define ARM_0_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) // DO NOT USE THIS !!!!!
-#define ARM_0_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0xB8)   // Status read
-//#define ARM_0_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) // DO NOT USE THIS !!!!!
-// General SEM, BELL, MAIL config/status
-#define ARM_0_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN0+0xE0)  // semaphore clear/debug register
-#define ARM_0_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN0+0xE4)  // Doorbells clear/debug register
-#define ARM_0_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN0+0xF8)  // ALL interrupts
-#define ARM_0_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN0+0xFC)  // IRQS pending for owner 0
-
-// Semaphores, Doorbells, Mailboxes Owner 1
-//=========================================
-#define ARM_1_SEMS       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
-#define ARM_1_SEM0       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
-#define ARM_1_SEM1       HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
-#define ARM_1_SEM2       HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
-#define ARM_1_SEM3       HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
-#define ARM_1_SEM4       HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
-#define ARM_1_SEM5       HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
-#define ARM_1_SEM6       HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
-#define ARM_1_SEM7       HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
-#define ARM_1_BELL0      HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
-#define ARM_1_BELL1      HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
-#define ARM_1_BELL2      HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
-#define ARM_1_BELL3      HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
-// MAILBOX 0 access in Owner 0 area
-// Owner 1 should only WRITE to this mailbox
-#define ARM_1_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0x80)  // .. 0x8C (4 locations)
-//#define ARM_1_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN1+0x80) // DO NOT USE THIS !!!!!
-//#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) // DO NOT USE THIS !!!!!
-//#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) // DO NOT USE THIS !!!!!
-#define ARM_1_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0x98)  // Status read
-//#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) // DO NOT USE THIS !!!!!
-// MAILBOX 1 access in Owner 0 area
-#define ARM_1_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  // .. 0xAC (4 locations)
-#define ARM_1_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  // .. 0xAC (4 locations) Normal read
-#define ARM_1_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN1+0xB0)  // none-pop read
-#define ARM_1_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN1+0xB4)  // Sender read (only LS 2 bits)
-#define ARM_1_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0xB8)  // Status read
-#define ARM_1_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
-// General SEM, BELL, MAIL config/status
-#define ARM_1_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN1+0xE0)  // semaphore clear/debug register
-#define ARM_1_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN1+0xE4)  // Doorbells clear/debug register
-#define ARM_1_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN1+0xFC)  // IRQS pending for owner 1
-#define ARM_1_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN1+0xF8)  // ALL interrupts
-
-// Semaphores, Doorbells, Mailboxes Owner 2
-//=========================================
-#define ARM_2_SEMS       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
-#define ARM_2_SEM0       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
-#define ARM_2_SEM1       HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
-#define ARM_2_SEM2       HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
-#define ARM_2_SEM3       HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
-#define ARM_2_SEM4       HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
-#define ARM_2_SEM5       HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
-#define ARM_2_SEM6       HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
-#define ARM_2_SEM7       HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
-#define ARM_2_BELL0      HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
-#define ARM_2_BELL1      HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
-#define ARM_2_BELL2      HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
-#define ARM_2_BELL3      HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
-// MAILBOX 0 access in Owner 2 area
-// Owner 2 should only WRITE to this mailbox
-#define ARM_2_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)   // .. 0x8C (4 locations)
-//#define ARM_2_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)  // DO NOT USE THIS !!!!!
-//#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90)  // DO NOT USE THIS !!!!!
-//#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94)  // DO NOT USE THIS !!!!!
-#define ARM_2_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0x98)   // Status read
-//#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C)  // DO NOT USE THIS !!!!!
-// MAILBOX 1 access in Owner 2 area
-// Owner 2 should only WRITE to this mailbox
-#define ARM_2_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0xA0)   // .. 0xAC (4 locations)
-//#define ARM_2_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) // DO NOT USE THIS !!!!!
-//#define ARM_2_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) // DO NOT USE THIS !!!!!
-//#define ARM_2_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) // DO NOT USE THIS !!!!!
-#define ARM_2_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0xB8)   // Status read
-//#define ARM_2_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) // DO NOT USE THIS !!!!!
-// General SEM, BELL, MAIL config/status
-#define ARM_2_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN2+0xE0)  // semaphore clear/debug register
-#define ARM_2_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN2+0xE4)  // Doorbells clear/debug register
-#define ARM_2_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN2+0xFC)  // IRQS pending for owner 2
-#define ARM_2_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN2+0xF8)  // ALL interrupts
-
-// Semaphores, Doorbells, Mailboxes Owner 3
-//=========================================
-#define ARM_3_SEMS       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
-#define ARM_3_SEM0       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
-#define ARM_3_SEM1       HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
-#define ARM_3_SEM2       HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
-#define ARM_3_SEM3       HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
-#define ARM_3_SEM4       HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
-#define ARM_3_SEM5       HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
-#define ARM_3_SEM6       HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
-#define ARM_3_SEM7       HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
-#define ARM_3_BELL0      HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
-#define ARM_3_BELL1      HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
-#define ARM_3_BELL2      HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
-#define ARM_3_BELL3      HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
-// MAILBOX 0 access in Owner 3 area
-// Owner 3 should only WRITE to this mailbox
-#define ARM_3_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)   // .. 0x8C (4 locations)
-//#define ARM_3_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)  // DO NOT USE THIS !!!!!
-//#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90)  // DO NOT USE THIS !!!!!
-//#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94)  // DO NOT USE THIS !!!!!
-#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98)    // Status read
-//#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C)  // DO NOT USE THIS !!!!!
-// MAILBOX 1 access in Owner 3 area
-// Owner 3 should only WRITE to this mailbox
-#define ARM_3_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0xA0)   // .. 0xAC (4 locations)
-//#define ARM_3_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) // DO NOT USE THIS !!!!!
-//#define ARM_3_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) // DO NOT USE THIS !!!!!
-//#define ARM_3_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) // DO NOT USE THIS !!!!!
-#define ARM_3_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN3+0xB8)   // Status read
-//#define ARM_3_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) // DO NOT USE THIS !!!!!
-// General SEM, BELL, MAIL config/status
-#define ARM_3_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN3+0xE0)  // semaphore clear/debug register
-#define ARM_3_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN3+0xE4)  // Doorbells clear/debug register
-#define ARM_3_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN3+0xFC)  // IRQS pending for owner 3
-#define ARM_3_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN3+0xF8)  // ALL interrupts
-
-
-
-///////////////////////////////////////////
-//  MAILBOX FLAGS. VALID FOR ALL OWNERS  //
-///////////////////////////////////////////
-
-// MAILBOX status register (...0x98)
-#define ARM_MS_FULL       0x80000000
-#define ARM_MS_EMPTY      0x40000000
-#define ARM_MS_LEVEL      0x400000FF // Max. value depdnds on mailbox depth parameter
-
-// MAILBOX config/status register (...0x9C)
-// ANY write to this register clears the error bits!
-#define ARM_MC_IHAVEDATAIRQEN    0x00000001 // mailbox irq enable:  has data
-#define ARM_MC_IHAVESPACEIRQEN   0x00000002 // mailbox irq enable:  has space
-#define ARM_MC_OPPISEMPTYIRQEN   0x00000004 // mailbox irq enable: Opp. is empty
-#define ARM_MC_MAIL_CLEAR        0x00000008 // mailbox clear write 1, then  0
-#define ARM_MC_IHAVEDATAIRQPEND  0x00000010 // mailbox irq pending:  has space
-#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 // mailbox irq pending: Opp. is empty
-#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 // mailbox irq pending
-// Bit 7 is unused
-#define ARM_MC_ERRNOOWN   0x00000100 // error : none owner read from mailbox
-#define ARM_MC_ERROVERFLW 0x00000200 // error : write to fill mailbox
-#define ARM_MC_ERRUNDRFLW 0x00000400 // error : read from empty mailbox
-
-// Semaphore clear/debug register (...0xE0)
-#define ARM_SD_OWN0      0x00000003  // Owner of sem 0
-#define ARM_SD_OWN1      0x0000000C  // Owner of sem 1
-#define ARM_SD_OWN2      0x00000030  // Owner of sem 2
-#define ARM_SD_OWN3      0x000000C0  // Owner of sem 3
-#define ARM_SD_OWN4      0x00000300  // Owner of sem 4
-#define ARM_SD_OWN5      0x00000C00  // Owner of sem 5
-#define ARM_SD_OWN6      0x00003000  // Owner of sem 6
-#define ARM_SD_OWN7      0x0000C000  // Owner of sem 7
-#define ARM_SD_SEM0      0x00010000  // Status of sem 0
-#define ARM_SD_SEM1      0x00020000  // Status of sem 1
-#define ARM_SD_SEM2      0x00040000  // Status of sem 2
-#define ARM_SD_SEM3      0x00080000  // Status of sem 3
-#define ARM_SD_SEM4      0x00100000  // Status of sem 4
-#define ARM_SD_SEM5      0x00200000  // Status of sem 5
-#define ARM_SD_SEM6      0x00400000  // Status of sem 6
-#define ARM_SD_SEM7      0x00800000  // Status of sem 7
-
-// Doorbell status registers (...0x40-4C)
-#define ARM_DS_ACTIVE    0x00000004  // Doorbell rung since last read?
-#define ARM_DS_OWNER     0x00000003  // Owner
-
-// Doorbells clear/debug register (...0xE4)
-#define ARM_BD_OWN0      0x00000003  // Owner of doorbell 0
-#define ARM_BD_OWN1      0x0000000C  // Owner of doorbell 1
-#define ARM_BD_OWN2      0x00000030  // Owner of doorbell 2
-#define ARM_BD_OWN3      0x000000C0  // Owner of doorbell 3
-#define ARM_BD_BELL0     0x00000100  // Status of doorbell 0
-#define ARM_BD_BELL1     0x00000200  // Status of doorbell 1
-#define ARM_BD_BELL2     0x00000400  // Status of doorbell 2
-#define ARM_BD_BELL3     0x00000800  // Status of doorbell 3
-
-// MY IRQS register (...0xF8)
-#define ARM_MYIRQ_BELL   0x00000001  // This owner has a doorbell IRQ
-#define ARM_MYIRQ_MAIL   0x00000002  // This owner has a mailbox  IRQ
-
-// ALL IRQS register (...0xF8)
-#define ARM_AIS_BELL0 0x00000001  // Doorbell 0 IRQ pending
-#define ARM_AIS_BELL1 0x00000002  // Doorbell 1 IRQ pending
-#define ARM_AIS_BELL2 0x00000004  // Doorbell 2 IRQ pending
-#define ARM_AIS_BELL3 0x00000008  // Doorbell 3 IRQ pending
-#define ARM_AIS0_HAVEDATA 0x00000010  // MAIL 0 has data IRQ pending
-#define ARM_AIS0_HAVESPAC 0x00000020  // MAIL 0 has space IRQ pending
-#define ARM_AIS0_OPPEMPTY 0x00000040  // MAIL 0 opposite is empty IRQ
-#define ARM_AIS1_HAVEDATA 0x00000080  // MAIL 1 has data IRQ pending
-#define ARM_AIS1_HAVESPAC 0x00000100  // MAIL 1 has space IRQ pending
-#define ARM_AIS1_OPPEMPTY 0x00000200  // MAIL 1 opposite is empty IRQ
-// Note   that bell-0, bell-1 and MAIL0 IRQ go only to the ARM
-// Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC
-//
-// ARM JTAG BASH
-//
-#define AJB_BASE 0x7e2000c0
-
-#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
-#define   AJB_BITS0    0x000000
-#define   AJB_BITS4    0x000004
-#define   AJB_BITS8    0x000008
-#define   AJB_BITS12   0x00000C
-#define   AJB_BITS16   0x000010
-#define   AJB_BITS20   0x000014
-#define   AJB_BITS24   0x000018
-#define   AJB_BITS28   0x00001C
-#define   AJB_BITS32   0x000020
-#define   AJB_BITS34   0x000022
-#define   AJB_OUT_MS   0x000040
-#define   AJB_OUT_LS   0x000000
-#define   AJB_INV_CLK  0x000080
-#define   AJB_D0_RISE  0x000100
-#define   AJB_D0_FALL  0x000000
-#define   AJB_D1_RISE  0x000200
-#define   AJB_D1_FALL  0x000000
-#define   AJB_IN_RISE  0x000400
-#define   AJB_IN_FALL  0x000000
-#define   AJB_ENABLE   0x000800
-#define   AJB_HOLD0    0x000000
-#define   AJB_HOLD1    0x001000
-#define   AJB_HOLD2    0x002000
-#define   AJB_HOLD3    0x003000
-#define   AJB_RESETN   0x004000
-#define   AJB_CLKSHFT  16
-#define   AJB_BUSY     0x80000000
-#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
-#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
-#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
diff --git a/bcm2708_chip/aux_io.h b/bcm2708_chip/aux_io.h
deleted file mode 100644 (file)
index ff4fe9a..0000000
+++ /dev/null
@@ -1,170 +0,0 @@
-//
-// Auxiliary I/O header file
-//
-
-#define AUX_IO_BASE               0x7E215000
-#define AUX_IRQ                   (AUX_IO_BASE+0x000)
-#define AUX_ENABLES               (AUX_IO_BASE+0x004)
-#define    AUX_ENABLE_MINIUART    0x01
-#define    AUX_ENABLE_SPI0        0x02
-#define    AUX_ENABLE_SPI1        0x04
-
-
-//
-// Micro UART
-//
-// Baud rate = sysclk/(8*(BAUD_REG+1))
-
-#define AUX_MU_IO_REG             (AUX_IO_BASE+0x040) // Write=TX read=RX
-#define AUX_MU_BDLS_REG           (AUX_IO_BASE+0x040) // Baudrate LS
-#define AUX_MU_BDMS_REG           (AUX_IO_BASE+0x044) // Baudrate MS.
-
-#define AUX_MU_IER_REG            (AUX_IO_BASE+0x044) // IRQ enbl. reg.
-#define    AUX_MU_IER_RXIRQEN     0x01  //
-#define    AUX_MU_IER_TXIRQEN     0x02  //
-// Line interrupts are not supported
-
-#define AUX_MU_IIR_REG            (AUX_IO_BASE+0x048) // IRQ status reg
-#define    AUX_MU_IIR_NOIRQS      0x01  // No irq pending
-#define    AUX_MU_IIR_IRQ         0x06  // 10 = rec irq, 01 = tx irq
-// Timeout is not supported
-
-#define AUX_MU_FCR_REG            (AUX_IO_BASE+0x048) // FIFO control reg
-#define    AUX_MU_FCR_RXCLR       0x02  // Flush receive FF
-#define    AUX_MU_FCR_TXCLR       0x04  // Flush transmit fifo
-
-
-#define AUX_MU_LCR_REG            (AUX_IO_BASE+0x04C) // Line control reg.
-#define    AUX_MU_LCR_7BITS       0x02 // 7 bits mode
-#define    AUX_MU_LCR_8BITS       0x03 // 8 bits mode
-#define    AUX_MU_LCR_BREAK       0x40 // send break
-#define    AUX_MU_LCR_DLAB        0x80 // DLAB access
-// 5 & 6 bits are not supported
-// 2 stop bits are not supported
-// Parity bits are not supported
-
-#define AUX_MU_MCR_REG            (AUX_IO_BASE+0x050) // Modem control reg.
-#define    AUX_MU_MCR_RTS         0x02 // Set RTS high
-// DTR is not supported
-// Out1/2 are not supported
-// Loopback is not supported
-
-#define AUX_MU_LSR_REG            (AUX_IO_BASE+0x054) // Line status reg.
-#define    AUX_MU_LSR_DR          0x01 // Receive Data ready
-#define    AUX_MU_LSR_OE          0x02 // Receiver overrun error
-#define    AUX_MU_LSR_THRE        0x20 // Transmitter holding register
-#define    AUX_MU_LSR_TEMT        0x40 // Transmitter empty
-// Parity bits (and thus errors) are not supported
-// Framing errors are not detected
-// Break detect is not (yet) supported
-
-#define AUX_MU_MSR_REG            (AUX_IO_BASE+0x058) // Modem status reg.
-#define    AUX_MU_MSR_CTS         0x10
-// Delta CTS not supported
-// DCE,DCD not supportred
-
-#define AUX_MU_SCRATCH            (AUX_IO_BASE+0x05C) // Scratch reg.
-
-// None 16550 features
-#define AUX_MU_CNTL_REG           (AUX_IO_BASE+0x060) // AUX control reg.
-#define    AUX_MU_CNTL_REC_ENBL   0x01 // receiver enable
-#define    AUX_MU_CNTL_TRN_ENBL   0x02 // transmitter enable
-#define    AUX_MU_CNTL_AUTO_RTR   0x04 // RTR set by RX FF level
-#define    AUX_MU_CNTL_AUTO_CTS   0x08 // CTS auto stops transmitter
-#define    AUX_MU_CNTL_FLOW3      0x00 // Stop on RX FF 3 entries left
-#define    AUX_MU_CNTL_FLOW2      0x10 // Stop on RX FF 2 entries left
-#define    AUX_MU_CNTL_FLOW1      0x20 // Stop on RX FF 1 entries left
-#define    AUX_MU_CNTL_FLOW4      0x30 // Stop on RX FF 4 entries left
-#define    AUX_MU_CNTL_AURTRINV   0x40 // Invert AUTO RTR polarity
-#define    AUX_MU_CNTL_AUCTSINV   0x80 // Invert AUTO CTS polarity
-
-
-#define AUX_MU_STAT_REG           (AUX_IO_BASE+0x064) // AUX status reg.
-#define    AUX_MU_STAT_RX_DATA    0x00000001 // RX FF has value
-#define    AUX_MU_STAT_TX_SPACE   0x00000002 // TX FF has space (not full)
-#define    AUX_MU_STAT_RX_IDLE    0x00000004 // Receiver is idle
-#define    AUX_MU_STAT_TX_IDLE    0x00000008 // Transmitter is idle
-#define    AUX_MU_STAT_RX_OFLW    0x00000010 // Receiver FF overflow error
-#define    AUX_MU_STAT_TX_FULL    0x00000020 // Transmit FF full
-#define    AUX_MU_STAT_RTR        0x00000040 // Status of the RTR line
-#define    AUX_MU_STAT_CTS        0x00000080 // Status of the CTS line (fully synced)
-#define    AUX_MU_STAT_TXEMPTY    0x00000100 // TX FF is empty
-#define    AUX_MU_STAT_TXDONE     0x00000200  // TX FF is empty and TX is idle
-#define    AUX_MU_STAT_RXFILL     0x00FF0000 // RX FF fill level
-#define    AUX_MU_STAT_TXFILL     0xFF000000 // TX FF fill level
-
-#define AUX_MU_BAUD_REG           (AUX_IO_BASE+0x068) // Baudrate reg (16 bits)
-                                             // Baud rate = sysclk/(8*(BAUD_REG+1))
-
-//
-// SPI 0 (SPI1 in the device!)
-//
-#define AUX_SPI0_CNTL0_REG        (AUX_IO_BASE+0x080) // control reg 0
-#define   AUX_SPI_CNTL0_BITS      0x0000003F // Number of bits to send/receive
-#define   AUX_SPI_CNTL0_OUTMS     0x00000040 // Shift MS bit out first)
-#define   AUX_SPI_CNTL0_INVCLK    0x00000080 // Invert SPI_CLK
-#define   AUX_SPI_CNTL0_OUTRISE   0x00000100 // data out leaves on rising clock edge
-#define   AUX_SPI_CNTL0_OUTFALL   0x00000000 // data out leaves on falling clock edge
-#define   AUX_SPI_CNTL0_FFCLR     0x00000200 // Reset fifos (Set and clear bit)
-#define   AUX_SPI_CNTL0_INRISE    0x00000400 // data in on rising clock edge
-#define   AUX_SPI_CNTL0_INFALL    0x00000000 // data in on falling clock edge
-#define   AUX_SPI_CNTL0_SERENBL   0x00000800 // Serial enable (does not disable FFs)
-#define   AUX_SPI_CNTL0_HOLD0     0x00000000 // Dout hold 0 sys clock cycles
-#define   AUX_SPI_CNTL0_HOLD4     0x00001000 // Dout hold 4 sys clock cycle
-#define   AUX_SPI_CNTL0_HOLD7     0x00002000 // Dout hold 7 sys clock cycles
-#define   AUX_SPI_CNTL0_HOLD10    0x00003000 // Dout hold 10 sys clock cycles
-#define   AUX_SPI_CNTL0_VARWID    0x00004000 // Variable width mode (din[15-12]=bits)
-#define   AUX_SPI_CNTL0_CSFROMFF  0x00008000 // CS pattern comesfrom MS 3 TX FIFO bits
-#define   AUX_SPI_CNTL0_POSTIN    0x00010000 // Load last bit after cycles finished
-#define   AUX_SPI_CNTL0_CS_HIGH   0x000E0000 // All CS are high
-#define   AUX_SPI_CNTL0_CS0_N     0x000C0000 // CS 0 low
-#define   AUX_SPI_CNTL0_CS1_N     0x000A0000 // CS 1 low
-#define   AUX_SPI_CNTL0_CS2_N     0x00060000 // CS 2 low
-#define   AUX_SPI_CNTL0_CSA_N     0x00000000 // ALL CS low (test only)
-#define   AUX_SPI_CNTL0_SPEED     0xFFF00000 // SPI clock = sysclock/(2xspeed)
-#define   AUX_SPI_CNTL0_SPEEDSHFT 20         // Speed shift left value
-
-#define AUX_SPI0_CNTL1_REG        (AUX_IO_BASE+0x084) // control reg 1
-#define   AUX_SPI_CNTL1_HOLDIN    0x00000001 // Do not clear DIN register at start
-#define   AUX_SPI_CNTL1_INMS      0x00000002 // Shift data in MS first MS--->LS
-//#define   AUX_SPI_CNTL1_CS_NOW    0x00000004 // Assert CS pattern now
-#define   AUX_SPI_CNTL1_EMPTYIRQ  0x00000040 // IRQ on TX Fifo empty
-#define   AUX_SPI_CNTL1_DONEIRQ   0x00000080 // IRQ on IDLE AND TxFifo empty
-#define   AUX_SPI_CNTL1_CSPLUS1   0x00000100 // CS HI plus 1 bit
-#define   AUX_SPI_CNTL1_CSPLUS2   0x00000200 // CS HI plus 2 bit
-#define   AUX_SPI_CNTL1_CSPLUS3   0x00000300 // CS HI plus 3 bit
-#define   AUX_SPI_CNTL1_CSPLUS4   0x00000400 // CS HI plus 4 bit
-#define   AUX_SPI_CNTL1_CSPLUS5   0x00000500 // CS HI plus 5 bit
-#define   AUX_SPI_CNTL1_CSPLUS6   0x00000600 // CS HI plus 6 bit
-#define   AUX_SPI_CNTL1_CSPLUS7   0x00000700 // CS HI plus 7 bit
-
-#define AUX_SPI0_STAT_REG         (AUX_IO_BASE+0x088) // Status reg.
-#define    AUX_SPI_STAT_BITCNT    0x0000003F // Bits remaining to be shifted out
-#define    AUX_SPI_STAT_BUSY      0x00000040 // FSM is busy
-#define    AUX_SPI_STAT_RXEMPTY   0x00000080 // RX FF is empty
-#define    AUX_SPI_STAT_RXFULL    0x00000100 // RX FF is full
-#define    AUX_SPI_STAT_TXEMPTY   0x00000200 // TX FF is empyt
-#define    AUX_SPI_STAT_TXFULL    0x00000400 // TX FF is full
-#define    AUX_SPI_STAT_RXFILL    0x000F0000 // RX FF fill level
-#define    AUX_SPI_STAT_TXFILL    0x0F000000 // TX FF fill level
-#define AUX_SPI0_PEEK_REG         (AUX_IO_BASE+0x08C) // Read but do not take from FF
-#define AUX_SPI0_IO_REG           (AUX_IO_BASE+0x0A0) // Write = TX, read=RX
-#define AUX_SPI0_TXHOLD_REG       (AUX_IO_BASE+0x0B0) // Write = TX keep cs, read=RX
-
-
-
-//
-// SPI 1 (SPI2 in the device!)
-//
-#define AUX_SPI1_CNTL0_REG        (AUX_IO_BASE+0x0C0)
-#define AUX_SPI1_CNTL1_REG        (AUX_IO_BASE+0x0C4)
-#define AUX_SPI1_STAT_REG         (AUX_IO_BASE+0x0C8)
-#define AUX_SPI1_PEEK_REG         (AUX_IO_BASE+0x0CC)
-#define AUX_SPI1_IO_REG           (AUX_IO_BASE+0x0E0)
-#define AUX_SPI1_TXHOLD_REG       (AUX_IO_BASE+0x0F0) // Write = TX keep cs, read=RX
-
-//
-//  Some usefull GPIO macros
-//
-#define CLR_GPIO(g) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))&= ~(7<<(((g)%10)*3))
-#define SET_GPIO_ALT(g,a) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))|= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
diff --git a/bcm2708_chip/ave_in.h b/bcm2708_chip/ave_in.h
deleted file mode 100644 (file)
index d35fccf..0000000
+++ /dev/null
@@ -1,334 +0,0 @@
-// This file was generated by the create_regs script
-#define AVE_IN_BASE                                              0x7e910000
-#define AVE_IN_APB_ID                                            0x61766530
-#define AVE_IN_CTRL                                              HW_REGISTER_RW( 0x7e910000 ) 
-   #define AVE_IN_CTRL_MASK                                      0x87ffffff
-   #define AVE_IN_CTRL_WIDTH                                     32
-   #define AVE_IN_CTRL_RESET                                     0x08000080
-      #define AVE_IN_CTRL_ENABLE_BITS                            31:31
-      #define AVE_IN_CTRL_ENABLE_SET                             0x80000000
-      #define AVE_IN_CTRL_ENABLE_CLR                             0x7fffffff
-      #define AVE_IN_CTRL_ENABLE_MSB                             31
-      #define AVE_IN_CTRL_ENABLE_LSB                             31
-      #define AVE_IN_CTRL_PRIORITY_LIMIT_BITS                    26:24
-      #define AVE_IN_CTRL_PRIORITY_LIMIT_SET                     0x07000000
-      #define AVE_IN_CTRL_PRIORITY_LIMIT_CLR                     0xf8ffffff
-      #define AVE_IN_CTRL_PRIORITY_LIMIT_MSB                     26
-      #define AVE_IN_CTRL_PRIORITY_LIMIT_LSB                     24
-      #define AVE_IN_CTRL_HIGH_PRIORITY_BITS                     23:20
-      #define AVE_IN_CTRL_HIGH_PRIORITY_SET                      0x00f00000
-      #define AVE_IN_CTRL_HIGH_PRIORITY_CLR                      0xff0fffff
-      #define AVE_IN_CTRL_HIGH_PRIORITY_MSB                      23
-      #define AVE_IN_CTRL_HIGH_PRIORITY_LSB                      20
-      #define AVE_IN_CTRL_LOW_PRIORITY_BITS                      19:16
-      #define AVE_IN_CTRL_LOW_PRIORITY_SET                       0x000f0000
-      #define AVE_IN_CTRL_LOW_PRIORITY_CLR                       0xfff0ffff
-      #define AVE_IN_CTRL_LOW_PRIORITY_MSB                       19
-      #define AVE_IN_CTRL_LOW_PRIORITY_LSB                       16
-      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_BITS                  15:15
-      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_SET                   0x00008000
-      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_CLR                   0xffff7fff
-      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_MSB                   15
-      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_LSB                   15
-      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_BITS             14:14
-      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_SET              0x00004000
-      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_CLR              0xffffbfff
-      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_MSB              14
-      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_LSB              14
-      #define AVE_IN_CTRL_BYTE_ORDER_BITS                        13:11
-      #define AVE_IN_CTRL_BYTE_ORDER_SET                         0x00003800
-      #define AVE_IN_CTRL_BYTE_ORDER_CLR                         0xffffc7ff
-      #define AVE_IN_CTRL_BYTE_ORDER_MSB                         13
-      #define AVE_IN_CTRL_BYTE_ORDER_LSB                         11
-      #define AVE_IN_CTRL_FRAME_MODE_BITS                        10:9
-      #define AVE_IN_CTRL_FRAME_MODE_SET                         0x00000600
-      #define AVE_IN_CTRL_FRAME_MODE_CLR                         0xfffff9ff
-      #define AVE_IN_CTRL_FRAME_MODE_MSB                         10
-      #define AVE_IN_CTRL_FRAME_MODE_LSB                         9
-      #define AVE_IN_CTRL_LENGTH_IN_PXLS_BITS                    8:8
-      #define AVE_IN_CTRL_LENGTH_IN_PXLS_SET                     0x00000100
-      #define AVE_IN_CTRL_LENGTH_IN_PXLS_CLR                     0xfffffeff
-      #define AVE_IN_CTRL_LENGTH_IN_PXLS_MSB                     8
-      #define AVE_IN_CTRL_LENGTH_IN_PXLS_LSB                     8
-      #define AVE_IN_CTRL_PRIV_MODE_BITS                         7:7
-      #define AVE_IN_CTRL_PRIV_MODE_SET                          0x00000080
-      #define AVE_IN_CTRL_PRIV_MODE_CLR                          0xffffff7f
-      #define AVE_IN_CTRL_PRIV_MODE_MSB                          7
-      #define AVE_IN_CTRL_PRIV_MODE_LSB                          7
-      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_BITS                 6:6
-      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_SET                  0x00000040
-      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_CLR                  0xffffffbf
-      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_MSB                  6
-      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_LSB                  6
-      #define AVE_IN_CTRL_HSYNC_IRQ_EN_BITS                      5:5
-      #define AVE_IN_CTRL_HSYNC_IRQ_EN_SET                       0x00000020
-      #define AVE_IN_CTRL_HSYNC_IRQ_EN_CLR                       0xffffffdf
-      #define AVE_IN_CTRL_HSYNC_IRQ_EN_MSB                       5
-      #define AVE_IN_CTRL_HSYNC_IRQ_EN_LSB                       5
-      #define AVE_IN_CTRL_LINE_IRQ_EN_BITS                       4:4
-      #define AVE_IN_CTRL_LINE_IRQ_EN_SET                        0x00000010
-      #define AVE_IN_CTRL_LINE_IRQ_EN_CLR                        0xffffffef
-      #define AVE_IN_CTRL_LINE_IRQ_EN_MSB                        4
-      #define AVE_IN_CTRL_LINE_IRQ_EN_LSB                        4
-      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_BITS                    3:3
-      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_SET                     0x00000008
-      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_CLR                     0xfffffff7
-      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_MSB                     3
-      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_LSB                     3
-      #define AVE_IN_CTRL_BUF1_IRQ_EN_BITS                       2:2
-      #define AVE_IN_CTRL_BUF1_IRQ_EN_SET                        0x00000004
-      #define AVE_IN_CTRL_BUF1_IRQ_EN_CLR                        0xfffffffb
-      #define AVE_IN_CTRL_BUF1_IRQ_EN_MSB                        2
-      #define AVE_IN_CTRL_BUF1_IRQ_EN_LSB                        2
-      #define AVE_IN_CTRL_BUF0_IRQ_EN_BITS                       1:1
-      #define AVE_IN_CTRL_BUF0_IRQ_EN_SET                        0x00000002
-      #define AVE_IN_CTRL_BUF0_IRQ_EN_CLR                        0xfffffffd
-      #define AVE_IN_CTRL_BUF0_IRQ_EN_MSB                        1
-      #define AVE_IN_CTRL_BUF0_IRQ_EN_LSB                        1
-      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_BITS                    0:0
-      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_SET                     0x00000001
-      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_CLR                     0xfffffffe
-      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_MSB                     0
-      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_LSB                     0
-#define AVE_IN_STATUS                                            HW_REGISTER_RW( 0x7e910004 ) 
-   #define AVE_IN_STATUS_MASK                                    0x9f733f7f
-   #define AVE_IN_STATUS_WIDTH                                   32
-   #define AVE_IN_STATUS_RESET                                   0000000000
-      #define AVE_IN_STATUS_CAPTURING_BITS                       31:31
-      #define AVE_IN_STATUS_CAPTURING_SET                        0x80000000
-      #define AVE_IN_STATUS_CAPTURING_CLR                        0x7fffffff
-      #define AVE_IN_STATUS_CAPTURING_MSB                        31
-      #define AVE_IN_STATUS_CAPTURING_LSB                        31
-      #define AVE_IN_STATUS_OVERRUN_CNT_BITS                     28:24
-      #define AVE_IN_STATUS_OVERRUN_CNT_SET                      0x1f000000
-      #define AVE_IN_STATUS_OVERRUN_CNT_CLR                      0xe0ffffff
-      #define AVE_IN_STATUS_OVERRUN_CNT_MSB                      28
-      #define AVE_IN_STATUS_OVERRUN_CNT_LSB                      24
-      #define AVE_IN_STATUS_AXI_STATE_BITS                       22:20
-      #define AVE_IN_STATUS_AXI_STATE_SET                        0x00700000
-      #define AVE_IN_STATUS_AXI_STATE_CLR                        0xff8fffff
-      #define AVE_IN_STATUS_AXI_STATE_MSB                        22
-      #define AVE_IN_STATUS_AXI_STATE_LSB                        20
-      #define AVE_IN_STATUS_CURRENT_BUF_BITS                     17:17
-      #define AVE_IN_STATUS_CURRENT_BUF_SET                      0x00020000
-      #define AVE_IN_STATUS_CURRENT_BUF_CLR                      0xfffdffff
-      #define AVE_IN_STATUS_CURRENT_BUF_MSB                      17
-      #define AVE_IN_STATUS_CURRENT_BUF_LSB                      17
-      #define AVE_IN_STATUS_MAX_HIT_BITS                         16:16
-      #define AVE_IN_STATUS_MAX_HIT_SET                          0x00010000
-      #define AVE_IN_STATUS_MAX_HIT_CLR                          0xfffeffff
-      #define AVE_IN_STATUS_MAX_HIT_MSB                          16
-      #define AVE_IN_STATUS_MAX_HIT_LSB                          16
-      #define AVE_IN_STATUS_CSYNC_FIELD_BITS                     13:13
-      #define AVE_IN_STATUS_CSYNC_FIELD_SET                      0x00002000
-      #define AVE_IN_STATUS_CSYNC_FIELD_CLR                      0xffffdfff
-      #define AVE_IN_STATUS_CSYNC_FIELD_MSB                      13
-      #define AVE_IN_STATUS_CSYNC_FIELD_LSB                      13
-      #define AVE_IN_STATUS_VFORM_FIELD_BITS                     12:12
-      #define AVE_IN_STATUS_VFORM_FIELD_SET                      0x00001000
-      #define AVE_IN_STATUS_VFORM_FIELD_CLR                      0xffffefff
-      #define AVE_IN_STATUS_VFORM_FIELD_MSB                      12
-      #define AVE_IN_STATUS_VFORM_FIELD_LSB                      12
-      #define AVE_IN_STATUS_EVEN_FIELD_BITS                      11:11
-      #define AVE_IN_STATUS_EVEN_FIELD_SET                       0x00000800
-      #define AVE_IN_STATUS_EVEN_FIELD_CLR                       0xfffff7ff
-      #define AVE_IN_STATUS_EVEN_FIELD_MSB                       11
-      #define AVE_IN_STATUS_EVEN_FIELD_LSB                       11
-      #define AVE_IN_STATUS_INTERLACED_BITS                      10:10
-      #define AVE_IN_STATUS_INTERLACED_SET                       0x00000400
-      #define AVE_IN_STATUS_INTERLACED_CLR                       0xfffffbff
-      #define AVE_IN_STATUS_INTERLACED_MSB                       10
-      #define AVE_IN_STATUS_INTERLACED_LSB                       10
-      #define AVE_IN_STATUS_FRAME_RATE_BITS                      9:8
-      #define AVE_IN_STATUS_FRAME_RATE_SET                       0x00000300
-      #define AVE_IN_STATUS_FRAME_RATE_CLR                       0xfffffcff
-      #define AVE_IN_STATUS_FRAME_RATE_MSB                       9
-      #define AVE_IN_STATUS_FRAME_RATE_LSB                       8
-      #define AVE_IN_STATUS_FRAME_RATE_DET_BITS                  6:6
-      #define AVE_IN_STATUS_FRAME_RATE_DET_SET                   0x00000040
-      #define AVE_IN_STATUS_FRAME_RATE_DET_CLR                   0xffffffbf
-      #define AVE_IN_STATUS_FRAME_RATE_DET_MSB                   6
-      #define AVE_IN_STATUS_FRAME_RATE_DET_LSB                   6
-      #define AVE_IN_STATUS_HSYNC_DET_BITS                       5:5
-      #define AVE_IN_STATUS_HSYNC_DET_SET                        0x00000020
-      #define AVE_IN_STATUS_HSYNC_DET_CLR                        0xffffffdf
-      #define AVE_IN_STATUS_HSYNC_DET_MSB                        5
-      #define AVE_IN_STATUS_HSYNC_DET_LSB                        5
-      #define AVE_IN_STATUS_LINE_NUM_HIT_BITS                    4:4
-      #define AVE_IN_STATUS_LINE_NUM_HIT_SET                     0x00000010
-      #define AVE_IN_STATUS_LINE_NUM_HIT_CLR                     0xffffffef
-      #define AVE_IN_STATUS_LINE_NUM_HIT_MSB                     4
-      #define AVE_IN_STATUS_LINE_NUM_HIT_LSB                     4
-      #define AVE_IN_STATUS_BUF_NOT_SERV_BITS                    3:3
-      #define AVE_IN_STATUS_BUF_NOT_SERV_SET                     0x00000008
-      #define AVE_IN_STATUS_BUF_NOT_SERV_CLR                     0xfffffff7
-      #define AVE_IN_STATUS_BUF_NOT_SERV_MSB                     3
-      #define AVE_IN_STATUS_BUF_NOT_SERV_LSB                     3
-      #define AVE_IN_STATUS_BUF1_COMPL_BITS                      2:2
-      #define AVE_IN_STATUS_BUF1_COMPL_SET                       0x00000004
-      #define AVE_IN_STATUS_BUF1_COMPL_CLR                       0xfffffffb
-      #define AVE_IN_STATUS_BUF1_COMPL_MSB                       2
-      #define AVE_IN_STATUS_BUF1_COMPL_LSB                       2
-      #define AVE_IN_STATUS_BUF0_COMPL_BITS                      1:1
-      #define AVE_IN_STATUS_BUF0_COMPL_SET                       0x00000002
-      #define AVE_IN_STATUS_BUF0_COMPL_CLR                       0xfffffffd
-      #define AVE_IN_STATUS_BUF0_COMPL_MSB                       1
-      #define AVE_IN_STATUS_BUF0_COMPL_LSB                       1
-      #define AVE_IN_STATUS_OVERRUN_DET_BITS                     0:0
-      #define AVE_IN_STATUS_OVERRUN_DET_SET                      0x00000001
-      #define AVE_IN_STATUS_OVERRUN_DET_CLR                      0xfffffffe
-      #define AVE_IN_STATUS_OVERRUN_DET_MSB                      0
-      #define AVE_IN_STATUS_OVERRUN_DET_LSB                      0
-#define AVE_IN_BUF0_ADDRESS                                      HW_REGISTER_RW( 0x7e910008 ) 
-   #define AVE_IN_BUF0_ADDRESS_MASK                              0xffffffff
-   #define AVE_IN_BUF0_ADDRESS_WIDTH                             32
-   #define AVE_IN_BUF0_ADDRESS_RESET                             0000000000
-      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_BITS                 31:0
-      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_SET                  0xffffffff
-      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_CLR                  0x00000000
-      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_MSB                  31
-      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_LSB                  0
-#define AVE_IN_BUF1_ADDRESS                                      HW_REGISTER_RW( 0x7e91000c ) 
-   #define AVE_IN_BUF1_ADDRESS_MASK                              0xffffffff
-   #define AVE_IN_BUF1_ADDRESS_WIDTH                             32
-   #define AVE_IN_BUF1_ADDRESS_RESET                             0000000000
-      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_BITS                 31:0
-      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_SET                  0xffffffff
-      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_CLR                  0x00000000
-      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_MSB                  31
-      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_LSB                  0
-#define AVE_IN_MAX_TRANSFER                                      HW_REGISTER_RW( 0x7e910010 ) 
-   #define AVE_IN_MAX_TRANSFER_MASK                              0xffffffff
-   #define AVE_IN_MAX_TRANSFER_WIDTH                             32
-   #define AVE_IN_MAX_TRANSFER_RESET                             0000000000
-      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_BITS              31:0
-      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_SET               0xffffffff
-      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_CLR               0x00000000
-      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_MSB               31
-      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_LSB               0
-#define AVE_IN_LINE_LENGTH                                       HW_REGISTER_RW( 0x7e910014 ) 
-   #define AVE_IN_LINE_LENGTH_MASK                               0x00000fff
-   #define AVE_IN_LINE_LENGTH_WIDTH                              12
-   #define AVE_IN_LINE_LENGTH_RESET                              0000000000
-      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_BITS                11:0
-      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_SET                 0x00000fff
-      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_CLR                 0xfffff000
-      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_MSB                 11
-      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_LSB                 0
-#define AVE_IN_CURRENT_ADDRESS                                   HW_REGISTER_RW( 0x7e910018 ) 
-   #define AVE_IN_CURRENT_ADDRESS_MASK                           0xffffffff
-   #define AVE_IN_CURRENT_ADDRESS_WIDTH                          32
-   #define AVE_IN_CURRENT_ADDRESS_RESET                          0000000000
-      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_BITS               31:0
-      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_SET                0xffffffff
-      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_CLR                0x00000000
-      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_MSB                31
-      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_LSB                0
-#define AVE_IN_CURRENT_LINE_BUF0                                 HW_REGISTER_RW( 0x7e91001c ) 
-   #define AVE_IN_CURRENT_LINE_BUF0_MASK                         0x80000fff
-   #define AVE_IN_CURRENT_LINE_BUF0_WIDTH                        32
-   #define AVE_IN_CURRENT_LINE_BUF0_RESET                        0000000000
-      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_BITS         11:0
-      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_SET          0x00000fff
-      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_CLR          0xfffff000
-      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_MSB          11
-      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_LSB          0
-      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_BITS           31:31
-      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_SET            0x80000000
-      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_CLR            0x7fffffff
-      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_MSB            31
-      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_LSB            31
-#define AVE_IN_CURRENT_LINE_BUF1                                 HW_REGISTER_RW( 0x7e910020 ) 
-   #define AVE_IN_CURRENT_LINE_BUF1_MASK                         0x80000fff
-   #define AVE_IN_CURRENT_LINE_BUF1_WIDTH                        32
-   #define AVE_IN_CURRENT_LINE_BUF1_RESET                        0000000000
-      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_BITS         11:0
-      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_SET          0x00000fff
-      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_CLR          0xfffff000
-      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_MSB          11
-      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_LSB          0
-      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_BITS           31:31
-      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_SET            0x80000000
-      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_CLR            0x7fffffff
-      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_MSB            31
-      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_LSB            31
-#define AVE_IN_CURRENT_LINE_NUM                                  HW_REGISTER_RW( 0x7e910024 ) 
-   #define AVE_IN_CURRENT_LINE_NUM_MASK                          0xe0000fff
-   #define AVE_IN_CURRENT_LINE_NUM_WIDTH                         32
-   #define AVE_IN_CURRENT_LINE_NUM_RESET                         0000000000
-      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_BITS          11:0
-      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_SET           0x00000fff
-      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_CLR           0xfffff000
-      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_MSB           11
-      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_LSB           0
-      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_BITS        29:29
-      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_SET         0x20000000
-      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_CLR         0xdfffffff
-      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_MSB         29
-      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_LSB         29
-      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_BITS            30:30
-      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_SET             0x40000000
-      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_CLR             0xbfffffff
-      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_MSB             30
-      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_LSB             30
-      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_BITS            31:31
-      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_SET             0x80000000
-      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_CLR             0x7fffffff
-      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_MSB             31
-      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_LSB             31
-#define AVE_IN_OVERRUN_ADDRESS                                   HW_REGISTER_RW( 0x7e910028 ) 
-   #define AVE_IN_OVERRUN_ADDRESS_MASK                           0xffffffff
-   #define AVE_IN_OVERRUN_ADDRESS_WIDTH                          32
-   #define AVE_IN_OVERRUN_ADDRESS_RESET                          0000000000
-      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_BITS           31:0
-      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_SET            0xffffffff
-      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_CLR            0x00000000
-      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_MSB            31
-      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_LSB            0
-#define AVE_IN_LINE_NUM_INT                                      HW_REGISTER_RW( 0x7e91002c ) 
-   #define AVE_IN_LINE_NUM_INT_MASK                              0x00000fff
-   #define AVE_IN_LINE_NUM_INT_WIDTH                             12
-   #define AVE_IN_LINE_NUM_INT_RESET                             0000000000
-      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_BITS              11:0
-      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_SET               0x00000fff
-      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_CLR               0xfffff000
-      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_MSB               11
-      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_LSB               0
-#define AVE_IN_CALC_LINE_STEP                                    HW_REGISTER_RW( 0x7e910030 ) 
-   #define AVE_IN_CALC_LINE_STEP_MASK                            0x00000fff
-   #define AVE_IN_CALC_LINE_STEP_WIDTH                           12
-   #define AVE_IN_CALC_LINE_STEP_RESET                           0000000000
-      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_BITS          11:0
-      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_SET           0x00000fff
-      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_CLR           0xfffff000
-      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_MSB           11
-      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_LSB           0
-#define AVE_IN_OUTSTANDING_BUFF0                                 HW_REGISTER_RW( 0x7e910034 ) 
-   #define AVE_IN_OUTSTANDING_BUFF0_MASK                         0x000000ff
-   #define AVE_IN_OUTSTANDING_BUFF0_WIDTH                        8
-   #define AVE_IN_OUTSTANDING_BUFF0_RESET                        0000000000
-#define AVE_IN_OUTSTANDING_BUFF1                                 HW_REGISTER_RW( 0x7e910038 ) 
-   #define AVE_IN_OUTSTANDING_BUFF1_MASK                         0x000000ff
-   #define AVE_IN_OUTSTANDING_BUFF1_WIDTH                        8
-   #define AVE_IN_OUTSTANDING_BUFF1_RESET                        0000000000
-#define AVE_IN_CHAR_CTRL                                         HW_REGISTER_RW( 0x7e91003c ) 
-   #define AVE_IN_CHAR_CTRL_MASK                                 0x8000000f
-   #define AVE_IN_CHAR_CTRL_WIDTH                                32
-   #define AVE_IN_CHAR_CTRL_RESET                                0000000000
-#define AVE_IN_SYNC_CTRL                                         HW_REGISTER_RW( 0x7e910040 ) 
-   #define AVE_IN_SYNC_CTRL_MASK                                 0x0000008f
-   #define AVE_IN_SYNC_CTRL_WIDTH                                8
-   #define AVE_IN_SYNC_CTRL_RESET                                0000000000
-#define AVE_IN_FRAME_NUM                                         HW_REGISTER_RW( 0x7e910044 ) 
-   #define AVE_IN_FRAME_NUM_MASK                                 0x00000fff
-   #define AVE_IN_FRAME_NUM_WIDTH                                12
-   #define AVE_IN_FRAME_NUM_RESET                                0000000000
-      #define AVE_IN_FRAME_NUM_FRAME_NUM_BITS                    11:0
-      #define AVE_IN_FRAME_NUM_FRAME_NUM_SET                     0x00000fff
-      #define AVE_IN_FRAME_NUM_FRAME_NUM_CLR                     0xfffff000
-      #define AVE_IN_FRAME_NUM_FRAME_NUM_MSB                     11
-      #define AVE_IN_FRAME_NUM_FRAME_NUM_LSB                     0
-#define AVE_IN_BLOCK_ID                                          HW_REGISTER_RW( 0x7e910060 ) 
-   #define AVE_IN_BLOCK_ID_MASK                                  0xffffffff
-   #define AVE_IN_BLOCK_ID_WIDTH                                 32
-   #define AVE_IN_BLOCK_ID_RESET                                 0x61766530
diff --git a/bcm2708_chip/ave_out.h b/bcm2708_chip/ave_out.h
deleted file mode 100644 (file)
index ab7262e..0000000
+++ /dev/null
@@ -1,216 +0,0 @@
-// This file was generated by the create_regs script
-#define AVE_OUT_BASE                                             0x7e240000
-#define AVE_OUT_APB_ID                                           0x61766538
-#define AVE_OUT_CTRL                                             HW_REGISTER_RW( 0x7e240000 ) 
-   #define AVE_OUT_CTRL_MASK                                     0xc0fff13f
-   #define AVE_OUT_CTRL_WIDTH                                    32
-   #define AVE_OUT_CTRL_RESET                                    0x40000100
-      #define AVE_OUT_CTRL_ENABLE_BITS                           31:31
-      #define AVE_OUT_CTRL_ENABLE_SET                            0x80000000
-      #define AVE_OUT_CTRL_ENABLE_CLR                            0x7fffffff
-      #define AVE_OUT_CTRL_ENABLE_MSB                            31
-      #define AVE_OUT_CTRL_ENABLE_LSB                            31
-      #define AVE_OUT_CTRL_SOFT_RESET_BITS                       30:30
-      #define AVE_OUT_CTRL_SOFT_RESET_SET                        0x40000000
-      #define AVE_OUT_CTRL_SOFT_RESET_CLR                        0xbfffffff
-      #define AVE_OUT_CTRL_SOFT_RESET_MSB                        30
-      #define AVE_OUT_CTRL_SOFT_RESET_LSB                        30
-      #define AVE_OUT_CTRL_BYTE_SWAP_BITS                        23:19
-      #define AVE_OUT_CTRL_BYTE_SWAP_SET                         0x00f80000
-      #define AVE_OUT_CTRL_BYTE_SWAP_CLR                         0xff07ffff
-      #define AVE_OUT_CTRL_BYTE_SWAP_MSB                         23
-      #define AVE_OUT_CTRL_BYTE_SWAP_LSB                         19
-      #define AVE_OUT_CTRL_INVERT_DSYNC_BITS                     18:18
-      #define AVE_OUT_CTRL_INVERT_DSYNC_SET                      0x00040000
-      #define AVE_OUT_CTRL_INVERT_DSYNC_CLR                      0xfffbffff
-      #define AVE_OUT_CTRL_INVERT_DSYNC_MSB                      18
-      #define AVE_OUT_CTRL_INVERT_DSYNC_LSB                      18
-      #define AVE_OUT_CTRL_INVERT_CSYNC_BITS                     17:17
-      #define AVE_OUT_CTRL_INVERT_CSYNC_SET                      0x00020000
-      #define AVE_OUT_CTRL_INVERT_CSYNC_CLR                      0xfffdffff
-      #define AVE_OUT_CTRL_INVERT_CSYNC_MSB                      17
-      #define AVE_OUT_CTRL_INVERT_CSYNC_LSB                      17
-      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_BITS                16:16
-      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_SET                 0x00010000
-      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_CLR                 0xfffeffff
-      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_MSB                 16
-      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_LSB                 16
-      #define AVE_OUT_CTRL_INVERT_VSYNC_BITS                     15:15
-      #define AVE_OUT_CTRL_INVERT_VSYNC_SET                      0x00008000
-      #define AVE_OUT_CTRL_INVERT_VSYNC_CLR                      0xffff7fff
-      #define AVE_OUT_CTRL_INVERT_VSYNC_MSB                      15
-      #define AVE_OUT_CTRL_INVERT_VSYNC_LSB                      15
-      #define AVE_OUT_CTRL_INVERT_HSYNC_BITS                     14:14
-      #define AVE_OUT_CTRL_INVERT_HSYNC_SET                      0x00004000
-      #define AVE_OUT_CTRL_INVERT_HSYNC_CLR                      0xffffbfff
-      #define AVE_OUT_CTRL_INVERT_HSYNC_MSB                      14
-      #define AVE_OUT_CTRL_INVERT_HSYNC_LSB                      14
-      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_BITS                   13:13
-      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_SET                    0x00002000
-      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_CLR                    0xffffdfff
-      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_MSB                    13
-      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_LSB                    13
-      #define AVE_OUT_CTRL_INTERLEAVE_BITS                       12:12
-      #define AVE_OUT_CTRL_INTERLEAVE_SET                        0x00001000
-      #define AVE_OUT_CTRL_INTERLEAVE_CLR                        0xffffefff
-      #define AVE_OUT_CTRL_INTERLEAVE_MSB                        12
-      #define AVE_OUT_CTRL_INTERLEAVE_LSB                        12
-      #define AVE_OUT_CTRL_PRIV_ACCESS_BITS                      8:8
-      #define AVE_OUT_CTRL_PRIV_ACCESS_SET                       0x00000100
-      #define AVE_OUT_CTRL_PRIV_ACCESS_CLR                       0xfffffeff
-      #define AVE_OUT_CTRL_PRIV_ACCESS_MSB                       8
-      #define AVE_OUT_CTRL_PRIV_ACCESS_LSB                       8
-      #define AVE_OUT_CTRL_MODE_BITS                             5:4
-      #define AVE_OUT_CTRL_MODE_SET                              0x00000030
-      #define AVE_OUT_CTRL_MODE_CLR                              0xffffffcf
-      #define AVE_OUT_CTRL_MODE_MSB                              5
-      #define AVE_OUT_CTRL_MODE_LSB                              4
-      #define AVE_OUT_CTRL_REFRESH_RATE_BITS                     3:2
-      #define AVE_OUT_CTRL_REFRESH_RATE_SET                      0x0000000c
-      #define AVE_OUT_CTRL_REFRESH_RATE_CLR                      0xfffffff3
-      #define AVE_OUT_CTRL_REFRESH_RATE_MSB                      3
-      #define AVE_OUT_CTRL_REFRESH_RATE_LSB                      2
-      #define AVE_OUT_CTRL_COEFF_IRQ_EN_BITS                     1:1
-      #define AVE_OUT_CTRL_COEFF_IRQ_EN_SET                      0x00000002
-      #define AVE_OUT_CTRL_COEFF_IRQ_EN_CLR                      0xfffffffd
-      #define AVE_OUT_CTRL_COEFF_IRQ_EN_MSB                      1
-      #define AVE_OUT_CTRL_COEFF_IRQ_EN_LSB                      1
-      #define AVE_OUT_CTRL_ERROR_IRQ_EN_BITS                     0:0
-      #define AVE_OUT_CTRL_ERROR_IRQ_EN_SET                      0x00000001
-      #define AVE_OUT_CTRL_ERROR_IRQ_EN_CLR                      0xfffffffe
-      #define AVE_OUT_CTRL_ERROR_IRQ_EN_MSB                      0
-      #define AVE_OUT_CTRL_ERROR_IRQ_EN_LSB                      0
-#define AVE_OUT_STATUS                                           HW_REGISTER_RW( 0x7e240004 ) 
-   #define AVE_OUT_STATUS_MASK                                   0x000003f7
-   #define AVE_OUT_STATUS_WIDTH                                  10
-   #define AVE_OUT_STATUS_RESET                                  0000000000
-      #define AVE_OUT_STATUS_VSYNC_BITS                          9:9
-      #define AVE_OUT_STATUS_VSYNC_SET                           0x00000200
-      #define AVE_OUT_STATUS_VSYNC_CLR                           0xfffffdff
-      #define AVE_OUT_STATUS_VSYNC_MSB                           9
-      #define AVE_OUT_STATUS_VSYNC_LSB                           9
-      #define AVE_OUT_STATUS_VBACK_PORCH_BITS                    8:8
-      #define AVE_OUT_STATUS_VBACK_PORCH_SET                     0x00000100
-      #define AVE_OUT_STATUS_VBACK_PORCH_CLR                     0xfffffeff
-      #define AVE_OUT_STATUS_VBACK_PORCH_MSB                     8
-      #define AVE_OUT_STATUS_VBACK_PORCH_LSB                     8
-      #define AVE_OUT_STATUS_VFRONT_PORCH_BITS                   7:7
-      #define AVE_OUT_STATUS_VFRONT_PORCH_SET                    0x00000080
-      #define AVE_OUT_STATUS_VFRONT_PORCH_CLR                    0xffffff7f
-      #define AVE_OUT_STATUS_VFRONT_PORCH_MSB                    7
-      #define AVE_OUT_STATUS_VFRONT_PORCH_LSB                    7
-      #define AVE_OUT_STATUS_HSYNC_BITS                          6:6
-      #define AVE_OUT_STATUS_HSYNC_SET                           0x00000040
-      #define AVE_OUT_STATUS_HSYNC_CLR                           0xffffffbf
-      #define AVE_OUT_STATUS_HSYNC_MSB                           6
-      #define AVE_OUT_STATUS_HSYNC_LSB                           6
-      #define AVE_OUT_STATUS_HBACK_PORCH_BITS                    5:5
-      #define AVE_OUT_STATUS_HBACK_PORCH_SET                     0x00000020
-      #define AVE_OUT_STATUS_HBACK_PORCH_CLR                     0xffffffdf
-      #define AVE_OUT_STATUS_HBACK_PORCH_MSB                     5
-      #define AVE_OUT_STATUS_HBACK_PORCH_LSB                     5
-      #define AVE_OUT_STATUS_HFRONT_PORCH_BITS                   4:4
-      #define AVE_OUT_STATUS_HFRONT_PORCH_SET                    0x00000010
-      #define AVE_OUT_STATUS_HFRONT_PORCH_CLR                    0xffffffef
-      #define AVE_OUT_STATUS_HFRONT_PORCH_MSB                    4
-      #define AVE_OUT_STATUS_HFRONT_PORCH_LSB                    4
-      #define AVE_OUT_STATUS_COEFF_ERROR_BITS                    2:2
-      #define AVE_OUT_STATUS_COEFF_ERROR_SET                     0x00000004
-      #define AVE_OUT_STATUS_COEFF_ERROR_CLR                     0xfffffffb
-      #define AVE_OUT_STATUS_COEFF_ERROR_MSB                     2
-      #define AVE_OUT_STATUS_COEFF_ERROR_LSB                     2
-      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_BITS               1:1
-      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_SET                0x00000002
-      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_CLR                0xfffffffd
-      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_MSB                1
-      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_LSB                1
-      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_BITS               0:0
-      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_SET                0x00000001
-      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_CLR                0xfffffffe
-      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_MSB                0
-      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_LSB                0
-#define AVE_OUT_OFFSET                                           HW_REGISTER_RW( 0x7e240008 ) 
-   #define AVE_OUT_OFFSET_MASK                                   0x80ffffff
-   #define AVE_OUT_OFFSET_WIDTH                                  32
-   #define AVE_OUT_OFFSET_RESET                                  0x80109090
-      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_BITS              31:31
-      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_SET               0x80000000
-      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_CLR               0x7fffffff
-      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_MSB               31
-      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_LSB               31
-      #define AVE_OUT_OFFSET_RED_OFFSET_BITS                     23:16
-      #define AVE_OUT_OFFSET_RED_OFFSET_SET                      0x00ff0000
-      #define AVE_OUT_OFFSET_RED_OFFSET_CLR                      0xff00ffff
-      #define AVE_OUT_OFFSET_RED_OFFSET_MSB                      23
-      #define AVE_OUT_OFFSET_RED_OFFSET_LSB                      16
-      #define AVE_OUT_OFFSET_GREEN_OFFSET_BITS                   15:8
-      #define AVE_OUT_OFFSET_GREEN_OFFSET_SET                    0x0000ff00
-      #define AVE_OUT_OFFSET_GREEN_OFFSET_CLR                    0xffff00ff
-      #define AVE_OUT_OFFSET_GREEN_OFFSET_MSB                    15
-      #define AVE_OUT_OFFSET_GREEN_OFFSET_LSB                    8
-      #define AVE_OUT_OFFSET_BLUE_OFFSET_BITS                    7:0
-      #define AVE_OUT_OFFSET_BLUE_OFFSET_SET                     0x000000ff
-      #define AVE_OUT_OFFSET_BLUE_OFFSET_CLR                     0xffffff00
-      #define AVE_OUT_OFFSET_BLUE_OFFSET_MSB                     7
-      #define AVE_OUT_OFFSET_BLUE_OFFSET_LSB                     0
-#define AVE_OUT_Y_COEFF                                          HW_REGISTER_RW( 0x7e24000c ) 
-   #define AVE_OUT_Y_COEFF_MASK                                  0x3fffffff
-   #define AVE_OUT_Y_COEFF_WIDTH                                 30
-   #define AVE_OUT_Y_COEFF_RESET                                 0x0994b43a
-      #define AVE_OUT_Y_COEFF_RED_COEFF_BITS                     29:20
-      #define AVE_OUT_Y_COEFF_RED_COEFF_SET                      0x3ff00000
-      #define AVE_OUT_Y_COEFF_RED_COEFF_CLR                      0xc00fffff
-      #define AVE_OUT_Y_COEFF_RED_COEFF_MSB                      29
-      #define AVE_OUT_Y_COEFF_RED_COEFF_LSB                      20
-      #define AVE_OUT_Y_COEFF_GREEN_COEFF_BITS                   19:10
-      #define AVE_OUT_Y_COEFF_GREEN_COEFF_SET                    0x000ffc00
-      #define AVE_OUT_Y_COEFF_GREEN_COEFF_CLR                    0xfff003ff
-      #define AVE_OUT_Y_COEFF_GREEN_COEFF_MSB                    19
-      #define AVE_OUT_Y_COEFF_GREEN_COEFF_LSB                    10
-      #define AVE_OUT_Y_COEFF_BLUE_COEFF_BITS                    9:0
-      #define AVE_OUT_Y_COEFF_BLUE_COEFF_SET                     0x000003ff
-      #define AVE_OUT_Y_COEFF_BLUE_COEFF_CLR                     0xfffffc00
-      #define AVE_OUT_Y_COEFF_BLUE_COEFF_MSB                     9
-      #define AVE_OUT_Y_COEFF_BLUE_COEFF_LSB                     0
-#define AVE_OUT_CB_COEFF                                         HW_REGISTER_RW( 0x7e240010 ) 
-   #define AVE_OUT_CB_COEFF_MASK                                 0x3fffffff
-   #define AVE_OUT_CB_COEFF_WIDTH                                30
-   #define AVE_OUT_CB_COEFF_RESET                                0x3a9d5900
-      #define AVE_OUT_CB_COEFF_RED_COEFF_BITS                    29:20
-      #define AVE_OUT_CB_COEFF_RED_COEFF_SET                     0x3ff00000
-      #define AVE_OUT_CB_COEFF_RED_COEFF_CLR                     0xc00fffff
-      #define AVE_OUT_CB_COEFF_RED_COEFF_MSB                     29
-      #define AVE_OUT_CB_COEFF_RED_COEFF_LSB                     20
-      #define AVE_OUT_CB_COEFF_GREEN_COEFF_BITS                  19:10
-      #define AVE_OUT_CB_COEFF_GREEN_COEFF_SET                   0x000ffc00
-      #define AVE_OUT_CB_COEFF_GREEN_COEFF_CLR                   0xfff003ff
-      #define AVE_OUT_CB_COEFF_GREEN_COEFF_MSB                   19
-      #define AVE_OUT_CB_COEFF_GREEN_COEFF_LSB                   10
-      #define AVE_OUT_CB_COEFF_BLUE_COEFF_BITS                   9:0
-      #define AVE_OUT_CB_COEFF_BLUE_COEFF_SET                    0x000003ff
-      #define AVE_OUT_CB_COEFF_BLUE_COEFF_CLR                    0xfffffc00
-      #define AVE_OUT_CB_COEFF_BLUE_COEFF_MSB                    9
-      #define AVE_OUT_CB_COEFF_BLUE_COEFF_LSB                    0
-#define AVE_OUT_CR_COEFF                                         HW_REGISTER_RW( 0x7e240014 ) 
-   #define AVE_OUT_CR_COEFF_MASK                                 0x3fffffff
-   #define AVE_OUT_CR_COEFF_WIDTH                                30
-   #define AVE_OUT_CR_COEFF_RESET                                0x100ca7d6
-      #define AVE_OUT_CR_COEFF_RED_COEFF_BITS                    29:20
-      #define AVE_OUT_CR_COEFF_RED_COEFF_SET                     0x3ff00000
-      #define AVE_OUT_CR_COEFF_RED_COEFF_CLR                     0xc00fffff
-      #define AVE_OUT_CR_COEFF_RED_COEFF_MSB                     29
-      #define AVE_OUT_CR_COEFF_RED_COEFF_LSB                     20
-      #define AVE_OUT_CR_COEFF_GREEN_COEFF_BITS                  19:10
-      #define AVE_OUT_CR_COEFF_GREEN_COEFF_SET                   0x000ffc00
-      #define AVE_OUT_CR_COEFF_GREEN_COEFF_CLR                   0xfff003ff
-      #define AVE_OUT_CR_COEFF_GREEN_COEFF_MSB                   19
-      #define AVE_OUT_CR_COEFF_GREEN_COEFF_LSB                   10
-      #define AVE_OUT_CR_COEFF_BLUE_COEFF_BITS                   9:0
-      #define AVE_OUT_CR_COEFF_BLUE_COEFF_SET                    0x000003ff
-      #define AVE_OUT_CR_COEFF_BLUE_COEFF_CLR                    0xfffffc00
-      #define AVE_OUT_CR_COEFF_BLUE_COEFF_MSB                    9
-      #define AVE_OUT_CR_COEFF_BLUE_COEFF_LSB                    0
-#define AVE_OUT_BLOCK_ID                                         HW_REGISTER_RW( 0x7e240060 ) 
-   #define AVE_OUT_BLOCK_ID_MASK                                 0xffffffff
-   #define AVE_OUT_BLOCK_ID_WIDTH                                32
-   #define AVE_OUT_BLOCK_ID_RESET                                0x61766538
diff --git a/bcm2708_chip/axi_dma0.h b/bcm2708_chip/axi_dma0.h
deleted file mode 100644 (file)
index 897e88b..0000000
+++ /dev/null
@@ -1,257 +0,0 @@
-// This file was generated by the create_regs script
-#define DMA0_BASE                                                0x7e007000
-#define DMA0_CS                                                  HW_REGISTER_RW( 0x7e007000 ) 
-   #define DMA0_CS_MASK                                          0xf0ff017f
-   #define DMA0_CS_WIDTH                                         32
-   #define DMA0_CS_RESET                                         0000000000
-      #define DMA0_CS_RESET_BITS                                 31:31
-      #define DMA0_CS_RESET_SET                                  0x80000000
-      #define DMA0_CS_RESET_CLR                                  0x7fffffff
-      #define DMA0_CS_RESET_MSB                                  31
-      #define DMA0_CS_RESET_LSB                                  31
-      #define DMA0_CS_ABORT_BITS                                 30:30
-      #define DMA0_CS_ABORT_SET                                  0x40000000
-      #define DMA0_CS_ABORT_CLR                                  0xbfffffff
-      #define DMA0_CS_ABORT_MSB                                  30
-      #define DMA0_CS_ABORT_LSB                                  30
-      #define DMA0_CS_DISDEBUG_BITS                              29:29
-      #define DMA0_CS_DISDEBUG_SET                               0x20000000
-      #define DMA0_CS_DISDEBUG_CLR                               0xdfffffff
-      #define DMA0_CS_DISDEBUG_MSB                               29
-      #define DMA0_CS_DISDEBUG_LSB                               29
-      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
-      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
-      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
-      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
-      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
-      #define DMA0_CS_PANIC_PRIORITY_BITS                        23:20
-      #define DMA0_CS_PANIC_PRIORITY_SET                         0x00f00000
-      #define DMA0_CS_PANIC_PRIORITY_CLR                         0xff0fffff
-      #define DMA0_CS_PANIC_PRIORITY_MSB                         23
-      #define DMA0_CS_PANIC_PRIORITY_LSB                         20
-      #define DMA0_CS_PRIORITY_BITS                              19:16
-      #define DMA0_CS_PRIORITY_SET                               0x000f0000
-      #define DMA0_CS_PRIORITY_CLR                               0xfff0ffff
-      #define DMA0_CS_PRIORITY_MSB                               19
-      #define DMA0_CS_PRIORITY_LSB                               16
-      #define DMA0_CS_ERROR_BITS                                 8:8
-      #define DMA0_CS_ERROR_SET                                  0x00000100
-      #define DMA0_CS_ERROR_CLR                                  0xfffffeff
-      #define DMA0_CS_ERROR_MSB                                  8
-      #define DMA0_CS_ERROR_LSB                                  8
-      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
-      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
-      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
-      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
-      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
-      #define DMA0_CS_DREQ_STOPS_DMA_BITS                        5:5
-      #define DMA0_CS_DREQ_STOPS_DMA_SET                         0x00000020
-      #define DMA0_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
-      #define DMA0_CS_DREQ_STOPS_DMA_MSB                         5
-      #define DMA0_CS_DREQ_STOPS_DMA_LSB                         5
-      #define DMA0_CS_PAUSED_BITS                                4:4
-      #define DMA0_CS_PAUSED_SET                                 0x00000010
-      #define DMA0_CS_PAUSED_CLR                                 0xffffffef
-      #define DMA0_CS_PAUSED_MSB                                 4
-      #define DMA0_CS_PAUSED_LSB                                 4
-      #define DMA0_CS_DREQ_BITS                                  3:3
-      #define DMA0_CS_DREQ_SET                                   0x00000008
-      #define DMA0_CS_DREQ_CLR                                   0xfffffff7
-      #define DMA0_CS_DREQ_MSB                                   3
-      #define DMA0_CS_DREQ_LSB                                   3
-      #define DMA0_CS_INT_BITS                                   2:2
-      #define DMA0_CS_INT_SET                                    0x00000004
-      #define DMA0_CS_INT_CLR                                    0xfffffffb
-      #define DMA0_CS_INT_MSB                                    2
-      #define DMA0_CS_INT_LSB                                    2
-      #define DMA0_CS_END_BITS                                   1:1
-      #define DMA0_CS_END_SET                                    0x00000002
-      #define DMA0_CS_END_CLR                                    0xfffffffd
-      #define DMA0_CS_END_MSB                                    1
-      #define DMA0_CS_END_LSB                                    1
-      #define DMA0_CS_ACTIVE_BITS                                0:0
-      #define DMA0_CS_ACTIVE_SET                                 0x00000001
-      #define DMA0_CS_ACTIVE_CLR                                 0xfffffffe
-      #define DMA0_CS_ACTIVE_MSB                                 0
-      #define DMA0_CS_ACTIVE_LSB                                 0
-#define DMA0_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007004 ) 
-   #define DMA0_CONBLK_AD_MASK                                   0xffffffe0
-   #define DMA0_CONBLK_AD_WIDTH                                  32
-   #define DMA0_CONBLK_AD_RESET                                  0000000000
-      #define DMA0_CONBLK_AD_SCB_ADDR_BITS                       31:5
-      #define DMA0_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
-      #define DMA0_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
-      #define DMA0_CONBLK_AD_SCB_ADDR_MSB                        31
-      #define DMA0_CONBLK_AD_SCB_ADDR_LSB                        5
-#define DMA0_TI                                                  HW_REGISTER_RO( 0x7e007008 ) 
-   #define DMA0_TI_MASK                                          0x07fffffb
-   #define DMA0_TI_WIDTH                                         27
-      #define DMA0_TI_NO_WIDE_BURSTS_BITS                        26:26
-      #define DMA0_TI_NO_WIDE_BURSTS_SET                         0x04000000
-      #define DMA0_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
-      #define DMA0_TI_NO_WIDE_BURSTS_MSB                         26
-      #define DMA0_TI_NO_WIDE_BURSTS_LSB                         26
-      #define DMA0_TI_WAITS_BITS                                 25:21
-      #define DMA0_TI_WAITS_SET                                  0x03e00000
-      #define DMA0_TI_WAITS_CLR                                  0xfc1fffff
-      #define DMA0_TI_WAITS_MSB                                  25
-      #define DMA0_TI_WAITS_LSB                                  21
-      #define DMA0_TI_PERMAP_BITS                                20:16
-      #define DMA0_TI_PERMAP_SET                                 0x001f0000
-      #define DMA0_TI_PERMAP_CLR                                 0xffe0ffff
-      #define DMA0_TI_PERMAP_MSB                                 20
-      #define DMA0_TI_PERMAP_LSB                                 16
-      #define DMA0_TI_BURST_LENGTH_BITS                          15:12
-      #define DMA0_TI_BURST_LENGTH_SET                           0x0000f000
-      #define DMA0_TI_BURST_LENGTH_CLR                           0xffff0fff
-      #define DMA0_TI_BURST_LENGTH_MSB                           15
-      #define DMA0_TI_BURST_LENGTH_LSB                           12
-      #define DMA0_TI_SRC_IGNORE_BITS                            11:11
-      #define DMA0_TI_SRC_IGNORE_SET                             0x00000800
-      #define DMA0_TI_SRC_IGNORE_CLR                             0xfffff7ff
-      #define DMA0_TI_SRC_IGNORE_MSB                             11
-      #define DMA0_TI_SRC_IGNORE_LSB                             11
-      #define DMA0_TI_SRC_DREQ_BITS                              10:10
-      #define DMA0_TI_SRC_DREQ_SET                               0x00000400
-      #define DMA0_TI_SRC_DREQ_CLR                               0xfffffbff
-      #define DMA0_TI_SRC_DREQ_MSB                               10
-      #define DMA0_TI_SRC_DREQ_LSB                               10
-      #define DMA0_TI_SRC_WIDTH_BITS                             9:9
-      #define DMA0_TI_SRC_WIDTH_SET                              0x00000200
-      #define DMA0_TI_SRC_WIDTH_CLR                              0xfffffdff
-      #define DMA0_TI_SRC_WIDTH_MSB                              9
-      #define DMA0_TI_SRC_WIDTH_LSB                              9
-      #define DMA0_TI_SRC_INC_BITS                               8:8
-      #define DMA0_TI_SRC_INC_SET                                0x00000100
-      #define DMA0_TI_SRC_INC_CLR                                0xfffffeff
-      #define DMA0_TI_SRC_INC_MSB                                8
-      #define DMA0_TI_SRC_INC_LSB                                8
-      #define DMA0_TI_DEST_IGNORE_BITS                           7:7
-      #define DMA0_TI_DEST_IGNORE_SET                            0x00000080
-      #define DMA0_TI_DEST_IGNORE_CLR                            0xffffff7f
-      #define DMA0_TI_DEST_IGNORE_MSB                            7
-      #define DMA0_TI_DEST_IGNORE_LSB                            7
-      #define DMA0_TI_DEST_DREQ_BITS                             6:6
-      #define DMA0_TI_DEST_DREQ_SET                              0x00000040
-      #define DMA0_TI_DEST_DREQ_CLR                              0xffffffbf
-      #define DMA0_TI_DEST_DREQ_MSB                              6
-      #define DMA0_TI_DEST_DREQ_LSB                              6
-      #define DMA0_TI_DEST_WIDTH_BITS                            5:5
-      #define DMA0_TI_DEST_WIDTH_SET                             0x00000020
-      #define DMA0_TI_DEST_WIDTH_CLR                             0xffffffdf
-      #define DMA0_TI_DEST_WIDTH_MSB                             5
-      #define DMA0_TI_DEST_WIDTH_LSB                             5
-      #define DMA0_TI_DEST_INC_BITS                              4:4
-      #define DMA0_TI_DEST_INC_SET                               0x00000010
-      #define DMA0_TI_DEST_INC_CLR                               0xffffffef
-      #define DMA0_TI_DEST_INC_MSB                               4
-      #define DMA0_TI_DEST_INC_LSB                               4
-      #define DMA0_TI_WAIT_RESP_BITS                             3:3
-      #define DMA0_TI_WAIT_RESP_SET                              0x00000008
-      #define DMA0_TI_WAIT_RESP_CLR                              0xfffffff7
-      #define DMA0_TI_WAIT_RESP_MSB                              3
-      #define DMA0_TI_WAIT_RESP_LSB                              3
-      #define DMA0_TI_TDMODE_BITS                                1:1
-      #define DMA0_TI_TDMODE_SET                                 0x00000002
-      #define DMA0_TI_TDMODE_CLR                                 0xfffffffd
-      #define DMA0_TI_TDMODE_MSB                                 1
-      #define DMA0_TI_TDMODE_LSB                                 1
-      #define DMA0_TI_INTEN_BITS                                 0:0
-      #define DMA0_TI_INTEN_SET                                  0x00000001
-      #define DMA0_TI_INTEN_CLR                                  0xfffffffe
-      #define DMA0_TI_INTEN_MSB                                  0
-      #define DMA0_TI_INTEN_LSB                                  0
-#define DMA0_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00700c ) 
-   #define DMA0_SOURCE_AD_MASK                                   0xffffffff
-   #define DMA0_SOURCE_AD_WIDTH                                  32
-      #define DMA0_SOURCE_AD_S_ADDR_BITS                         31:0
-      #define DMA0_SOURCE_AD_S_ADDR_SET                          0xffffffff
-      #define DMA0_SOURCE_AD_S_ADDR_CLR                          0x00000000
-      #define DMA0_SOURCE_AD_S_ADDR_MSB                          31
-      #define DMA0_SOURCE_AD_S_ADDR_LSB                          0
-#define DMA0_DEST_AD                                             HW_REGISTER_RO( 0x7e007010 ) 
-   #define DMA0_DEST_AD_MASK                                     0xffffffff
-   #define DMA0_DEST_AD_WIDTH                                    32
-      #define DMA0_DEST_AD_D_ADDR_BITS                           31:0
-      #define DMA0_DEST_AD_D_ADDR_SET                            0xffffffff
-      #define DMA0_DEST_AD_D_ADDR_CLR                            0x00000000
-      #define DMA0_DEST_AD_D_ADDR_MSB                            31
-      #define DMA0_DEST_AD_D_ADDR_LSB                            0
-#define DMA0_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007014 ) 
-   #define DMA0_TXFR_LEN_MASK                                    0x3fffffff
-   #define DMA0_TXFR_LEN_WIDTH                                   30
-      #define DMA0_TXFR_LEN_YLENGTH_BITS                         29:16
-      #define DMA0_TXFR_LEN_YLENGTH_SET                          0x3fff0000
-      #define DMA0_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
-      #define DMA0_TXFR_LEN_YLENGTH_MSB                          29
-      #define DMA0_TXFR_LEN_YLENGTH_LSB                          16
-      #define DMA0_TXFR_LEN_XLENGTH_BITS                         15:0
-      #define DMA0_TXFR_LEN_XLENGTH_SET                          0x0000ffff
-      #define DMA0_TXFR_LEN_XLENGTH_CLR                          0xffff0000
-      #define DMA0_TXFR_LEN_XLENGTH_MSB                          15
-      #define DMA0_TXFR_LEN_XLENGTH_LSB                          0
-#define DMA0_STRIDE                                              HW_REGISTER_RO( 0x7e007018 ) 
-   #define DMA0_STRIDE_MASK                                      0xffffffff
-   #define DMA0_STRIDE_WIDTH                                     32
-      #define DMA0_STRIDE_D_STRIDE_BITS                          31:16
-      #define DMA0_STRIDE_D_STRIDE_SET                           0xffff0000
-      #define DMA0_STRIDE_D_STRIDE_CLR                           0x0000ffff
-      #define DMA0_STRIDE_D_STRIDE_MSB                           31
-      #define DMA0_STRIDE_D_STRIDE_LSB                           16
-      #define DMA0_STRIDE_S_STRIDE_BITS                          15:0
-      #define DMA0_STRIDE_S_STRIDE_SET                           0x0000ffff
-      #define DMA0_STRIDE_S_STRIDE_CLR                           0xffff0000
-      #define DMA0_STRIDE_S_STRIDE_MSB                           15
-      #define DMA0_STRIDE_S_STRIDE_LSB                           0
-#define DMA0_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00701c ) 
-   #define DMA0_NEXTCONBK_MASK                                   0xffffffe0
-   #define DMA0_NEXTCONBK_WIDTH                                  32
-      #define DMA0_NEXTCONBK_ADDR_BITS                           31:5
-      #define DMA0_NEXTCONBK_ADDR_SET                            0xffffffe0
-      #define DMA0_NEXTCONBK_ADDR_CLR                            0x0000001f
-      #define DMA0_NEXTCONBK_ADDR_MSB                            31
-      #define DMA0_NEXTCONBK_ADDR_LSB                            5
-#define DMA0_DEBUG                                               HW_REGISTER_RW( 0x7e007020 ) 
-   #define DMA0_DEBUG_MASK                                       0x1ffffff7
-   #define DMA0_DEBUG_WIDTH                                      29
-   #define DMA0_DEBUG_RESET                                      0000000000
-      #define DMA0_DEBUG_LITE_BITS                               28:28
-      #define DMA0_DEBUG_LITE_SET                                0x10000000
-      #define DMA0_DEBUG_LITE_CLR                                0xefffffff
-      #define DMA0_DEBUG_LITE_MSB                                28
-      #define DMA0_DEBUG_LITE_LSB                                28
-      #define DMA0_DEBUG_VERSION_BITS                            27:25
-      #define DMA0_DEBUG_VERSION_SET                             0x0e000000
-      #define DMA0_DEBUG_VERSION_CLR                             0xf1ffffff
-      #define DMA0_DEBUG_VERSION_MSB                             27
-      #define DMA0_DEBUG_VERSION_LSB                             25
-      #define DMA0_DEBUG_DMA_STATE_BITS                          24:16
-      #define DMA0_DEBUG_DMA_STATE_SET                           0x01ff0000
-      #define DMA0_DEBUG_DMA_STATE_CLR                           0xfe00ffff
-      #define DMA0_DEBUG_DMA_STATE_MSB                           24
-      #define DMA0_DEBUG_DMA_STATE_LSB                           16
-      #define DMA0_DEBUG_DMA_ID_BITS                             15:8
-      #define DMA0_DEBUG_DMA_ID_SET                              0x0000ff00
-      #define DMA0_DEBUG_DMA_ID_CLR                              0xffff00ff
-      #define DMA0_DEBUG_DMA_ID_MSB                              15
-      #define DMA0_DEBUG_DMA_ID_LSB                              8
-      #define DMA0_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
-      #define DMA0_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
-      #define DMA0_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
-      #define DMA0_DEBUG_OUTSTANDING_WRITES_MSB                  7
-      #define DMA0_DEBUG_OUTSTANDING_WRITES_LSB                  4
-      #define DMA0_DEBUG_READ_ERROR_BITS                         2:2
-      #define DMA0_DEBUG_READ_ERROR_SET                          0x00000004
-      #define DMA0_DEBUG_READ_ERROR_CLR                          0xfffffffb
-      #define DMA0_DEBUG_READ_ERROR_MSB                          2
-      #define DMA0_DEBUG_READ_ERROR_LSB                          2
-      #define DMA0_DEBUG_FIFO_ERROR_BITS                         1:1
-      #define DMA0_DEBUG_FIFO_ERROR_SET                          0x00000002
-      #define DMA0_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
-      #define DMA0_DEBUG_FIFO_ERROR_MSB                          1
-      #define DMA0_DEBUG_FIFO_ERROR_LSB                          1
-      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
-      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
-      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
-      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
-      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma1.h b/bcm2708_chip/axi_dma1.h
deleted file mode 100644 (file)
index fa68999..0000000
+++ /dev/null
@@ -1,257 +0,0 @@
-// This file was generated by the create_regs script
-#define DMA1_BASE                                                0x7e007100
-#define DMA1_CS                                                  HW_REGISTER_RW( 0x7e007100 ) 
-   #define DMA1_CS_MASK                                          0xf0ff017f
-   #define DMA1_CS_WIDTH                                         32
-   #define DMA1_CS_RESET                                         0000000000
-      #define DMA1_CS_RESET_BITS                                 31:31
-      #define DMA1_CS_RESET_SET                                  0x80000000
-      #define DMA1_CS_RESET_CLR                                  0x7fffffff
-      #define DMA1_CS_RESET_MSB                                  31
-      #define DMA1_CS_RESET_LSB                                  31
-      #define DMA1_CS_ABORT_BITS                                 30:30
-      #define DMA1_CS_ABORT_SET                                  0x40000000
-      #define DMA1_CS_ABORT_CLR                                  0xbfffffff
-      #define DMA1_CS_ABORT_MSB                                  30
-      #define DMA1_CS_ABORT_LSB                                  30
-      #define DMA1_CS_DISDEBUG_BITS                              29:29
-      #define DMA1_CS_DISDEBUG_SET                               0x20000000
-      #define DMA1_CS_DISDEBUG_CLR                               0xdfffffff
-      #define DMA1_CS_DISDEBUG_MSB                               29
-      #define DMA1_CS_DISDEBUG_LSB                               29
-      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
-      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
-      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
-      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
-      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
-      #define DMA1_CS_PANIC_PRIORITY_BITS                        23:20
-      #define DMA1_CS_PANIC_PRIORITY_SET                         0x00f00000
-      #define DMA1_CS_PANIC_PRIORITY_CLR                         0xff0fffff
-      #define DMA1_CS_PANIC_PRIORITY_MSB                         23
-      #define DMA1_CS_PANIC_PRIORITY_LSB                         20
-      #define DMA1_CS_PRIORITY_BITS                              19:16
-      #define DMA1_CS_PRIORITY_SET                               0x000f0000
-      #define DMA1_CS_PRIORITY_CLR                               0xfff0ffff
-      #define DMA1_CS_PRIORITY_MSB                               19
-      #define DMA1_CS_PRIORITY_LSB                               16
-      #define DMA1_CS_ERROR_BITS                                 8:8
-      #define DMA1_CS_ERROR_SET                                  0x00000100
-      #define DMA1_CS_ERROR_CLR                                  0xfffffeff
-      #define DMA1_CS_ERROR_MSB                                  8
-      #define DMA1_CS_ERROR_LSB                                  8
-      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
-      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
-      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
-      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
-      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
-      #define DMA1_CS_DREQ_STOPS_DMA_BITS                        5:5
-      #define DMA1_CS_DREQ_STOPS_DMA_SET                         0x00000020
-      #define DMA1_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
-      #define DMA1_CS_DREQ_STOPS_DMA_MSB                         5
-      #define DMA1_CS_DREQ_STOPS_DMA_LSB                         5
-      #define DMA1_CS_PAUSED_BITS                                4:4
-      #define DMA1_CS_PAUSED_SET                                 0x00000010
-      #define DMA1_CS_PAUSED_CLR                                 0xffffffef
-      #define DMA1_CS_PAUSED_MSB                                 4
-      #define DMA1_CS_PAUSED_LSB                                 4
-      #define DMA1_CS_DREQ_BITS                                  3:3
-      #define DMA1_CS_DREQ_SET                                   0x00000008
-      #define DMA1_CS_DREQ_CLR                                   0xfffffff7
-      #define DMA1_CS_DREQ_MSB                                   3
-      #define DMA1_CS_DREQ_LSB                                   3
-      #define DMA1_CS_INT_BITS                                   2:2
-      #define DMA1_CS_INT_SET                                    0x00000004
-      #define DMA1_CS_INT_CLR                                    0xfffffffb
-      #define DMA1_CS_INT_MSB                                    2
-      #define DMA1_CS_INT_LSB                                    2
-      #define DMA1_CS_END_BITS                                   1:1
-      #define DMA1_CS_END_SET                                    0x00000002
-      #define DMA1_CS_END_CLR                                    0xfffffffd
-      #define DMA1_CS_END_MSB                                    1
-      #define DMA1_CS_END_LSB                                    1
-      #define DMA1_CS_ACTIVE_BITS                                0:0
-      #define DMA1_CS_ACTIVE_SET                                 0x00000001
-      #define DMA1_CS_ACTIVE_CLR                                 0xfffffffe
-      #define DMA1_CS_ACTIVE_MSB                                 0
-      #define DMA1_CS_ACTIVE_LSB                                 0
-#define DMA1_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007104 ) 
-   #define DMA1_CONBLK_AD_MASK                                   0xffffffe0
-   #define DMA1_CONBLK_AD_WIDTH                                  32
-   #define DMA1_CONBLK_AD_RESET                                  0000000000
-      #define DMA1_CONBLK_AD_SCB_ADDR_BITS                       31:5
-      #define DMA1_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
-      #define DMA1_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
-      #define DMA1_CONBLK_AD_SCB_ADDR_MSB                        31
-      #define DMA1_CONBLK_AD_SCB_ADDR_LSB                        5
-#define DMA1_TI                                                  HW_REGISTER_RO( 0x7e007108 ) 
-   #define DMA1_TI_MASK                                          0x07fffffb
-   #define DMA1_TI_WIDTH                                         27
-      #define DMA1_TI_NO_WIDE_BURSTS_BITS                        26:26
-      #define DMA1_TI_NO_WIDE_BURSTS_SET                         0x04000000
-      #define DMA1_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
-      #define DMA1_TI_NO_WIDE_BURSTS_MSB                         26
-      #define DMA1_TI_NO_WIDE_BURSTS_LSB                         26
-      #define DMA1_TI_WAITS_BITS                                 25:21
-      #define DMA1_TI_WAITS_SET                                  0x03e00000
-      #define DMA1_TI_WAITS_CLR                                  0xfc1fffff
-      #define DMA1_TI_WAITS_MSB                                  25
-      #define DMA1_TI_WAITS_LSB                                  21
-      #define DMA1_TI_PERMAP_BITS                                20:16
-      #define DMA1_TI_PERMAP_SET                                 0x001f0000
-      #define DMA1_TI_PERMAP_CLR                                 0xffe0ffff
-      #define DMA1_TI_PERMAP_MSB                                 20
-      #define DMA1_TI_PERMAP_LSB                                 16
-      #define DMA1_TI_BURST_LENGTH_BITS                          15:12
-      #define DMA1_TI_BURST_LENGTH_SET                           0x0000f000
-      #define DMA1_TI_BURST_LENGTH_CLR                           0xffff0fff
-      #define DMA1_TI_BURST_LENGTH_MSB                           15
-      #define DMA1_TI_BURST_LENGTH_LSB                           12
-      #define DMA1_TI_SRC_IGNORE_BITS                            11:11
-      #define DMA1_TI_SRC_IGNORE_SET                             0x00000800
-      #define DMA1_TI_SRC_IGNORE_CLR                             0xfffff7ff
-      #define DMA1_TI_SRC_IGNORE_MSB                             11
-      #define DMA1_TI_SRC_IGNORE_LSB                             11
-      #define DMA1_TI_SRC_DREQ_BITS                              10:10
-      #define DMA1_TI_SRC_DREQ_SET                               0x00000400
-      #define DMA1_TI_SRC_DREQ_CLR                               0xfffffbff
-      #define DMA1_TI_SRC_DREQ_MSB                               10
-      #define DMA1_TI_SRC_DREQ_LSB                               10
-      #define DMA1_TI_SRC_WIDTH_BITS                             9:9
-      #define DMA1_TI_SRC_WIDTH_SET                              0x00000200
-      #define DMA1_TI_SRC_WIDTH_CLR                              0xfffffdff
-      #define DMA1_TI_SRC_WIDTH_MSB                              9
-      #define DMA1_TI_SRC_WIDTH_LSB                              9
-      #define DMA1_TI_SRC_INC_BITS                               8:8
-      #define DMA1_TI_SRC_INC_SET                                0x00000100
-      #define DMA1_TI_SRC_INC_CLR                                0xfffffeff
-      #define DMA1_TI_SRC_INC_MSB                                8
-      #define DMA1_TI_SRC_INC_LSB                                8
-      #define DMA1_TI_DEST_IGNORE_BITS                           7:7
-      #define DMA1_TI_DEST_IGNORE_SET                            0x00000080
-      #define DMA1_TI_DEST_IGNORE_CLR                            0xffffff7f
-      #define DMA1_TI_DEST_IGNORE_MSB                            7
-      #define DMA1_TI_DEST_IGNORE_LSB                            7
-      #define DMA1_TI_DEST_DREQ_BITS                             6:6
-      #define DMA1_TI_DEST_DREQ_SET                              0x00000040
-      #define DMA1_TI_DEST_DREQ_CLR                              0xffffffbf
-      #define DMA1_TI_DEST_DREQ_MSB                              6
-      #define DMA1_TI_DEST_DREQ_LSB                              6
-      #define DMA1_TI_DEST_WIDTH_BITS                            5:5
-      #define DMA1_TI_DEST_WIDTH_SET                             0x00000020
-      #define DMA1_TI_DEST_WIDTH_CLR                             0xffffffdf
-      #define DMA1_TI_DEST_WIDTH_MSB                             5
-      #define DMA1_TI_DEST_WIDTH_LSB                             5
-      #define DMA1_TI_DEST_INC_BITS                              4:4
-      #define DMA1_TI_DEST_INC_SET                               0x00000010
-      #define DMA1_TI_DEST_INC_CLR                               0xffffffef
-      #define DMA1_TI_DEST_INC_MSB                               4
-      #define DMA1_TI_DEST_INC_LSB                               4
-      #define DMA1_TI_WAIT_RESP_BITS                             3:3
-      #define DMA1_TI_WAIT_RESP_SET                              0x00000008
-      #define DMA1_TI_WAIT_RESP_CLR                              0xfffffff7
-      #define DMA1_TI_WAIT_RESP_MSB                              3
-      #define DMA1_TI_WAIT_RESP_LSB                              3
-      #define DMA1_TI_TDMODE_BITS                                1:1
-      #define DMA1_TI_TDMODE_SET                                 0x00000002
-      #define DMA1_TI_TDMODE_CLR                                 0xfffffffd
-      #define DMA1_TI_TDMODE_MSB                                 1
-      #define DMA1_TI_TDMODE_LSB                                 1
-      #define DMA1_TI_INTEN_BITS                                 0:0
-      #define DMA1_TI_INTEN_SET                                  0x00000001
-      #define DMA1_TI_INTEN_CLR                                  0xfffffffe
-      #define DMA1_TI_INTEN_MSB                                  0
-      #define DMA1_TI_INTEN_LSB                                  0
-#define DMA1_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00710c ) 
-   #define DMA1_SOURCE_AD_MASK                                   0xffffffff
-   #define DMA1_SOURCE_AD_WIDTH                                  32
-      #define DMA1_SOURCE_AD_S_ADDR_BITS                         31:0
-      #define DMA1_SOURCE_AD_S_ADDR_SET                          0xffffffff
-      #define DMA1_SOURCE_AD_S_ADDR_CLR                          0x00000000
-      #define DMA1_SOURCE_AD_S_ADDR_MSB                          31
-      #define DMA1_SOURCE_AD_S_ADDR_LSB                          0
-#define DMA1_DEST_AD                                             HW_REGISTER_RO( 0x7e007110 ) 
-   #define DMA1_DEST_AD_MASK                                     0xffffffff
-   #define DMA1_DEST_AD_WIDTH                                    32
-      #define DMA1_DEST_AD_D_ADDR_BITS                           31:0
-      #define DMA1_DEST_AD_D_ADDR_SET                            0xffffffff
-      #define DMA1_DEST_AD_D_ADDR_CLR                            0x00000000
-      #define DMA1_DEST_AD_D_ADDR_MSB                            31
-      #define DMA1_DEST_AD_D_ADDR_LSB                            0
-#define DMA1_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007114 ) 
-   #define DMA1_TXFR_LEN_MASK                                    0x3fffffff
-   #define DMA1_TXFR_LEN_WIDTH                                   30
-      #define DMA1_TXFR_LEN_YLENGTH_BITS                         29:16
-      #define DMA1_TXFR_LEN_YLENGTH_SET                          0x3fff0000
-      #define DMA1_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
-      #define DMA1_TXFR_LEN_YLENGTH_MSB                          29
-      #define DMA1_TXFR_LEN_YLENGTH_LSB                          16
-      #define DMA1_TXFR_LEN_XLENGTH_BITS                         15:0
-      #define DMA1_TXFR_LEN_XLENGTH_SET                          0x0000ffff
-      #define DMA1_TXFR_LEN_XLENGTH_CLR                          0xffff0000
-      #define DMA1_TXFR_LEN_XLENGTH_MSB                          15
-      #define DMA1_TXFR_LEN_XLENGTH_LSB                          0
-#define DMA1_STRIDE                                              HW_REGISTER_RO( 0x7e007118 ) 
-   #define DMA1_STRIDE_MASK                                      0xffffffff
-   #define DMA1_STRIDE_WIDTH                                     32
-      #define DMA1_STRIDE_D_STRIDE_BITS                          31:16
-      #define DMA1_STRIDE_D_STRIDE_SET                           0xffff0000
-      #define DMA1_STRIDE_D_STRIDE_CLR                           0x0000ffff
-      #define DMA1_STRIDE_D_STRIDE_MSB                           31
-      #define DMA1_STRIDE_D_STRIDE_LSB                           16
-      #define DMA1_STRIDE_S_STRIDE_BITS                          15:0
-      #define DMA1_STRIDE_S_STRIDE_SET                           0x0000ffff
-      #define DMA1_STRIDE_S_STRIDE_CLR                           0xffff0000
-      #define DMA1_STRIDE_S_STRIDE_MSB                           15
-      #define DMA1_STRIDE_S_STRIDE_LSB                           0
-#define DMA1_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00711c ) 
-   #define DMA1_NEXTCONBK_MASK                                   0xffffffe0
-   #define DMA1_NEXTCONBK_WIDTH                                  32
-      #define DMA1_NEXTCONBK_ADDR_BITS                           31:5
-      #define DMA1_NEXTCONBK_ADDR_SET                            0xffffffe0
-      #define DMA1_NEXTCONBK_ADDR_CLR                            0x0000001f
-      #define DMA1_NEXTCONBK_ADDR_MSB                            31
-      #define DMA1_NEXTCONBK_ADDR_LSB                            5
-#define DMA1_DEBUG                                               HW_REGISTER_RW( 0x7e007120 ) 
-   #define DMA1_DEBUG_MASK                                       0x1ffffff7
-   #define DMA1_DEBUG_WIDTH                                      29
-   #define DMA1_DEBUG_RESET                                      0000000000
-      #define DMA1_DEBUG_LITE_BITS                               28:28
-      #define DMA1_DEBUG_LITE_SET                                0x10000000
-      #define DMA1_DEBUG_LITE_CLR                                0xefffffff
-      #define DMA1_DEBUG_LITE_MSB                                28
-      #define DMA1_DEBUG_LITE_LSB                                28
-      #define DMA1_DEBUG_VERSION_BITS                            27:25
-      #define DMA1_DEBUG_VERSION_SET                             0x0e000000
-      #define DMA1_DEBUG_VERSION_CLR                             0xf1ffffff
-      #define DMA1_DEBUG_VERSION_MSB                             27
-      #define DMA1_DEBUG_VERSION_LSB                             25
-      #define DMA1_DEBUG_DMA_STATE_BITS                          24:16
-      #define DMA1_DEBUG_DMA_STATE_SET                           0x01ff0000
-      #define DMA1_DEBUG_DMA_STATE_CLR                           0xfe00ffff
-      #define DMA1_DEBUG_DMA_STATE_MSB                           24
-      #define DMA1_DEBUG_DMA_STATE_LSB                           16
-      #define DMA1_DEBUG_DMA_ID_BITS                             15:8
-      #define DMA1_DEBUG_DMA_ID_SET                              0x0000ff00
-      #define DMA1_DEBUG_DMA_ID_CLR                              0xffff00ff
-      #define DMA1_DEBUG_DMA_ID_MSB                              15
-      #define DMA1_DEBUG_DMA_ID_LSB                              8
-      #define DMA1_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
-      #define DMA1_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
-      #define DMA1_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
-      #define DMA1_DEBUG_OUTSTANDING_WRITES_MSB                  7
-      #define DMA1_DEBUG_OUTSTANDING_WRITES_LSB                  4
-      #define DMA1_DEBUG_READ_ERROR_BITS                         2:2
-      #define DMA1_DEBUG_READ_ERROR_SET                          0x00000004
-      #define DMA1_DEBUG_READ_ERROR_CLR                          0xfffffffb
-      #define DMA1_DEBUG_READ_ERROR_MSB                          2
-      #define DMA1_DEBUG_READ_ERROR_LSB                          2
-      #define DMA1_DEBUG_FIFO_ERROR_BITS                         1:1
-      #define DMA1_DEBUG_FIFO_ERROR_SET                          0x00000002
-      #define DMA1_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
-      #define DMA1_DEBUG_FIFO_ERROR_MSB                          1
-      #define DMA1_DEBUG_FIFO_ERROR_LSB                          1
-      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
-      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
-      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
-      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
-      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma15.h b/bcm2708_chip/axi_dma15.h
deleted file mode 100644 (file)
index 170f80c..0000000
+++ /dev/null
@@ -1,257 +0,0 @@
-// This file was generated by the create_regs script
-#define DMA15_BASE                                               0x7ee05000
-#define DMA15_CS                                                 HW_REGISTER_RW( 0x7ee05000 ) 
-   #define DMA15_CS_MASK                                         0xf0ff017f
-   #define DMA15_CS_WIDTH                                        32
-   #define DMA15_CS_RESET                                        0000000000
-      #define DMA15_CS_RESET_BITS                                31:31
-      #define DMA15_CS_RESET_SET                                 0x80000000
-      #define DMA15_CS_RESET_CLR                                 0x7fffffff
-      #define DMA15_CS_RESET_MSB                                 31
-      #define DMA15_CS_RESET_LSB                                 31
-      #define DMA15_CS_ABORT_BITS                                30:30
-      #define DMA15_CS_ABORT_SET                                 0x40000000
-      #define DMA15_CS_ABORT_CLR                                 0xbfffffff
-      #define DMA15_CS_ABORT_MSB                                 30
-      #define DMA15_CS_ABORT_LSB                                 30
-      #define DMA15_CS_DISDEBUG_BITS                             29:29
-      #define DMA15_CS_DISDEBUG_SET                              0x20000000
-      #define DMA15_CS_DISDEBUG_CLR                              0xdfffffff
-      #define DMA15_CS_DISDEBUG_MSB                              29
-      #define DMA15_CS_DISDEBUG_LSB                              29
-      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS          28:28
-      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_SET           0x10000000
-      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR           0xefffffff
-      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB           28
-      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB           28
-      #define DMA15_CS_PANIC_PRIORITY_BITS                       23:20
-      #define DMA15_CS_PANIC_PRIORITY_SET                        0x00f00000
-      #define DMA15_CS_PANIC_PRIORITY_CLR                        0xff0fffff
-      #define DMA15_CS_PANIC_PRIORITY_MSB                        23
-      #define DMA15_CS_PANIC_PRIORITY_LSB                        20
-      #define DMA15_CS_PRIORITY_BITS                             19:16
-      #define DMA15_CS_PRIORITY_SET                              0x000f0000
-      #define DMA15_CS_PRIORITY_CLR                              0xfff0ffff
-      #define DMA15_CS_PRIORITY_MSB                              19
-      #define DMA15_CS_PRIORITY_LSB                              16
-      #define DMA15_CS_ERROR_BITS                                8:8
-      #define DMA15_CS_ERROR_SET                                 0x00000100
-      #define DMA15_CS_ERROR_CLR                                 0xfffffeff
-      #define DMA15_CS_ERROR_MSB                                 8
-      #define DMA15_CS_ERROR_LSB                                 8
-      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS       6:6
-      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_SET        0x00000040
-      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR        0xffffffbf
-      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB        6
-      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB        6
-      #define DMA15_CS_DREQ_STOPS_DMA_BITS                       5:5
-      #define DMA15_CS_DREQ_STOPS_DMA_SET                        0x00000020
-      #define DMA15_CS_DREQ_STOPS_DMA_CLR                        0xffffffdf
-      #define DMA15_CS_DREQ_STOPS_DMA_MSB                        5
-      #define DMA15_CS_DREQ_STOPS_DMA_LSB                        5
-      #define DMA15_CS_PAUSED_BITS                               4:4
-      #define DMA15_CS_PAUSED_SET                                0x00000010
-      #define DMA15_CS_PAUSED_CLR                                0xffffffef
-      #define DMA15_CS_PAUSED_MSB                                4
-      #define DMA15_CS_PAUSED_LSB                                4
-      #define DMA15_CS_DREQ_BITS                                 3:3
-      #define DMA15_CS_DREQ_SET                                  0x00000008
-      #define DMA15_CS_DREQ_CLR                                  0xfffffff7
-      #define DMA15_CS_DREQ_MSB                                  3
-      #define DMA15_CS_DREQ_LSB                                  3
-      #define DMA15_CS_INT_BITS                                  2:2
-      #define DMA15_CS_INT_SET                                   0x00000004
-      #define DMA15_CS_INT_CLR                                   0xfffffffb
-      #define DMA15_CS_INT_MSB                                   2
-      #define DMA15_CS_INT_LSB                                   2
-      #define DMA15_CS_END_BITS                                  1:1
-      #define DMA15_CS_END_SET                                   0x00000002
-      #define DMA15_CS_END_CLR                                   0xfffffffd
-      #define DMA15_CS_END_MSB                                   1
-      #define DMA15_CS_END_LSB                                   1
-      #define DMA15_CS_ACTIVE_BITS                               0:0
-      #define DMA15_CS_ACTIVE_SET                                0x00000001
-      #define DMA15_CS_ACTIVE_CLR                                0xfffffffe
-      #define DMA15_CS_ACTIVE_MSB                                0
-      #define DMA15_CS_ACTIVE_LSB                                0
-#define DMA15_CONBLK_AD                                          HW_REGISTER_RW( 0x7ee05004 ) 
-   #define DMA15_CONBLK_AD_MASK                                  0xffffffe0
-   #define DMA15_CONBLK_AD_WIDTH                                 32
-   #define DMA15_CONBLK_AD_RESET                                 0000000000
-      #define DMA15_CONBLK_AD_SCB_ADDR_BITS                      31:5
-      #define DMA15_CONBLK_AD_SCB_ADDR_SET                       0xffffffe0
-      #define DMA15_CONBLK_AD_SCB_ADDR_CLR                       0x0000001f
-      #define DMA15_CONBLK_AD_SCB_ADDR_MSB                       31
-      #define DMA15_CONBLK_AD_SCB_ADDR_LSB                       5
-#define DMA15_TI                                                 HW_REGISTER_RO( 0x7ee05008 ) 
-   #define DMA15_TI_MASK                                         0x07fffffb
-   #define DMA15_TI_WIDTH                                        27
-      #define DMA15_TI_NO_WIDE_BURSTS_BITS                       26:26
-      #define DMA15_TI_NO_WIDE_BURSTS_SET                        0x04000000
-      #define DMA15_TI_NO_WIDE_BURSTS_CLR                        0xfbffffff
-      #define DMA15_TI_NO_WIDE_BURSTS_MSB                        26
-      #define DMA15_TI_NO_WIDE_BURSTS_LSB                        26
-      #define DMA15_TI_WAITS_BITS                                25:21
-      #define DMA15_TI_WAITS_SET                                 0x03e00000
-      #define DMA15_TI_WAITS_CLR                                 0xfc1fffff
-      #define DMA15_TI_WAITS_MSB                                 25
-      #define DMA15_TI_WAITS_LSB                                 21
-      #define DMA15_TI_PERMAP_BITS                               20:16
-      #define DMA15_TI_PERMAP_SET                                0x001f0000
-      #define DMA15_TI_PERMAP_CLR                                0xffe0ffff
-      #define DMA15_TI_PERMAP_MSB                                20
-      #define DMA15_TI_PERMAP_LSB                                16
-      #define DMA15_TI_BURST_LENGTH_BITS                         15:12
-      #define DMA15_TI_BURST_LENGTH_SET                          0x0000f000
-      #define DMA15_TI_BURST_LENGTH_CLR                          0xffff0fff
-      #define DMA15_TI_BURST_LENGTH_MSB                          15
-      #define DMA15_TI_BURST_LENGTH_LSB                          12
-      #define DMA15_TI_SRC_IGNORE_BITS                           11:11
-      #define DMA15_TI_SRC_IGNORE_SET                            0x00000800
-      #define DMA15_TI_SRC_IGNORE_CLR                            0xfffff7ff
-      #define DMA15_TI_SRC_IGNORE_MSB                            11
-      #define DMA15_TI_SRC_IGNORE_LSB                            11
-      #define DMA15_TI_SRC_DREQ_BITS                             10:10
-      #define DMA15_TI_SRC_DREQ_SET                              0x00000400
-      #define DMA15_TI_SRC_DREQ_CLR                              0xfffffbff
-      #define DMA15_TI_SRC_DREQ_MSB                              10
-      #define DMA15_TI_SRC_DREQ_LSB                              10
-      #define DMA15_TI_SRC_WIDTH_BITS                            9:9
-      #define DMA15_TI_SRC_WIDTH_SET                             0x00000200
-      #define DMA15_TI_SRC_WIDTH_CLR                             0xfffffdff
-      #define DMA15_TI_SRC_WIDTH_MSB                             9
-      #define DMA15_TI_SRC_WIDTH_LSB                             9
-      #define DMA15_TI_SRC_INC_BITS                              8:8
-      #define DMA15_TI_SRC_INC_SET                               0x00000100
-      #define DMA15_TI_SRC_INC_CLR                               0xfffffeff
-      #define DMA15_TI_SRC_INC_MSB                               8
-      #define DMA15_TI_SRC_INC_LSB                               8
-      #define DMA15_TI_DEST_IGNORE_BITS                          7:7
-      #define DMA15_TI_DEST_IGNORE_SET                           0x00000080
-      #define DMA15_TI_DEST_IGNORE_CLR                           0xffffff7f
-      #define DMA15_TI_DEST_IGNORE_MSB                           7
-      #define DMA15_TI_DEST_IGNORE_LSB                           7
-      #define DMA15_TI_DEST_DREQ_BITS                            6:6
-      #define DMA15_TI_DEST_DREQ_SET                             0x00000040
-      #define DMA15_TI_DEST_DREQ_CLR                             0xffffffbf
-      #define DMA15_TI_DEST_DREQ_MSB                             6
-      #define DMA15_TI_DEST_DREQ_LSB                             6
-      #define DMA15_TI_DEST_WIDTH_BITS                           5:5
-      #define DMA15_TI_DEST_WIDTH_SET                            0x00000020
-      #define DMA15_TI_DEST_WIDTH_CLR                            0xffffffdf
-      #define DMA15_TI_DEST_WIDTH_MSB                            5
-      #define DMA15_TI_DEST_WIDTH_LSB                            5
-      #define DMA15_TI_DEST_INC_BITS                             4:4
-      #define DMA15_TI_DEST_INC_SET                              0x00000010
-      #define DMA15_TI_DEST_INC_CLR                              0xffffffef
-      #define DMA15_TI_DEST_INC_MSB                              4
-      #define DMA15_TI_DEST_INC_LSB                              4
-      #define DMA15_TI_WAIT_RESP_BITS                            3:3
-      #define DMA15_TI_WAIT_RESP_SET                             0x00000008
-      #define DMA15_TI_WAIT_RESP_CLR                             0xfffffff7
-      #define DMA15_TI_WAIT_RESP_MSB                             3
-      #define DMA15_TI_WAIT_RESP_LSB                             3
-      #define DMA15_TI_TDMODE_BITS                               1:1
-      #define DMA15_TI_TDMODE_SET                                0x00000002
-      #define DMA15_TI_TDMODE_CLR                                0xfffffffd
-      #define DMA15_TI_TDMODE_MSB                                1
-      #define DMA15_TI_TDMODE_LSB                                1
-      #define DMA15_TI_INTEN_BITS                                0:0
-      #define DMA15_TI_INTEN_SET                                 0x00000001
-      #define DMA15_TI_INTEN_CLR                                 0xfffffffe
-      #define DMA15_TI_INTEN_MSB                                 0
-      #define DMA15_TI_INTEN_LSB                                 0
-#define DMA15_SOURCE_AD                                          HW_REGISTER_RO( 0x7ee0500c ) 
-   #define DMA15_SOURCE_AD_MASK                                  0xffffffff
-   #define DMA15_SOURCE_AD_WIDTH                                 32
-      #define DMA15_SOURCE_AD_S_ADDR_BITS                        31:0
-      #define DMA15_SOURCE_AD_S_ADDR_SET                         0xffffffff
-      #define DMA15_SOURCE_AD_S_ADDR_CLR                         0x00000000
-      #define DMA15_SOURCE_AD_S_ADDR_MSB                         31
-      #define DMA15_SOURCE_AD_S_ADDR_LSB                         0
-#define DMA15_DEST_AD                                            HW_REGISTER_RO( 0x7ee05010 ) 
-   #define DMA15_DEST_AD_MASK                                    0xffffffff
-   #define DMA15_DEST_AD_WIDTH                                   32
-      #define DMA15_DEST_AD_D_ADDR_BITS                          31:0
-      #define DMA15_DEST_AD_D_ADDR_SET                           0xffffffff
-      #define DMA15_DEST_AD_D_ADDR_CLR                           0x00000000
-      #define DMA15_DEST_AD_D_ADDR_MSB                           31
-      #define DMA15_DEST_AD_D_ADDR_LSB                           0
-#define DMA15_TXFR_LEN                                           HW_REGISTER_RO( 0x7ee05014 ) 
-   #define DMA15_TXFR_LEN_MASK                                   0x3fffffff
-   #define DMA15_TXFR_LEN_WIDTH                                  30
-      #define DMA15_TXFR_LEN_YLENGTH_BITS                        29:16
-      #define DMA15_TXFR_LEN_YLENGTH_SET                         0x3fff0000
-      #define DMA15_TXFR_LEN_YLENGTH_CLR                         0xc000ffff
-      #define DMA15_TXFR_LEN_YLENGTH_MSB                         29
-      #define DMA15_TXFR_LEN_YLENGTH_LSB                         16
-      #define DMA15_TXFR_LEN_XLENGTH_BITS                        15:0
-      #define DMA15_TXFR_LEN_XLENGTH_SET                         0x0000ffff
-      #define DMA15_TXFR_LEN_XLENGTH_CLR                         0xffff0000
-      #define DMA15_TXFR_LEN_XLENGTH_MSB                         15
-      #define DMA15_TXFR_LEN_XLENGTH_LSB                         0
-#define DMA15_STRIDE                                             HW_REGISTER_RO( 0x7ee05018 ) 
-   #define DMA15_STRIDE_MASK                                     0xffffffff
-   #define DMA15_STRIDE_WIDTH                                    32
-      #define DMA15_STRIDE_D_STRIDE_BITS                         31:16
-      #define DMA15_STRIDE_D_STRIDE_SET                          0xffff0000
-      #define DMA15_STRIDE_D_STRIDE_CLR                          0x0000ffff
-      #define DMA15_STRIDE_D_STRIDE_MSB                          31
-      #define DMA15_STRIDE_D_STRIDE_LSB                          16
-      #define DMA15_STRIDE_S_STRIDE_BITS                         15:0
-      #define DMA15_STRIDE_S_STRIDE_SET                          0x0000ffff
-      #define DMA15_STRIDE_S_STRIDE_CLR                          0xffff0000
-      #define DMA15_STRIDE_S_STRIDE_MSB                          15
-      #define DMA15_STRIDE_S_STRIDE_LSB                          0
-#define DMA15_NEXTCONBK                                          HW_REGISTER_RO( 0x7ee0501c ) 
-   #define DMA15_NEXTCONBK_MASK                                  0xffffffe0
-   #define DMA15_NEXTCONBK_WIDTH                                 32
-      #define DMA15_NEXTCONBK_ADDR_BITS                          31:5
-      #define DMA15_NEXTCONBK_ADDR_SET                           0xffffffe0
-      #define DMA15_NEXTCONBK_ADDR_CLR                           0x0000001f
-      #define DMA15_NEXTCONBK_ADDR_MSB                           31
-      #define DMA15_NEXTCONBK_ADDR_LSB                           5
-#define DMA15_DEBUG                                              HW_REGISTER_RW( 0x7ee05020 ) 
-   #define DMA15_DEBUG_MASK                                      0x1ffffff7
-   #define DMA15_DEBUG_WIDTH                                     29
-   #define DMA15_DEBUG_RESET                                     0000000000
-      #define DMA15_DEBUG_LITE_BITS                              28:28
-      #define DMA15_DEBUG_LITE_SET                               0x10000000
-      #define DMA15_DEBUG_LITE_CLR                               0xefffffff
-      #define DMA15_DEBUG_LITE_MSB                               28
-      #define DMA15_DEBUG_LITE_LSB                               28
-      #define DMA15_DEBUG_VERSION_BITS                           27:25
-      #define DMA15_DEBUG_VERSION_SET                            0x0e000000
-      #define DMA15_DEBUG_VERSION_CLR                            0xf1ffffff
-      #define DMA15_DEBUG_VERSION_MSB                            27
-      #define DMA15_DEBUG_VERSION_LSB                            25
-      #define DMA15_DEBUG_DMA_STATE_BITS                         24:16
-      #define DMA15_DEBUG_DMA_STATE_SET                          0x01ff0000
-      #define DMA15_DEBUG_DMA_STATE_CLR                          0xfe00ffff
-      #define DMA15_DEBUG_DMA_STATE_MSB                          24
-      #define DMA15_DEBUG_DMA_STATE_LSB                          16
-      #define DMA15_DEBUG_DMA_ID_BITS                            15:8
-      #define DMA15_DEBUG_DMA_ID_SET                             0x0000ff00
-      #define DMA15_DEBUG_DMA_ID_CLR                             0xffff00ff
-      #define DMA15_DEBUG_DMA_ID_MSB                             15
-      #define DMA15_DEBUG_DMA_ID_LSB                             8
-      #define DMA15_DEBUG_OUTSTANDING_WRITES_BITS                7:4
-      #define DMA15_DEBUG_OUTSTANDING_WRITES_SET                 0x000000f0
-      #define DMA15_DEBUG_OUTSTANDING_WRITES_CLR                 0xffffff0f
-      #define DMA15_DEBUG_OUTSTANDING_WRITES_MSB                 7
-      #define DMA15_DEBUG_OUTSTANDING_WRITES_LSB                 4
-      #define DMA15_DEBUG_READ_ERROR_BITS                        2:2
-      #define DMA15_DEBUG_READ_ERROR_SET                         0x00000004
-      #define DMA15_DEBUG_READ_ERROR_CLR                         0xfffffffb
-      #define DMA15_DEBUG_READ_ERROR_MSB                         2
-      #define DMA15_DEBUG_READ_ERROR_LSB                         2
-      #define DMA15_DEBUG_FIFO_ERROR_BITS                        1:1
-      #define DMA15_DEBUG_FIFO_ERROR_SET                         0x00000002
-      #define DMA15_DEBUG_FIFO_ERROR_CLR                         0xfffffffd
-      #define DMA15_DEBUG_FIFO_ERROR_MSB                         1
-      #define DMA15_DEBUG_FIFO_ERROR_LSB                         1
-      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_BITS           0:0
-      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_SET            0x00000001
-      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_CLR            0xfffffffe
-      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_MSB            0
-      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_LSB            0
diff --git a/bcm2708_chip/axi_dma2.h b/bcm2708_chip/axi_dma2.h
deleted file mode 100644 (file)
index 81b4ed9..0000000
+++ /dev/null
@@ -1,257 +0,0 @@
-// This file was generated by the create_regs script
-#define DMA2_BASE                                                0x7e007200
-#define DMA2_CS                                                  HW_REGISTER_RW( 0x7e007200 ) 
-   #define DMA2_CS_MASK                                          0xf0ff017f
-   #define DMA2_CS_WIDTH                                         32
-   #define DMA2_CS_RESET                                         0000000000
-      #define DMA2_CS_RESET_BITS                                 31:31
-      #define DMA2_CS_RESET_SET                                  0x80000000
-      #define DMA2_CS_RESET_CLR                                  0x7fffffff
-      #define DMA2_CS_RESET_MSB                                  31
-      #define DMA2_CS_RESET_LSB                                  31
-      #define DMA2_CS_ABORT_BITS                                 30:30
-      #define DMA2_CS_ABORT_SET                                  0x40000000
-      #define DMA2_CS_ABORT_CLR                                  0xbfffffff
-      #define DMA2_CS_ABORT_MSB                                  30
-      #define DMA2_CS_ABORT_LSB                                  30
-      #define DMA2_CS_DISDEBUG_BITS                              29:29
-      #define DMA2_CS_DISDEBUG_SET                               0x20000000
-      #define DMA2_CS_DISDEBUG_CLR                               0xdfffffff
-      #define DMA2_CS_DISDEBUG_MSB                               29
-      #define DMA2_CS_DISDEBUG_LSB                               29
-      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
-      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
-      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
-      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
-      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
-      #define DMA2_CS_PANIC_PRIORITY_BITS                        23:20
-      #define DMA2_CS_PANIC_PRIORITY_SET                         0x00f00000
-      #define DMA2_CS_PANIC_PRIORITY_CLR                         0xff0fffff
-      #define DMA2_CS_PANIC_PRIORITY_MSB                         23
-      #define DMA2_CS_PANIC_PRIORITY_LSB                         20
-      #define DMA2_CS_PRIORITY_BITS                              19:16
-      #define DMA2_CS_PRIORITY_SET                               0x000f0000
-      #define DMA2_CS_PRIORITY_CLR                               0xfff0ffff
-      #define DMA2_CS_PRIORITY_MSB                               19
-      #define DMA2_CS_PRIORITY_LSB                               16
-      #define DMA2_CS_ERROR_BITS                                 8:8
-      #define DMA2_CS_ERROR_SET                                  0x00000100
-      #define DMA2_CS_ERROR_CLR                                  0xfffffeff
-      #define DMA2_CS_ERROR_MSB                                  8
-      #define DMA2_CS_ERROR_LSB                                  8
-      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
-      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
-      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
-      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
-      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
-      #define DMA2_CS_DREQ_STOPS_DMA_BITS                        5:5
-      #define DMA2_CS_DREQ_STOPS_DMA_SET                         0x00000020
-      #define DMA2_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
-      #define DMA2_CS_DREQ_STOPS_DMA_MSB                         5
-      #define DMA2_CS_DREQ_STOPS_DMA_LSB                         5
-      #define DMA2_CS_PAUSED_BITS                                4:4
-      #define DMA2_CS_PAUSED_SET                                 0x00000010
-      #define DMA2_CS_PAUSED_CLR                                 0xffffffef
-      #define DMA2_CS_PAUSED_MSB                                 4
-      #define DMA2_CS_PAUSED_LSB                                 4
-      #define DMA2_CS_DREQ_BITS                                  3:3
-      #define DMA2_CS_DREQ_SET                                   0x00000008
-      #define DMA2_CS_DREQ_CLR                                   0xfffffff7
-      #define DMA2_CS_DREQ_MSB                                   3
-      #define DMA2_CS_DREQ_LSB                                   3
-      #define DMA2_CS_INT_BITS                                   2:2
-      #define DMA2_CS_INT_SET                                    0x00000004
-      #define DMA2_CS_INT_CLR                                    0xfffffffb
-      #define DMA2_CS_INT_MSB                                    2
-      #define DMA2_CS_INT_LSB                                    2
-      #define DMA2_CS_END_BITS                                   1:1
-      #define DMA2_CS_END_SET                                    0x00000002
-      #define DMA2_CS_END_CLR                                    0xfffffffd
-      #define DMA2_CS_END_MSB                                    1
-      #define DMA2_CS_END_LSB                                    1
-      #define DMA2_CS_ACTIVE_BITS                                0:0
-      #define DMA2_CS_ACTIVE_SET                                 0x00000001
-      #define DMA2_CS_ACTIVE_CLR                                 0xfffffffe
-      #define DMA2_CS_ACTIVE_MSB                                 0
-      #define DMA2_CS_ACTIVE_LSB                                 0
-#define DMA2_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007204 ) 
-   #define DMA2_CONBLK_AD_MASK                                   0xffffffe0
-   #define DMA2_CONBLK_AD_WIDTH                                  32
-   #define DMA2_CONBLK_AD_RESET                                  0000000000
-      #define DMA2_CONBLK_AD_SCB_ADDR_BITS                       31:5
-      #define DMA2_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
-      #define DMA2_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
-      #define DMA2_CONBLK_AD_SCB_ADDR_MSB                        31
-      #define DMA2_CONBLK_AD_SCB_ADDR_LSB                        5
-#define DMA2_TI                                                  HW_REGISTER_RO( 0x7e007208 ) 
-   #define DMA2_TI_MASK                                          0x07fffffb
-   #define DMA2_TI_WIDTH                                         27
-      #define DMA2_TI_NO_WIDE_BURSTS_BITS                        26:26
-      #define DMA2_TI_NO_WIDE_BURSTS_SET                         0x04000000
-      #define DMA2_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
-      #define DMA2_TI_NO_WIDE_BURSTS_MSB                         26
-      #define DMA2_TI_NO_WIDE_BURSTS_LSB                         26
-      #define DMA2_TI_WAITS_BITS                                 25:21
-      #define DMA2_TI_WAITS_SET                                  0x03e00000
-      #define DMA2_TI_WAITS_CLR                                  0xfc1fffff
-      #define DMA2_TI_WAITS_MSB                                  25
-      #define DMA2_TI_WAITS_LSB                                  21
-      #define DMA2_TI_PERMAP_BITS                                20:16
-      #define DMA2_TI_PERMAP_SET                                 0x001f0000
-      #define DMA2_TI_PERMAP_CLR                                 0xffe0ffff
-      #define DMA2_TI_PERMAP_MSB                                 20
-      #define DMA2_TI_PERMAP_LSB                                 16
-      #define DMA2_TI_BURST_LENGTH_BITS                          15:12
-      #define DMA2_TI_BURST_LENGTH_SET                           0x0000f000
-      #define DMA2_TI_BURST_LENGTH_CLR                           0xffff0fff
-      #define DMA2_TI_BURST_LENGTH_MSB                           15
-      #define DMA2_TI_BURST_LENGTH_LSB                           12
-      #define DMA2_TI_SRC_IGNORE_BITS                            11:11
-      #define DMA2_TI_SRC_IGNORE_SET                             0x00000800
-      #define DMA2_TI_SRC_IGNORE_CLR                             0xfffff7ff
-      #define DMA2_TI_SRC_IGNORE_MSB                             11
-      #define DMA2_TI_SRC_IGNORE_LSB                             11
-      #define DMA2_TI_SRC_DREQ_BITS                              10:10
-      #define DMA2_TI_SRC_DREQ_SET                               0x00000400
-      #define DMA2_TI_SRC_DREQ_CLR                               0xfffffbff
-      #define DMA2_TI_SRC_DREQ_MSB                               10
-      #define DMA2_TI_SRC_DREQ_LSB                               10
-      #define DMA2_TI_SRC_WIDTH_BITS                             9:9
-      #define DMA2_TI_SRC_WIDTH_SET                              0x00000200
-      #define DMA2_TI_SRC_WIDTH_CLR                              0xfffffdff
-      #define DMA2_TI_SRC_WIDTH_MSB                              9
-      #define DMA2_TI_SRC_WIDTH_LSB                              9
-      #define DMA2_TI_SRC_INC_BITS                               8:8
-      #define DMA2_TI_SRC_INC_SET                                0x00000100
-      #define DMA2_TI_SRC_INC_CLR                                0xfffffeff
-      #define DMA2_TI_SRC_INC_MSB                                8
-      #define DMA2_TI_SRC_INC_LSB                                8
-      #define DMA2_TI_DEST_IGNORE_BITS                           7:7
-      #define DMA2_TI_DEST_IGNORE_SET                            0x00000080
-      #define DMA2_TI_DEST_IGNORE_CLR                            0xffffff7f
-      #define DMA2_TI_DEST_IGNORE_MSB                            7
-      #define DMA2_TI_DEST_IGNORE_LSB                            7
-      #define DMA2_TI_DEST_DREQ_BITS                             6:6
-      #define DMA2_TI_DEST_DREQ_SET                              0x00000040
-      #define DMA2_TI_DEST_DREQ_CLR                              0xffffffbf
-      #define DMA2_TI_DEST_DREQ_MSB                              6
-      #define DMA2_TI_DEST_DREQ_LSB                              6
-      #define DMA2_TI_DEST_WIDTH_BITS                            5:5
-      #define DMA2_TI_DEST_WIDTH_SET                             0x00000020
-      #define DMA2_TI_DEST_WIDTH_CLR                             0xffffffdf
-      #define DMA2_TI_DEST_WIDTH_MSB                             5
-      #define DMA2_TI_DEST_WIDTH_LSB                             5
-      #define DMA2_TI_DEST_INC_BITS                              4:4
-      #define DMA2_TI_DEST_INC_SET                               0x00000010
-      #define DMA2_TI_DEST_INC_CLR                               0xffffffef
-      #define DMA2_TI_DEST_INC_MSB                               4
-      #define DMA2_TI_DEST_INC_LSB                               4
-      #define DMA2_TI_WAIT_RESP_BITS                             3:3
-      #define DMA2_TI_WAIT_RESP_SET                              0x00000008
-      #define DMA2_TI_WAIT_RESP_CLR                              0xfffffff7
-      #define DMA2_TI_WAIT_RESP_MSB                              3
-      #define DMA2_TI_WAIT_RESP_LSB                              3
-      #define DMA2_TI_TDMODE_BITS                                1:1
-      #define DMA2_TI_TDMODE_SET                                 0x00000002
-      #define DMA2_TI_TDMODE_CLR                                 0xfffffffd
-      #define DMA2_TI_TDMODE_MSB                                 1
-      #define DMA2_TI_TDMODE_LSB                                 1
-      #define DMA2_TI_INTEN_BITS                                 0:0
-      #define DMA2_TI_INTEN_SET                                  0x00000001
-      #define DMA2_TI_INTEN_CLR                                  0xfffffffe
-      #define DMA2_TI_INTEN_MSB                                  0
-      #define DMA2_TI_INTEN_LSB                                  0
-#define DMA2_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00720c ) 
-   #define DMA2_SOURCE_AD_MASK                                   0xffffffff
-   #define DMA2_SOURCE_AD_WIDTH                                  32
-      #define DMA2_SOURCE_AD_S_ADDR_BITS                         31:0
-      #define DMA2_SOURCE_AD_S_ADDR_SET                          0xffffffff
-      #define DMA2_SOURCE_AD_S_ADDR_CLR                          0x00000000
-      #define DMA2_SOURCE_AD_S_ADDR_MSB                          31
-      #define DMA2_SOURCE_AD_S_ADDR_LSB                          0
-#define DMA2_DEST_AD                                             HW_REGISTER_RO( 0x7e007210 ) 
-   #define DMA2_DEST_AD_MASK                                     0xffffffff
-   #define DMA2_DEST_AD_WIDTH                                    32
-      #define DMA2_DEST_AD_D_ADDR_BITS                           31:0
-      #define DMA2_DEST_AD_D_ADDR_SET                            0xffffffff
-      #define DMA2_DEST_AD_D_ADDR_CLR                            0x00000000
-      #define DMA2_DEST_AD_D_ADDR_MSB                            31
-      #define DMA2_DEST_AD_D_ADDR_LSB                            0
-#define DMA2_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007214 ) 
-   #define DMA2_TXFR_LEN_MASK                                    0x3fffffff
-   #define DMA2_TXFR_LEN_WIDTH                                   30
-      #define DMA2_TXFR_LEN_YLENGTH_BITS                         29:16
-      #define DMA2_TXFR_LEN_YLENGTH_SET                          0x3fff0000
-      #define DMA2_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
-      #define DMA2_TXFR_LEN_YLENGTH_MSB                          29
-      #define DMA2_TXFR_LEN_YLENGTH_LSB                          16
-      #define DMA2_TXFR_LEN_XLENGTH_BITS                         15:0
-      #define DMA2_TXFR_LEN_XLENGTH_SET                          0x0000ffff
-      #define DMA2_TXFR_LEN_XLENGTH_CLR                          0xffff0000
-      #define DMA2_TXFR_LEN_XLENGTH_MSB                          15
-      #define DMA2_TXFR_LEN_XLENGTH_LSB                          0
-#define DMA2_STRIDE                                              HW_REGISTER_RO( 0x7e007218 ) 
-   #define DMA2_STRIDE_MASK                                      0xffffffff
-   #define DMA2_STRIDE_WIDTH                                     32
-      #define DMA2_STRIDE_D_STRIDE_BITS                          31:16
-      #define DMA2_STRIDE_D_STRIDE_SET                           0xffff0000
-      #define DMA2_STRIDE_D_STRIDE_CLR                           0x0000ffff
-      #define DMA2_STRIDE_D_STRIDE_MSB                           31
-      #define DMA2_STRIDE_D_STRIDE_LSB                           16
-      #define DMA2_STRIDE_S_STRIDE_BITS                          15:0
-      #define DMA2_STRIDE_S_STRIDE_SET                           0x0000ffff
-      #define DMA2_STRIDE_S_STRIDE_CLR                           0xffff0000
-      #define DMA2_STRIDE_S_STRIDE_MSB                           15
-      #define DMA2_STRIDE_S_STRIDE_LSB                           0
-#define DMA2_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00721c ) 
-   #define DMA2_NEXTCONBK_MASK                                   0xffffffe0
-   #define DMA2_NEXTCONBK_WIDTH                                  32
-      #define DMA2_NEXTCONBK_ADDR_BITS                           31:5
-      #define DMA2_NEXTCONBK_ADDR_SET                            0xffffffe0
-      #define DMA2_NEXTCONBK_ADDR_CLR                            0x0000001f
-      #define DMA2_NEXTCONBK_ADDR_MSB                            31
-      #define DMA2_NEXTCONBK_ADDR_LSB                            5
-#define DMA2_DEBUG                                               HW_REGISTER_RW( 0x7e007220 ) 
-   #define DMA2_DEBUG_MASK                                       0x1ffffff7
-   #define DMA2_DEBUG_WIDTH                                      29
-   #define DMA2_DEBUG_RESET                                      0000000000
-      #define DMA2_DEBUG_LITE_BITS                               28:28
-      #define DMA2_DEBUG_LITE_SET                                0x10000000
-      #define DMA2_DEBUG_LITE_CLR                                0xefffffff
-      #define DMA2_DEBUG_LITE_MSB                                28
-      #define DMA2_DEBUG_LITE_LSB                                28
-      #define DMA2_DEBUG_VERSION_BITS                            27:25
-      #define DMA2_DEBUG_VERSION_SET                             0x0e000000
-      #define DMA2_DEBUG_VERSION_CLR                             0xf1ffffff
-      #define DMA2_DEBUG_VERSION_MSB                             27
-      #define DMA2_DEBUG_VERSION_LSB                             25
-      #define DMA2_DEBUG_DMA_STATE_BITS                          24:16
-      #define DMA2_DEBUG_DMA_STATE_SET                           0x01ff0000
-      #define DMA2_DEBUG_DMA_STATE_CLR                           0xfe00ffff
-      #define DMA2_DEBUG_DMA_STATE_MSB                           24
-      #define DMA2_DEBUG_DMA_STATE_LSB                           16
-      #define DMA2_DEBUG_DMA_ID_BITS                             15:8
-      #define DMA2_DEBUG_DMA_ID_SET                              0x0000ff00
-      #define DMA2_DEBUG_DMA_ID_CLR                              0xffff00ff
-      #define DMA2_DEBUG_DMA_ID_MSB                              15
-      #define DMA2_DEBUG_DMA_ID_LSB                              8
-      #define DMA2_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
-      #define DMA2_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
-      #define DMA2_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
-      #define DMA2_DEBUG_OUTSTANDING_WRITES_MSB                  7
-      #define DMA2_DEBUG_OUTSTANDING_WRITES_LSB                  4
-      #define DMA2_DEBUG_READ_ERROR_BITS                         2:2
-      #define DMA2_DEBUG_READ_ERROR_SET                          0x00000004
-      #define DMA2_DEBUG_READ_ERROR_CLR                          0xfffffffb
-      #define DMA2_DEBUG_READ_ERROR_MSB                          2
-      #define DMA2_DEBUG_READ_ERROR_LSB                          2
-      #define DMA2_DEBUG_FIFO_ERROR_BITS                         1:1
-      #define DMA2_DEBUG_FIFO_ERROR_SET                          0x00000002
-      #define DMA2_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
-      #define DMA2_DEBUG_FIFO_ERROR_MSB                          1
-      #define DMA2_DEBUG_FIFO_ERROR_LSB                          1
-      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
-      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
-      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
-      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
-      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma3.h b/bcm2708_chip/axi_dma3.h
deleted file mode 100644 (file)
index a2208c0..0000000
+++ /dev/null
@@ -1,257 +0,0 @@
-// This file was generated by the create_regs script
-#define DMA3_BASE                                                0x7e007300
-#define DMA3_CS                                                  HW_REGISTER_RW( 0x7e007300 ) 
-   #define DMA3_CS_MASK                                          0xf0ff017f
-   #define DMA3_CS_WIDTH                                         32
-   #define DMA3_CS_RESET                                         0000000000
-      #define DMA3_CS_RESET_BITS                                 31:31
-      #define DMA3_CS_RESET_SET                                  0x80000000
-      #define DMA3_CS_RESET_CLR                                  0x7fffffff
-      #define DMA3_CS_RESET_MSB                                  31
-      #define DMA3_CS_RESET_LSB                                  31
-      #define DMA3_CS_ABORT_BITS                                 30:30
-      #define DMA3_CS_ABORT_SET                                  0x40000000
-      #define DMA3_CS_ABORT_CLR                                  0xbfffffff
-      #define DMA3_CS_ABORT_MSB                                  30
-      #define DMA3_CS_ABORT_LSB                                  30
-      #define DMA3_CS_DISDEBUG_BITS                              29:29
-      #define DMA3_CS_DISDEBUG_SET                               0x20000000
-      #define DMA3_CS_DISDEBUG_CLR                               0xdfffffff
-      #define DMA3_CS_DISDEBUG_MSB                               29
-      #define DMA3_CS_DISDEBUG_LSB                               29
-      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
-      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
-      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
-      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
-      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
-      #define DMA3_CS_PANIC_PRIORITY_BITS                        23:20
-      #define DMA3_CS_PANIC_PRIORITY_SET                         0x00f00000
-      #define DMA3_CS_PANIC_PRIORITY_CLR                         0xff0fffff
-      #define DMA3_CS_PANIC_PRIORITY_MSB                         23
-      #define DMA3_CS_PANIC_PRIORITY_LSB                         20
-      #define DMA3_CS_PRIORITY_BITS                              19:16
-      #define DMA3_CS_PRIORITY_SET                               0x000f0000
-      #define DMA3_CS_PRIORITY_CLR                               0xfff0ffff
-      #define DMA3_CS_PRIORITY_MSB                               19
-      #define DMA3_CS_PRIORITY_LSB                               16
-      #define DMA3_CS_ERROR_BITS                                 8:8
-      #define DMA3_CS_ERROR_SET                                  0x00000100
-      #define DMA3_CS_ERROR_CLR                                  0xfffffeff
-      #define DMA3_CS_ERROR_MSB                                  8
-      #define DMA3_CS_ERROR_LSB                                  8
-      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
-      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
-      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
-      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
-      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
-      #define DMA3_CS_DREQ_STOPS_DMA_BITS                        5:5
-      #define DMA3_CS_DREQ_STOPS_DMA_SET                         0x00000020
-      #define DMA3_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
-      #define DMA3_CS_DREQ_STOPS_DMA_MSB                         5
-      #define DMA3_CS_DREQ_STOPS_DMA_LSB                         5
-      #define DMA3_CS_PAUSED_BITS                                4:4
-      #define DMA3_CS_PAUSED_SET                                 0x00000010
-      #define DMA3_CS_PAUSED_CLR                                 0xffffffef
-      #define DMA3_CS_PAUSED_MSB                                 4
-      #define DMA3_CS_PAUSED_LSB                                 4
-      #define DMA3_CS_DREQ_BITS                                  3:3
-      #define DMA3_CS_DREQ_SET                                   0x00000008
-      #define DMA3_CS_DREQ_CLR                                   0xfffffff7
-      #define DMA3_CS_DREQ_MSB                                   3
-      #define DMA3_CS_DREQ_LSB                                   3
-      #define DMA3_CS_INT_BITS                                   2:2
-      #define DMA3_CS_INT_SET                                    0x00000004
-      #define DMA3_CS_INT_CLR                                    0xfffffffb
-      #define DMA3_CS_INT_MSB                                    2
-      #define DMA3_CS_INT_LSB                                    2
-      #define DMA3_CS_END_BITS                                   1:1
-      #define DMA3_CS_END_SET                                    0x00000002
-      #define DMA3_CS_END_CLR                                    0xfffffffd
-      #define DMA3_CS_END_MSB                                    1
-      #define DMA3_CS_END_LSB                                    1
-      #define DMA3_CS_ACTIVE_BITS                                0:0
-      #define DMA3_CS_ACTIVE_SET                                 0x00000001
-      #define DMA3_CS_ACTIVE_CLR                                 0xfffffffe
-      #define DMA3_CS_ACTIVE_MSB                                 0
-      #define DMA3_CS_ACTIVE_LSB                                 0
-#define DMA3_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007304 ) 
-   #define DMA3_CONBLK_AD_MASK                                   0xffffffe0
-   #define DMA3_CONBLK_AD_WIDTH                                  32
-   #define DMA3_CONBLK_AD_RESET                                  0000000000
-      #define DMA3_CONBLK_AD_SCB_ADDR_BITS                       31:5
-      #define DMA3_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
-      #define DMA3_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
-      #define DMA3_CONBLK_AD_SCB_ADDR_MSB                        31
-      #define DMA3_CONBLK_AD_SCB_ADDR_LSB                        5
-#define DMA3_TI                                                  HW_REGISTER_RO( 0x7e007308 ) 
-   #define DMA3_TI_MASK                                          0x07fffffb
-   #define DMA3_TI_WIDTH                                         27
-      #define DMA3_TI_NO_WIDE_BURSTS_BITS                        26:26
-      #define DMA3_TI_NO_WIDE_BURSTS_SET                         0x04000000
-      #define DMA3_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
-      #define DMA3_TI_NO_WIDE_BURSTS_MSB                         26
-      #define DMA3_TI_NO_WIDE_BURSTS_LSB                         26
-      #define DMA3_TI_WAITS_BITS                                 25:21
-      #define DMA3_TI_WAITS_SET                                  0x03e00000
-      #define DMA3_TI_WAITS_CLR                                  0xfc1fffff
-      #define DMA3_TI_WAITS_MSB                                  25
-      #define DMA3_TI_WAITS_LSB                                  21
-      #define DMA3_TI_PERMAP_BITS                                20:16
-      #define DMA3_TI_PERMAP_SET                                 0x001f0000
-      #define DMA3_TI_PERMAP_CLR                                 0xffe0ffff
-      #define DMA3_TI_PERMAP_MSB                                 20
-      #define DMA3_TI_PERMAP_LSB                                 16
-      #define DMA3_TI_BURST_LENGTH_BITS                          15:12
-      #define DMA3_TI_BURST_LENGTH_SET                           0x0000f000
-      #define DMA3_TI_BURST_LENGTH_CLR                           0xffff0fff
-      #define DMA3_TI_BURST_LENGTH_MSB                           15
-      #define DMA3_TI_BURST_LENGTH_LSB                           12
-      #define DMA3_TI_SRC_IGNORE_BITS                            11:11
-      #define DMA3_TI_SRC_IGNORE_SET                             0x00000800
-      #define DMA3_TI_SRC_IGNORE_CLR                             0xfffff7ff
-      #define DMA3_TI_SRC_IGNORE_MSB                             11
-      #define DMA3_TI_SRC_IGNORE_LSB                             11
-      #define DMA3_TI_SRC_DREQ_BITS                              10:10
-      #define DMA3_TI_SRC_DREQ_SET                               0x00000400
-      #define DMA3_TI_SRC_DREQ_CLR                               0xfffffbff
-      #define DMA3_TI_SRC_DREQ_MSB                               10
-      #define DMA3_TI_SRC_DREQ_LSB                               10
-      #define DMA3_TI_SRC_WIDTH_BITS                             9:9
-      #define DMA3_TI_SRC_WIDTH_SET                              0x00000200
-      #define DMA3_TI_SRC_WIDTH_CLR                              0xfffffdff
-      #define DMA3_TI_SRC_WIDTH_MSB                              9
-      #define DMA3_TI_SRC_WIDTH_LSB                              9
-      #define DMA3_TI_SRC_INC_BITS                               8:8
-      #define DMA3_TI_SRC_INC_SET                                0x00000100
-      #define DMA3_TI_SRC_INC_CLR                                0xfffffeff
-      #define DMA3_TI_SRC_INC_MSB                                8
-      #define DMA3_TI_SRC_INC_LSB                                8
-      #define DMA3_TI_DEST_IGNORE_BITS                           7:7
-      #define DMA3_TI_DEST_IGNORE_SET                            0x00000080
-      #define DMA3_TI_DEST_IGNORE_CLR                            0xffffff7f
-      #define DMA3_TI_DEST_IGNORE_MSB                            7
-      #define DMA3_TI_DEST_IGNORE_LSB                            7
-      #define DMA3_TI_DEST_DREQ_BITS                             6:6
-      #define DMA3_TI_DEST_DREQ_SET                              0x00000040
-      #define DMA3_TI_DEST_DREQ_CLR                              0xffffffbf
-      #define DMA3_TI_DEST_DREQ_MSB                              6
-      #define DMA3_TI_DEST_DREQ_LSB                              6
-      #define DMA3_TI_DEST_WIDTH_BITS                            5:5
-      #define DMA3_TI_DEST_WIDTH_SET                             0x00000020
-      #define DMA3_TI_DEST_WIDTH_CLR                             0xffffffdf
-      #define DMA3_TI_DEST_WIDTH_MSB                             5
-      #define DMA3_TI_DEST_WIDTH_LSB                             5
-      #define DMA3_TI_DEST_INC_BITS                              4:4
-      #define DMA3_TI_DEST_INC_SET                               0x00000010
-      #define DMA3_TI_DEST_INC_CLR                               0xffffffef
-      #define DMA3_TI_DEST_INC_MSB                               4
-      #define DMA3_TI_DEST_INC_LSB                               4
-      #define DMA3_TI_WAIT_RESP_BITS                             3:3
-      #define DMA3_TI_WAIT_RESP_SET                              0x00000008
-      #define DMA3_TI_WAIT_RESP_CLR                              0xfffffff7
-      #define DMA3_TI_WAIT_RESP_MSB                              3
-      #define DMA3_TI_WAIT_RESP_LSB                              3
-      #define DMA3_TI_TDMODE_BITS                                1:1
-      #define DMA3_TI_TDMODE_SET                                 0x00000002
-      #define DMA3_TI_TDMODE_CLR                                 0xfffffffd
-      #define DMA3_TI_TDMODE_MSB                                 1
-      #define DMA3_TI_TDMODE_LSB                                 1
-      #define DMA3_TI_INTEN_BITS                                 0:0
-      #define DMA3_TI_INTEN_SET                                  0x00000001
-      #define DMA3_TI_INTEN_CLR                                  0xfffffffe
-      #define DMA3_TI_INTEN_MSB                                  0
-      #define DMA3_TI_INTEN_LSB                                  0
-#define DMA3_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00730c ) 
-   #define DMA3_SOURCE_AD_MASK                                   0xffffffff
-   #define DMA3_SOURCE_AD_WIDTH                                  32
-      #define DMA3_SOURCE_AD_S_ADDR_BITS                         31:0
-      #define DMA3_SOURCE_AD_S_ADDR_SET                          0xffffffff
-      #define DMA3_SOURCE_AD_S_ADDR_CLR                          0x00000000
-      #define DMA3_SOURCE_AD_S_ADDR_MSB                          31
-      #define DMA3_SOURCE_AD_S_ADDR_LSB                          0
-#define DMA3_DEST_AD                                             HW_REGISTER_RO( 0x7e007310 ) 
-   #define DMA3_DEST_AD_MASK                                     0xffffffff
-   #define DMA3_DEST_AD_WIDTH                                    32
-      #define DMA3_DEST_AD_D_ADDR_BITS                           31:0
-      #define DMA3_DEST_AD_D_ADDR_SET                            0xffffffff
-      #define DMA3_DEST_AD_D_ADDR_CLR                            0x00000000
-      #define DMA3_DEST_AD_D_ADDR_MSB                            31
-      #define DMA3_DEST_AD_D_ADDR_LSB                            0
-#define DMA3_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007314 ) 
-   #define DMA3_TXFR_LEN_MASK                                    0x3fffffff
-   #define DMA3_TXFR_LEN_WIDTH                                   30
-      #define DMA3_TXFR_LEN_YLENGTH_BITS                         29:16
-      #define DMA3_TXFR_LEN_YLENGTH_SET                          0x3fff0000
-      #define DMA3_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
-      #define DMA3_TXFR_LEN_YLENGTH_MSB                          29
-      #define DMA3_TXFR_LEN_YLENGTH_LSB                          16
-      #define DMA3_TXFR_LEN_XLENGTH_BITS                         15:0
-      #define DMA3_TXFR_LEN_XLENGTH_SET                          0x0000ffff
-      #define DMA3_TXFR_LEN_XLENGTH_CLR                          0xffff0000
-      #define DMA3_TXFR_LEN_XLENGTH_MSB                          15
-      #define DMA3_TXFR_LEN_XLENGTH_LSB                          0
-#define DMA3_STRIDE                                              HW_REGISTER_RO( 0x7e007318 ) 
-   #define DMA3_STRIDE_MASK                                      0xffffffff
-   #define DMA3_STRIDE_WIDTH                                     32
-      #define DMA3_STRIDE_D_STRIDE_BITS                          31:16
-      #define DMA3_STRIDE_D_STRIDE_SET                           0xffff0000
-      #define DMA3_STRIDE_D_STRIDE_CLR                           0x0000ffff
-      #define DMA3_STRIDE_D_STRIDE_MSB                           31
-      #define DMA3_STRIDE_D_STRIDE_LSB                           16
-      #define DMA3_STRIDE_S_STRIDE_BITS                          15:0
-      #define DMA3_STRIDE_S_STRIDE_SET                           0x0000ffff
-      #define DMA3_STRIDE_S_STRIDE_CLR                           0xffff0000
-      #define DMA3_STRIDE_S_STRIDE_MSB                           15
-      #define DMA3_STRIDE_S_STRIDE_LSB                           0
-#define DMA3_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00731c ) 
-   #define DMA3_NEXTCONBK_MASK                                   0xffffffe0
-   #define DMA3_NEXTCONBK_WIDTH                                  32
-      #define DMA3_NEXTCONBK_ADDR_BITS                           31:5
-      #define DMA3_NEXTCONBK_ADDR_SET                            0xffffffe0
-      #define DMA3_NEXTCONBK_ADDR_CLR                            0x0000001f
-      #define DMA3_NEXTCONBK_ADDR_MSB                            31
-      #define DMA3_NEXTCONBK_ADDR_LSB                            5
-#define DMA3_DEBUG                                               HW_REGISTER_RW( 0x7e007320 ) 
-   #define DMA3_DEBUG_MASK                                       0x1ffffff7
-   #define DMA3_DEBUG_WIDTH                                      29
-   #define DMA3_DEBUG_RESET                                      0000000000
-      #define DMA3_DEBUG_LITE_BITS                               28:28
-      #define DMA3_DEBUG_LITE_SET                                0x10000000
-      #define DMA3_DEBUG_LITE_CLR                                0xefffffff
-      #define DMA3_DEBUG_LITE_MSB                                28
-      #define DMA3_DEBUG_LITE_LSB                                28
-      #define DMA3_DEBUG_VERSION_BITS                            27:25
-      #define DMA3_DEBUG_VERSION_SET                             0x0e000000
-      #define DMA3_DEBUG_VERSION_CLR                             0xf1ffffff
-      #define DMA3_DEBUG_VERSION_MSB                             27
-      #define DMA3_DEBUG_VERSION_LSB                             25
-      #define DMA3_DEBUG_DMA_STATE_BITS                          24:16
-      #define DMA3_DEBUG_DMA_STATE_SET                           0x01ff0000
-      #define DMA3_DEBUG_DMA_STATE_CLR                           0xfe00ffff
-      #define DMA3_DEBUG_DMA_STATE_MSB                           24
-      #define DMA3_DEBUG_DMA_STATE_LSB                           16
-      #define DMA3_DEBUG_DMA_ID_BITS                             15:8
-      #define DMA3_DEBUG_DMA_ID_SET                              0x0000ff00
-      #define DMA3_DEBUG_DMA_ID_CLR                              0xffff00ff
-      #define DMA3_DEBUG_DMA_ID_MSB                              15
-      #define DMA3_DEBUG_DMA_ID_LSB                              8
-      #define DMA3_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
-      #define DMA3_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
-      #define DMA3_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
-      #define DMA3_DEBUG_OUTSTANDING_WRITES_MSB                  7
-      #define DMA3_DEBUG_OUTSTANDING_WRITES_LSB                  4
-      #define DMA3_DEBUG_READ_ERROR_BITS                         2:2
-      #define DMA3_DEBUG_READ_ERROR_SET                          0x00000004
-      #define DMA3_DEBUG_READ_ERROR_CLR                          0xfffffffb
-      #define DMA3_DEBUG_READ_ERROR_MSB                          2
-      #define DMA3_DEBUG_READ_ERROR_LSB                          2
-      #define DMA3_DEBUG_FIFO_ERROR_BITS                         1:1
-      #define DMA3_DEBUG_FIFO_ERROR_SET                          0x00000002
-      #define DMA3_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
-      #define DMA3_DEBUG_FIFO_ERROR_MSB                          1
-      #define DMA3_DEBUG_FIFO_ERROR_LSB                          1
-      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
-      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
-      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
-      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
-      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma4.h b/bcm2708_chip/axi_dma4.h
deleted file mode 100644 (file)
index 1cefda5..0000000
+++ /dev/null
@@ -1,257 +0,0 @@
-// This file was generated by the create_regs script
-#define DMA4_BASE                                                0x7e007400
-#define DMA4_CS                                                  HW_REGISTER_RW( 0x7e007400 ) 
-   #define DMA4_CS_MASK                                          0xf0ff017f
-   #define DMA4_CS_WIDTH                                         32
-   #define DMA4_CS_RESET                                         0000000000
-      #define DMA4_CS_RESET_BITS                                 31:31
-      #define DMA4_CS_RESET_SET                                  0x80000000
-      #define DMA4_CS_RESET_CLR                                  0x7fffffff
-      #define DMA4_CS_RESET_MSB                                  31
-      #define DMA4_CS_RESET_LSB                                  31
-      #define DMA4_CS_ABORT_BITS                                 30:30
-      #define DMA4_CS_ABORT_SET                                  0x40000000
-      #define DMA4_CS_ABORT_CLR                                  0xbfffffff
-      #define DMA4_CS_ABORT_MSB                                  30
-      #define DMA4_CS_ABORT_LSB                                  30
-      #define DMA4_CS_DISDEBUG_BITS                              29:29
-      #define DMA4_CS_DISDEBUG_SET                               0x20000000
-      #define DMA4_CS_DISDEBUG_CLR                               0xdfffffff
-      #define DMA4_CS_DISDEBUG_MSB                               29
-      #define DMA4_CS_DISDEBUG_LSB                               29
-      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
-      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
-      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
-      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
-      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
-      #define DMA4_CS_PANIC_PRIORITY_BITS                        23:20
-      #define DMA4_CS_PANIC_PRIORITY_SET                         0x00f00000
-      #define DMA4_CS_PANIC_PRIORITY_CLR                         0xff0fffff
-      #define DMA4_CS_PANIC_PRIORITY_MSB                         23
-      #define DMA4_CS_PANIC_PRIORITY_LSB                         20
-      #define DMA4_CS_PRIORITY_BITS                              19:16
-      #define DMA4_CS_PRIORITY_SET                               0x000f0000
-      #define DMA4_CS_PRIORITY_CLR                               0xfff0ffff
-      #define DMA4_CS_PRIORITY_MSB                               19
-      #define DMA4_CS_PRIORITY_LSB                               16
-      #define DMA4_CS_ERROR_BITS                                 8:8
-      #define DMA4_CS_ERROR_SET                                  0x00000100
-      #define DMA4_CS_ERROR_CLR                                  0xfffffeff
-      #define DMA4_CS_ERROR_MSB                                  8
-      #define DMA4_CS_ERROR_LSB                                  8
-      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
-      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
-      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
-      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
-      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
-      #define DMA4_CS_DREQ_STOPS_DMA_BITS                        5:5
-      #define DMA4_CS_DREQ_STOPS_DMA_SET                         0x00000020
-      #define DMA4_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
-      #define DMA4_CS_DREQ_STOPS_DMA_MSB                         5
-      #define DMA4_CS_DREQ_STOPS_DMA_LSB                         5
-      #define DMA4_CS_PAUSED_BITS                                4:4
-      #define DMA4_CS_PAUSED_SET                                 0x00000010
-      #define DMA4_CS_PAUSED_CLR                                 0xffffffef
-      #define DMA4_CS_PAUSED_MSB                                 4
-      #define DMA4_CS_PAUSED_LSB                                 4
-      #define DMA4_CS_DREQ_BITS                                  3:3
-      #define DMA4_CS_DREQ_SET                                   0x00000008
-      #define DMA4_CS_DREQ_CLR                                   0xfffffff7
-      #define DMA4_CS_DREQ_MSB                                   3
-      #define DMA4_CS_DREQ_LSB                                   3
-      #define DMA4_CS_INT_BITS                                   2:2
-      #define DMA4_CS_INT_SET                                    0x00000004
-      #define DMA4_CS_INT_CLR                                    0xfffffffb
-      #define DMA4_CS_INT_MSB                                    2
-      #define DMA4_CS_INT_LSB                                    2
-      #define DMA4_CS_END_BITS                                   1:1
-      #define DMA4_CS_END_SET                                    0x00000002
-      #define DMA4_CS_END_CLR                                    0xfffffffd
-      #define DMA4_CS_END_MSB                                    1
-      #define DMA4_CS_END_LSB                                    1
-      #define DMA4_CS_ACTIVE_BITS                                0:0
-      #define DMA4_CS_ACTIVE_SET                                 0x00000001
-      #define DMA4_CS_ACTIVE_CLR                                 0xfffffffe
-      #define DMA4_CS_ACTIVE_MSB                                 0
-      #define DMA4_CS_ACTIVE_LSB                                 0
-#define DMA4_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007404 ) 
-   #define DMA4_CONBLK_AD_MASK                                   0xffffffe0
-   #define DMA4_CONBLK_AD_WIDTH                                  32
-   #define DMA4_CONBLK_AD_RESET                                  0000000000
-      #define DMA4_CONBLK_AD_SCB_ADDR_BITS                       31:5
-      #define DMA4_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
-      #define DMA4_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
-      #define DMA4_CONBLK_AD_SCB_ADDR_MSB                        31
-      #define DMA4_CONBLK_AD_SCB_ADDR_LSB                        5
-#define DMA4_TI                                                  HW_REGISTER_RO( 0x7e007408 ) 
-   #define DMA4_TI_MASK                                          0x07fffffb
-   #define DMA4_TI_WIDTH                                         27
-      #define DMA4_TI_NO_WIDE_BURSTS_BITS                        26:26
-      #define DMA4_TI_NO_WIDE_BURSTS_SET                         0x04000000
-      #define DMA4_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
-      #define DMA4_TI_NO_WIDE_BURSTS_MSB                         26
-      #define DMA4_TI_NO_WIDE_BURSTS_LSB                         26
-      #define DMA4_TI_WAITS_BITS                                 25:21
-      #define DMA4_TI_WAITS_SET                                  0x03e00000
-      #define DMA4_TI_WAITS_CLR                                  0xfc1fffff
-      #define DMA4_TI_WAITS_MSB                                  25
-      #define DMA4_TI_WAITS_LSB                                  21
-      #define DMA4_TI_PERMAP_BITS                                20:16
-      #define DMA4_TI_PERMAP_SET                                 0x001f0000
-      #define DMA4_TI_PERMAP_CLR                                 0xffe0ffff
-      #define DMA4_TI_PERMAP_MSB                                 20
-      #define DMA4_TI_PERMAP_LSB                                 16
-      #define DMA4_TI_BURST_LENGTH_BITS                          15:12
-      #define DMA4_TI_BURST_LENGTH_SET                           0x0000f000
-      #define DMA4_TI_BURST_LENGTH_CLR                           0xffff0fff
-      #define DMA4_TI_BURST_LENGTH_MSB                           15
-      #define DMA4_TI_BURST_LENGTH_LSB                           12
-      #define DMA4_TI_SRC_IGNORE_BITS                            11:11
-      #define DMA4_TI_SRC_IGNORE_SET                             0x00000800
-      #define DMA4_TI_SRC_IGNORE_CLR                             0xfffff7ff
-      #define DMA4_TI_SRC_IGNORE_MSB                             11
-      #define DMA4_TI_SRC_IGNORE_LSB                             11
-      #define DMA4_TI_SRC_DREQ_BITS                              10:10
-      #define DMA4_TI_SRC_DREQ_SET                               0x00000400
-      #define DMA4_TI_SRC_DREQ_CLR                               0xfffffbff
-      #define DMA4_TI_SRC_DREQ_MSB                               10
-      #define DMA4_TI_SRC_DREQ_LSB                               10
-      #define DMA4_TI_SRC_WIDTH_BITS                             9:9
-      #define DMA4_TI_SRC_WIDTH_SET                              0x00000200
-      #define DMA4_TI_SRC_WIDTH_CLR                              0xfffffdff
-      #define DMA4_TI_SRC_WIDTH_MSB                              9
-      #define DMA4_TI_SRC_WIDTH_LSB                              9
-      #define DMA4_TI_SRC_INC_BITS                               8:8
-      #define DMA4_TI_SRC_INC_SET                                0x00000100
-      #define DMA4_TI_SRC_INC_CLR                                0xfffffeff
-      #define DMA4_TI_SRC_INC_MSB                                8
-      #define DMA4_TI_SRC_INC_LSB                                8
-      #define DMA4_TI_DEST_IGNORE_BITS                           7:7
-      #define DMA4_TI_DEST_IGNORE_SET                            0x00000080
-      #define DMA4_TI_DEST_IGNORE_CLR                            0xffffff7f
-      #define DMA4_TI_DEST_IGNORE_MSB                            7
-      #define DMA4_TI_DEST_IGNORE_LSB                            7
-      #define DMA4_TI_DEST_DREQ_BITS                             6:6
-      #define DMA4_TI_DEST_DREQ_SET                              0x00000040
-      #define DMA4_TI_DEST_DREQ_CLR                              0xffffffbf
-      #define DMA4_TI_DEST_DREQ_MSB                              6
-      #define DMA4_TI_DEST_DREQ_LSB                              6
-      #define DMA4_TI_DEST_WIDTH_BITS                            5:5
-      #define DMA4_TI_DEST_WIDTH_SET                             0x00000020
-      #define DMA4_TI_DEST_WIDTH_CLR                             0xffffffdf
-      #define DMA4_TI_DEST_WIDTH_MSB                             5
-      #define DMA4_TI_DEST_WIDTH_LSB                             5
-      #define DMA4_TI_DEST_INC_BITS                              4:4
-      #define DMA4_TI_DEST_INC_SET                               0x00000010
-      #define DMA4_TI_DEST_INC_CLR                               0xffffffef
-      #define DMA4_TI_DEST_INC_MSB                               4
-      #define DMA4_TI_DEST_INC_LSB                               4
-      #define DMA4_TI_WAIT_RESP_BITS                             3:3
-      #define DMA4_TI_WAIT_RESP_SET                              0x00000008
-      #define DMA4_TI_WAIT_RESP_CLR                              0xfffffff7
-      #define DMA4_TI_WAIT_RESP_MSB                              3
-      #define DMA4_TI_WAIT_RESP_LSB                              3
-      #define DMA4_TI_TDMODE_BITS                                1:1
-      #define DMA4_TI_TDMODE_SET                                 0x00000002
-      #define DMA4_TI_TDMODE_CLR                                 0xfffffffd
-      #define DMA4_TI_TDMODE_MSB                                 1
-      #define DMA4_TI_TDMODE_LSB                                 1
-      #define DMA4_TI_INTEN_BITS                                 0:0
-      #define DMA4_TI_INTEN_SET                                  0x00000001
-      #define DMA4_TI_INTEN_CLR                                  0xfffffffe
-      #define DMA4_TI_INTEN_MSB                                  0
-      #define DMA4_TI_INTEN_LSB                                  0
-#define DMA4_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00740c ) 
-   #define DMA4_SOURCE_AD_MASK                                   0xffffffff
-   #define DMA4_SOURCE_AD_WIDTH                                  32
-      #define DMA4_SOURCE_AD_S_ADDR_BITS                         31:0
-      #define DMA4_SOURCE_AD_S_ADDR_SET                          0xffffffff
-      #define DMA4_SOURCE_AD_S_ADDR_CLR                          0x00000000
-      #define DMA4_SOURCE_AD_S_ADDR_MSB                          31
-      #define DMA4_SOURCE_AD_S_ADDR_LSB                          0
-#define DMA4_DEST_AD                                             HW_REGISTER_RO( 0x7e007410 ) 
-   #define DMA4_DEST_AD_MASK                                     0xffffffff
-   #define DMA4_DEST_AD_WIDTH                                    32
-      #define DMA4_DEST_AD_D_ADDR_BITS                           31:0
-      #define DMA4_DEST_AD_D_ADDR_SET                            0xffffffff
-      #define DMA4_DEST_AD_D_ADDR_CLR                            0x00000000
-      #define DMA4_DEST_AD_D_ADDR_MSB                            31
-      #define DMA4_DEST_AD_D_ADDR_LSB                            0
-#define DMA4_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007414 ) 
-   #define DMA4_TXFR_LEN_MASK                                    0x3fffffff
-   #define DMA4_TXFR_LEN_WIDTH                                   30
-      #define DMA4_TXFR_LEN_YLENGTH_BITS                         29:16
-      #define DMA4_TXFR_LEN_YLENGTH_SET                          0x3fff0000
-      #define DMA4_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
-      #define DMA4_TXFR_LEN_YLENGTH_MSB                          29
-      #define DMA4_TXFR_LEN_YLENGTH_LSB                          16
-      #define DMA4_TXFR_LEN_XLENGTH_BITS                         15:0
-      #define DMA4_TXFR_LEN_XLENGTH_SET                          0x0000ffff
-      #define DMA4_TXFR_LEN_XLENGTH_CLR                          0xffff0000
-      #define DMA4_TXFR_LEN_XLENGTH_MSB                          15
-      #define DMA4_TXFR_LEN_XLENGTH_LSB                          0
-#define DMA4_STRIDE                                              HW_REGISTER_RO( 0x7e007418 ) 
-   #define DMA4_STRIDE_MASK                                      0xffffffff
-   #define DMA4_STRIDE_WIDTH                                     32
-      #define DMA4_STRIDE_D_STRIDE_BITS                          31:16
-      #define DMA4_STRIDE_D_STRIDE_SET                           0xffff0000
-      #define DMA4_STRIDE_D_STRIDE_CLR                           0x0000ffff
-      #define DMA4_STRIDE_D_STRIDE_MSB                           31
-      #define DMA4_STRIDE_D_STRIDE_LSB                           16
-      #define DMA4_STRIDE_S_STRIDE_BITS                          15:0
-      #define DMA4_STRIDE_S_STRIDE_SET                           0x0000ffff
-      #define DMA4_STRIDE_S_STRIDE_CLR                           0xffff0000
-      #define DMA4_STRIDE_S_STRIDE_MSB                           15
-      #define DMA4_STRIDE_S_STRIDE_LSB                           0
-#define DMA4_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00741c ) 
-   #define DMA4_NEXTCONBK_MASK                                   0xffffffe0
-   #define DMA4_NEXTCONBK_WIDTH                                  32
-      #define DMA4_NEXTCONBK_ADDR_BITS                           31:5
-      #define DMA4_NEXTCONBK_ADDR_SET                            0xffffffe0
-      #define DMA4_NEXTCONBK_ADDR_CLR                            0x0000001f
-      #define DMA4_NEXTCONBK_ADDR_MSB                            31
-      #define DMA4_NEXTCONBK_ADDR_LSB                            5
-#define DMA4_DEBUG                                               HW_REGISTER_RW( 0x7e007420 ) 
-   #define DMA4_DEBUG_MASK                                       0x1ffffff7
-   #define DMA4_DEBUG_WIDTH                                      29
-   #define DMA4_DEBUG_RESET                                      0000000000
-      #define DMA4_DEBUG_LITE_BITS                               28:28
-      #define DMA4_DEBUG_LITE_SET                                0x10000000
-      #define DMA4_DEBUG_LITE_CLR                                0xefffffff
-      #define DMA4_DEBUG_LITE_MSB                                28
-      #define DMA4_DEBUG_LITE_LSB                                28
-      #define DMA4_DEBUG_VERSION_BITS                            27:25
-      #define DMA4_DEBUG_VERSION_SET                             0x0e000000
-      #define DMA4_DEBUG_VERSION_CLR                             0xf1ffffff
-      #define DMA4_DEBUG_VERSION_MSB                             27
-      #define DMA4_DEBUG_VERSION_LSB                             25
-      #define DMA4_DEBUG_DMA_STATE_BITS                          24:16
-      #define DMA4_DEBUG_DMA_STATE_SET                           0x01ff0000
-      #define DMA4_DEBUG_DMA_STATE_CLR                           0xfe00ffff
-      #define DMA4_DEBUG_DMA_STATE_MSB                           24
-      #define DMA4_DEBUG_DMA_STATE_LSB                           16
-      #define DMA4_DEBUG_DMA_ID_BITS                             15:8
-      #define DMA4_DEBUG_DMA_ID_SET                              0x0000ff00
-      #define DMA4_DEBUG_DMA_ID_CLR                              0xffff00ff
-      #define DMA4_DEBUG_DMA_ID_MSB                              15
-      #define DMA4_DEBUG_DMA_ID_LSB                              8
-      #define DMA4_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
-      #define DMA4_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
-      #define DMA4_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
-      #define DMA4_DEBUG_OUTSTANDING_WRITES_MSB                  7
-      #define DMA4_DEBUG_OUTSTANDING_WRITES_LSB                  4
-      #define DMA4_DEBUG_READ_ERROR_BITS                         2:2
-      #define DMA4_DEBUG_READ_ERROR_SET                          0x00000004
-      #define DMA4_DEBUG_READ_ERROR_CLR                          0xfffffffb
-      #define DMA4_DEBUG_READ_ERROR_MSB                          2
-      #define DMA4_DEBUG_READ_ERROR_LSB                          2
-      #define DMA4_DEBUG_FIFO_ERROR_BITS                         1:1
-      #define DMA4_DEBUG_FIFO_ERROR_SET                          0x00000002
-      #define DMA4_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
-      #define DMA4_DEBUG_FIFO_ERROR_MSB                          1
-      #define DMA4_DEBUG_FIFO_ERROR_LSB                          1
-      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
-      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
-      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
-      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
-      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma5.h b/bcm2708_chip/axi_dma5.h
deleted file mode 100644 (file)
index a8f6a1f..0000000
+++ /dev/null
@@ -1,257 +0,0 @@
-// This file was generated by the create_regs script
-#define DMA5_BASE                                                0x7e007500
-#define DMA5_CS                                                  HW_REGISTER_RW( 0x7e007500 ) 
-   #define DMA5_CS_MASK                                          0xf0ff017f
-   #define DMA5_CS_WIDTH                                         32
-   #define DMA5_CS_RESET                                         0000000000
-      #define DMA5_CS_RESET_BITS                                 31:31
-      #define DMA5_CS_RESET_SET                                  0x80000000
-      #define DMA5_CS_RESET_CLR                                  0x7fffffff
-      #define DMA5_CS_RESET_MSB                                  31
-      #define DMA5_CS_RESET_LSB                                  31
-      #define DMA5_CS_ABORT_BITS                                 30:30
-      #define DMA5_CS_ABORT_SET                                  0x40000000
-      #define DMA5_CS_ABORT_CLR                                  0xbfffffff
-      #define DMA5_CS_ABORT_MSB                                  30
-      #define DMA5_CS_ABORT_LSB                                  30
-      #define DMA5_CS_DISDEBUG_BITS                              29:29
-      #define DMA5_CS_DISDEBUG_SET                               0x20000000
-      #define DMA5_CS_DISDEBUG_CLR                               0xdfffffff
-      #define DMA5_CS_DISDEBUG_MSB                               29
-      #define DMA5_CS_DISDEBUG_LSB                               29
-      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
-      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
-      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
-      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
-      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
-      #define DMA5_CS_PANIC_PRIORITY_BITS                        23:20
-      #define DMA5_CS_PANIC_PRIORITY_SET                         0x00f00000
-      #define DMA5_CS_PANIC_PRIORITY_CLR                         0xff0fffff
-      #define DMA5_CS_PANIC_PRIORITY_MSB                         23
-      #define DMA5_CS_PANIC_PRIORITY_LSB                         20
-      #define DMA5_CS_PRIORITY_BITS                              19:16
-      #define DMA5_CS_PRIORITY_SET                               0x000f0000
-      #define DMA5_CS_PRIORITY_CLR                               0xfff0ffff
-      #define DMA5_CS_PRIORITY_MSB                               19
-      #define DMA5_CS_PRIORITY_LSB                               16
-      #define DMA5_CS_ERROR_BITS                                 8:8
-      #define DMA5_CS_ERROR_SET                                  0x00000100
-      #define DMA5_CS_ERROR_CLR                                  0xfffffeff
-      #define DMA5_CS_ERROR_MSB                                  8
-      #define DMA5_CS_ERROR_LSB                                  8
-      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
-      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
-      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
-      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
-      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
-      #define DMA5_CS_DREQ_STOPS_DMA_BITS                        5:5
-      #define DMA5_CS_DREQ_STOPS_DMA_SET                         0x00000020
-      #define DMA5_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
-      #define DMA5_CS_DREQ_STOPS_DMA_MSB                         5
-      #define DMA5_CS_DREQ_STOPS_DMA_LSB                         5
-      #define DMA5_CS_PAUSED_BITS                                4:4
-      #define DMA5_CS_PAUSED_SET                                 0x00000010
-      #define DMA5_CS_PAUSED_CLR                                 0xffffffef
-      #define DMA5_CS_PAUSED_MSB                                 4
-      #define DMA5_CS_PAUSED_LSB                                 4
-      #define DMA5_CS_DREQ_BITS                                  3:3
-      #define DMA5_CS_DREQ_SET                                   0x00000008
-      #define DMA5_CS_DREQ_CLR                                   0xfffffff7
-      #define DMA5_CS_DREQ_MSB                                   3
-      #define DMA5_CS_DREQ_LSB                                   3
-      #define DMA5_CS_INT_BITS                                   2:2
-      #define DMA5_CS_INT_SET                                    0x00000004
-      #define DMA5_CS_INT_CLR                                    0xfffffffb
-      #define DMA5_CS_INT_MSB                                    2
-      #define DMA5_CS_INT_LSB                                    2
-      #define DMA5_CS_END_BITS                                   1:1
-      #define DMA5_CS_END_SET                                    0x00000002
-      #define DMA5_CS_END_CLR                                    0xfffffffd
-      #define DMA5_CS_END_MSB                                    1
-      #define DMA5_CS_END_LSB                                    1
-      #define DMA5_CS_ACTIVE_BITS                                0:0
-      #define DMA5_CS_ACTIVE_SET                                 0x00000001
-      #define DMA5_CS_ACTIVE_CLR                                 0xfffffffe
-      #define DMA5_CS_ACTIVE_MSB                                 0
-      #define DMA5_CS_ACTIVE_LSB                                 0
-#define DMA5_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007504 ) 
-   #define DMA5_CONBLK_AD_MASK                                   0xffffffe0
-   #define DMA5_CONBLK_AD_WIDTH                                  32
-   #define DMA5_CONBLK_AD_RESET                                  0000000000
-      #define DMA5_CONBLK_AD_SCB_ADDR_BITS                       31:5
-      #define DMA5_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
-      #define DMA5_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
-      #define DMA5_CONBLK_AD_SCB_ADDR_MSB                        31
-      #define DMA5_CONBLK_AD_SCB_ADDR_LSB                        5
-#define DMA5_TI                                                  HW_REGISTER_RO( 0x7e007508 ) 
-   #define DMA5_TI_MASK                                          0x07fffffb
-   #define DMA5_TI_WIDTH                                         27
-      #define DMA5_TI_NO_WIDE_BURSTS_BITS                        26:26
-      #define DMA5_TI_NO_WIDE_BURSTS_SET                         0x04000000
-      #define DMA5_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
-      #define DMA5_TI_NO_WIDE_BURSTS_MSB                         26
-      #define DMA5_TI_NO_WIDE_BURSTS_LSB                         26
-      #define DMA5_TI_WAITS_BITS                                 25:21
-      #define DMA5_TI_WAITS_SET                                  0x03e00000
-      #define DMA5_TI_WAITS_CLR                                  0xfc1fffff
-      #define DMA5_TI_WAITS_MSB                                  25
-      #define DMA5_TI_WAITS_LSB                                  21
-      #define DMA5_TI_PERMAP_BITS                                20:16
-      #define DMA5_TI_PERMAP_SET                                 0x001f0000
-      #define DMA5_TI_PERMAP_CLR                                 0xffe0ffff
-      #define DMA5_TI_PERMAP_MSB                                 20
-      #define DMA5_TI_PERMAP_LSB                                 16
-      #define DMA5_TI_BURST_LENGTH_BITS                          15:12
-      #define DMA5_TI_BURST_LENGTH_SET                           0x0000f000
-      #define DMA5_TI_BURST_LENGTH_CLR                           0xffff0fff
-      #define DMA5_TI_BURST_LENGTH_MSB                           15
-      #define DMA5_TI_BURST_LENGTH_LSB                           12
-      #define DMA5_TI_SRC_IGNORE_BITS                            11:11
-      #define DMA5_TI_SRC_IGNORE_SET                             0x00000800
-      #define DMA5_TI_SRC_IGNORE_CLR                             0xfffff7ff
-      #define DMA5_TI_SRC_IGNORE_MSB                             11
-      #define DMA5_TI_SRC_IGNORE_LSB                             11
-      #define DMA5_TI_SRC_DREQ_BITS                              10:10
-      #define DMA5_TI_SRC_DREQ_SET                               0x00000400
-      #define DMA5_TI_SRC_DREQ_CLR                               0xfffffbff
-      #define DMA5_TI_SRC_DREQ_MSB                               10
-      #define DMA5_TI_SRC_DREQ_LSB                               10
-      #define DMA5_TI_SRC_WIDTH_BITS                             9:9
-      #define DMA5_TI_SRC_WIDTH_SET                              0x00000200
-      #define DMA5_TI_SRC_WIDTH_CLR                              0xfffffdff
-      #define DMA5_TI_SRC_WIDTH_MSB                              9
-      #define DMA5_TI_SRC_WIDTH_LSB                              9
-      #define DMA5_TI_SRC_INC_BITS                               8:8
-      #define DMA5_TI_SRC_INC_SET                                0x00000100
-      #define DMA5_TI_SRC_INC_CLR                                0xfffffeff
-      #define DMA5_TI_SRC_INC_MSB                                8
-      #define DMA5_TI_SRC_INC_LSB                                8
-      #define DMA5_TI_DEST_IGNORE_BITS                           7:7
-      #define DMA5_TI_DEST_IGNORE_SET                            0x00000080
-      #define DMA5_TI_DEST_IGNORE_CLR                            0xffffff7f
-      #define DMA5_TI_DEST_IGNORE_MSB                            7
-      #define DMA5_TI_DEST_IGNORE_LSB                            7
-      #define DMA5_TI_DEST_DREQ_BITS                             6:6
-      #define DMA5_TI_DEST_DREQ_SET                              0x00000040
-      #define DMA5_TI_DEST_DREQ_CLR                              0xffffffbf
-      #define DMA5_TI_DEST_DREQ_MSB                              6
-      #define DMA5_TI_DEST_DREQ_LSB                              6
-      #define DMA5_TI_DEST_WIDTH_BITS                            5:5
-      #define DMA5_TI_DEST_WIDTH_SET                             0x00000020
-      #define DMA5_TI_DEST_WIDTH_CLR                             0xffffffdf
-      #define DMA5_TI_DEST_WIDTH_MSB                             5
-      #define DMA5_TI_DEST_WIDTH_LSB                             5
-      #define DMA5_TI_DEST_INC_BITS                              4:4
-      #define DMA5_TI_DEST_INC_SET                               0x00000010
-      #define DMA5_TI_DEST_INC_CLR                               0xffffffef
-      #define DMA5_TI_DEST_INC_MSB                               4
-      #define DMA5_TI_DEST_INC_LSB                               4
-      #define DMA5_TI_WAIT_RESP_BITS                             3:3
-      #define DMA5_TI_WAIT_RESP_SET                              0x00000008
-      #define DMA5_TI_WAIT_RESP_CLR                              0xfffffff7
-      #define DMA5_TI_WAIT_RESP_MSB                              3
-      #define DMA5_TI_WAIT_RESP_LSB                              3
-      #define DMA5_TI_TDMODE_BITS                                1:1
-      #define DMA5_TI_TDMODE_SET                                 0x00000002
-      #define DMA5_TI_TDMODE_CLR                                 0xfffffffd
-      #define DMA5_TI_TDMODE_MSB                                 1
-      #define DMA5_TI_TDMODE_LSB                                 1
-      #define DMA5_TI_INTEN_BITS                                 0:0
-      #define DMA5_TI_INTEN_SET                                  0x00000001
-      #define DMA5_TI_INTEN_CLR                                  0xfffffffe
-      #define DMA5_TI_INTEN_MSB                                  0
-      #define DMA5_TI_INTEN_LSB                                  0
-#define DMA5_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00750c ) 
-   #define DMA5_SOURCE_AD_MASK                                   0xffffffff
-   #define DMA5_SOURCE_AD_WIDTH                                  32
-      #define DMA5_SOURCE_AD_S_ADDR_BITS                         31:0
-      #define DMA5_SOURCE_AD_S_ADDR_SET                          0xffffffff
-      #define DMA5_SOURCE_AD_S_ADDR_CLR                          0x00000000
-      #define DMA5_SOURCE_AD_S_ADDR_MSB                          31
-      #define DMA5_SOURCE_AD_S_ADDR_LSB                          0
-#define DMA5_DEST_AD                                             HW_REGISTER_RO( 0x7e007510 ) 
-   #define DMA5_DEST_AD_MASK                                     0xffffffff
-   #define DMA5_DEST_AD_WIDTH                                    32
-      #define DMA5_DEST_AD_D_ADDR_BITS                           31:0
-      #define DMA5_DEST_AD_D_ADDR_SET                            0xffffffff
-      #define DMA5_DEST_AD_D_ADDR_CLR                            0x00000000
-      #define DMA5_DEST_AD_D_ADDR_MSB                            31
-      #define DMA5_DEST_AD_D_ADDR_LSB                            0
-#define DMA5_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007514 ) 
-   #define DMA5_TXFR_LEN_MASK                                    0x3fffffff
-   #define DMA5_TXFR_LEN_WIDTH                                   30
-      #define DMA5_TXFR_LEN_YLENGTH_BITS                         29:16
-      #define DMA5_TXFR_LEN_YLENGTH_SET                          0x3fff0000
-      #define DMA5_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
-      #define DMA5_TXFR_LEN_YLENGTH_MSB                          29
-      #define DMA5_TXFR_LEN_YLENGTH_LSB                          16
-      #define DMA5_TXFR_LEN_XLENGTH_BITS                         15:0
-      #define DMA5_TXFR_LEN_XLENGTH_SET                          0x0000ffff
-      #define DMA5_TXFR_LEN_XLENGTH_CLR                          0xffff0000
-      #define DMA5_TXFR_LEN_XLENGTH_MSB                          15
-      #define DMA5_TXFR_LEN_XLENGTH_LSB                          0
-#define DMA5_STRIDE                                              HW_REGISTER_RO( 0x7e007518 ) 
-   #define DMA5_STRIDE_MASK                                      0xffffffff
-   #define DMA5_STRIDE_WIDTH                                     32
-      #define DMA5_STRIDE_D_STRIDE_BITS                          31:16
-      #define DMA5_STRIDE_D_STRIDE_SET                           0xffff0000
-      #define DMA5_STRIDE_D_STRIDE_CLR                           0x0000ffff
-      #define DMA5_STRIDE_D_STRIDE_MSB                           31
-      #define DMA5_STRIDE_D_STRIDE_LSB                           16
-      #define DMA5_STRIDE_S_STRIDE_BITS                          15:0
-      #define DMA5_STRIDE_S_STRIDE_SET                           0x0000ffff
-      #define DMA5_STRIDE_S_STRIDE_CLR                           0xffff0000
-      #define DMA5_STRIDE_S_STRIDE_MSB                           15
-      #define DMA5_STRIDE_S_STRIDE_LSB                           0
-#define DMA5_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00751c ) 
-   #define DMA5_NEXTCONBK_MASK                                   0xffffffe0
-   #define DMA5_NEXTCONBK_WIDTH                                  32
-      #define DMA5_NEXTCONBK_ADDR_BITS                           31:5
-      #define DMA5_NEXTCONBK_ADDR_SET                            0xffffffe0
-      #define DMA5_NEXTCONBK_ADDR_CLR                            0x0000001f
-      #define DMA5_NEXTCONBK_ADDR_MSB                            31
-      #define DMA5_NEXTCONBK_ADDR_LSB                            5
-#define DMA5_DEBUG                                               HW_REGISTER_RW( 0x7e007520 ) 
-   #define DMA5_DEBUG_MASK                                       0x1ffffff7
-   #define DMA5_DEBUG_WIDTH                                      29
-   #define DMA5_DEBUG_RESET                                      0000000000
-      #define DMA5_DEBUG_LITE_BITS                               28:28
-      #define DMA5_DEBUG_LITE_SET                                0x10000000
-      #define DMA5_DEBUG_LITE_CLR                                0xefffffff
-      #define DMA5_DEBUG_LITE_MSB                                28
-      #define DMA5_DEBUG_LITE_LSB                                28
-      #define DMA5_DEBUG_VERSION_BITS                            27:25
-      #define DMA5_DEBUG_VERSION_SET                             0x0e000000
-      #define DMA5_DEBUG_VERSION_CLR                             0xf1ffffff
-      #define DMA5_DEBUG_VERSION_MSB                             27
-      #define DMA5_DEBUG_VERSION_LSB                             25
-      #define DMA5_DEBUG_DMA_STATE_BITS                          24:16
-      #define DMA5_DEBUG_DMA_STATE_SET                           0x01ff0000
-      #define DMA5_DEBUG_DMA_STATE_CLR                           0xfe00ffff
-      #define DMA5_DEBUG_DMA_STATE_MSB                           24
-      #define DMA5_DEBUG_DMA_STATE_LSB                           16
-      #define DMA5_DEBUG_DMA_ID_BITS                             15:8
-      #define DMA5_DEBUG_DMA_ID_SET                              0x0000ff00
-      #define DMA5_DEBUG_DMA_ID_CLR                              0xffff00ff
-      #define DMA5_DEBUG_DMA_ID_MSB                              15
-      #define DMA5_DEBUG_DMA_ID_LSB                              8
-      #define DMA5_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
-      #define DMA5_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
-      #define DMA5_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
-      #define DMA5_DEBUG_OUTSTANDING_WRITES_MSB                  7
-      #define DMA5_DEBUG_OUTSTANDING_WRITES_LSB                  4
-      #define DMA5_DEBUG_READ_ERROR_BITS                         2:2
-      #define DMA5_DEBUG_READ_ERROR_SET                          0x00000004
-      #define DMA5_DEBUG_READ_ERROR_CLR                          0xfffffffb
-      #define DMA5_DEBUG_READ_ERROR_MSB                          2
-      #define DMA5_DEBUG_READ_ERROR_LSB                          2
-      #define DMA5_DEBUG_FIFO_ERROR_BITS                         1:1
-      #define DMA5_DEBUG_FIFO_ERROR_SET                          0x00000002
-      #define DMA5_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
-      #define DMA5_DEBUG_FIFO_ERROR_MSB                          1
-      #define DMA5_DEBUG_FIFO_ERROR_LSB                          1
-      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
-      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
-      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
-      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
-      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma6.h b/bcm2708_chip/axi_dma6.h
deleted file mode 100644 (file)
index 988f002..0000000
+++ /dev/null
@@ -1,257 +0,0 @@
-// This file was generated by the create_regs script
-#define DMA6_BASE                                                0x7e007600
-#define DMA6_CS                                                  HW_REGISTER_RW( 0x7e007600 ) 
-   #define DMA6_CS_MASK                                          0xf0ff017f
-   #define DMA6_CS_WIDTH                                         32
-   #define DMA6_CS_RESET                                         0000000000
-      #define DMA6_CS_RESET_BITS                                 31:31
-      #define DMA6_CS_RESET_SET                                  0x80000000
-      #define DMA6_CS_RESET_CLR                                  0x7fffffff
-      #define DMA6_CS_RESET_MSB                                  31
-      #define DMA6_CS_RESET_LSB                                  31
-      #define DMA6_CS_ABORT_BITS                                 30:30
-      #define DMA6_CS_ABORT_SET                                  0x40000000
-      #define DMA6_CS_ABORT_CLR                                  0xbfffffff
-      #define DMA6_CS_ABORT_MSB                                  30
-      #define DMA6_CS_ABORT_LSB                                  30
-      #define DMA6_CS_DISDEBUG_BITS                              29:29
-      #define DMA6_CS_DISDEBUG_SET                               0x20000000
-      #define DMA6_CS_DISDEBUG_CLR                               0xdfffffff
-      #define DMA6_CS_DISDEBUG_MSB                               29
-      #define DMA6_CS_DISDEBUG_LSB                               29
-      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
-      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
-      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
-      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
-      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
-      #define DMA6_CS_PANIC_PRIORITY_BITS                        23:20
-      #define DMA6_CS_PANIC_PRIORITY_SET                         0x00f00000
-      #define DMA6_CS_PANIC_PRIORITY_CLR                         0xff0fffff
-      #define DMA6_CS_PANIC_PRIORITY_MSB                         23
-      #define DMA6_CS_PANIC_PRIORITY_LSB                         20
-      #define DMA6_CS_PRIORITY_BITS                              19:16
-      #define DMA6_CS_PRIORITY_SET                               0x000f0000
-      #define DMA6_CS_PRIORITY_CLR                               0xfff0ffff
-      #define DMA6_CS_PRIORITY_MSB                               19
-      #define DMA6_CS_PRIORITY_LSB                               16
-      #define DMA6_CS_ERROR_BITS                                 8:8
-      #define DMA6_CS_ERROR_SET                                  0x00000100
-      #define DMA6_CS_ERROR_CLR                                  0xfffffeff
-      #define DMA6_CS_ERROR_MSB                                  8
-      #define DMA6_CS_ERROR_LSB                                  8
-      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
-      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
-      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
-      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
-      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
-      #define DMA6_CS_DREQ_STOPS_DMA_BITS                        5:5
-      #define DMA6_CS_DREQ_STOPS_DMA_SET                         0x00000020
-      #define DMA6_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
-      #define DMA6_CS_DREQ_STOPS_DMA_MSB                         5
-      #define DMA6_CS_DREQ_STOPS_DMA_LSB                         5
-      #define DMA6_CS_PAUSED_BITS                                4:4
-      #define DMA6_CS_PAUSED_SET                                 0x00000010
-      #define DMA6_CS_PAUSED_CLR                                 0xffffffef
-      #define DMA6_CS_PAUSED_MSB                                 4
-      #define DMA6_CS_PAUSED_LSB                                 4
-      #define DMA6_CS_DREQ_BITS                                  3:3
-      #define DMA6_CS_DREQ_SET                                   0x00000008
-      #define DMA6_CS_DREQ_CLR                                   0xfffffff7
-      #define DMA6_CS_DREQ_MSB                                   3
-      #define DMA6_CS_DREQ_LSB                                   3
-      #define DMA6_CS_INT_BITS                                   2:2
-      #define DMA6_CS_INT_SET                                    0x00000004
-      #define DMA6_CS_INT_CLR                                    0xfffffffb
-      #define DMA6_CS_INT_MSB                                    2
-      #define DMA6_CS_INT_LSB                                    2
-      #define DMA6_CS_END_BITS                                   1:1
-      #define DMA6_CS_END_SET                                    0x00000002
-      #define DMA6_CS_END_CLR                                    0xfffffffd
-      #define DMA6_CS_END_MSB                                    1
-      #define DMA6_CS_END_LSB                                    1
-      #define DMA6_CS_ACTIVE_BITS                                0:0
-      #define DMA6_CS_ACTIVE_SET                                 0x00000001
-      #define DMA6_CS_ACTIVE_CLR                                 0xfffffffe
-      #define DMA6_CS_ACTIVE_MSB                                 0
-      #define DMA6_CS_ACTIVE_LSB                                 0
-#define DMA6_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007604 ) 
-   #define DMA6_CONBLK_AD_MASK                                   0xffffffe0
-   #define DMA6_CONBLK_AD_WIDTH                                  32
-   #define DMA6_CONBLK_AD_RESET                                  0000000000
-      #define DMA6_CONBLK_AD_SCB_ADDR_BITS                       31:5
-      #define DMA6_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
-      #define DMA6_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
-      #define DMA6_CONBLK_AD_SCB_ADDR_MSB                        31
-      #define DMA6_CONBLK_AD_SCB_ADDR_LSB                        5
-#define DMA6_TI                                                  HW_REGISTER_RO( 0x7e007608 ) 
-   #define DMA6_TI_MASK                                          0x07fffffb
-   #define DMA6_TI_WIDTH                                         27
-      #define DMA6_TI_NO_WIDE_BURSTS_BITS                        26:26
-      #define DMA6_TI_NO_WIDE_BURSTS_SET                         0x04000000
-      #define DMA6_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
-      #define DMA6_TI_NO_WIDE_BURSTS_MSB                         26
-      #define DMA6_TI_NO_WIDE_BURSTS_LSB                         26
-      #define DMA6_TI_WAITS_BITS                                 25:21
-      #define DMA6_TI_WAITS_SET                                  0x03e00000
-      #define DMA6_TI_WAITS_CLR                                  0xfc1fffff
-      #define DMA6_TI_WAITS_MSB                                  25
-      #define DMA6_TI_WAITS_LSB                                  21
-      #define DMA6_TI_PERMAP_BITS                                20:16
-      #define DMA6_TI_PERMAP_SET                                 0x001f0000
-      #define DMA6_TI_PERMAP_CLR                                 0xffe0ffff
-      #define DMA6_TI_PERMAP_MSB                                 20
-      #define DMA6_TI_PERMAP_LSB                                 16
-      #define DMA6_TI_BURST_LENGTH_BITS                          15:12
-      #define DMA6_TI_BURST_LENGTH_SET                           0x0000f000
-      #define DMA6_TI_BURST_LENGTH_CLR                           0xffff0fff
-      #define DMA6_TI_BURST_LENGTH_MSB                           15
-      #define DMA6_TI_BURST_LENGTH_LSB                           12
-      #define DMA6_TI_SRC_IGNORE_BITS                            11:11
-      #define DMA6_TI_SRC_IGNORE_SET                             0x00000800
-      #define DMA6_TI_SRC_IGNORE_CLR                             0xfffff7ff
-      #define DMA6_TI_SRC_IGNORE_MSB                             11
-      #define DMA6_TI_SRC_IGNORE_LSB                             11
-      #define DMA6_TI_SRC_DREQ_BITS                              10:10
-      #define DMA6_TI_SRC_DREQ_SET                               0x00000400
-      #define DMA6_TI_SRC_DREQ_CLR                               0xfffffbff
-      #define DMA6_TI_SRC_DREQ_MSB                               10
-      #define DMA6_TI_SRC_DREQ_LSB                               10
-      #define DMA6_TI_SRC_WIDTH_BITS                             9:9
-      #define DMA6_TI_SRC_WIDTH_SET                              0x00000200
-      #define DMA6_TI_SRC_WIDTH_CLR                              0xfffffdff
-      #define DMA6_TI_SRC_WIDTH_MSB                              9
-      #define DMA6_TI_SRC_WIDTH_LSB                              9
-      #define DMA6_TI_SRC_INC_BITS                               8:8
-      #define DMA6_TI_SRC_INC_SET                                0x00000100
-      #define DMA6_TI_SRC_INC_CLR                                0xfffffeff
-      #define DMA6_TI_SRC_INC_MSB                                8
-      #define DMA6_TI_SRC_INC_LSB                                8
-      #define DMA6_TI_DEST_IGNORE_BITS                           7:7
-      #define DMA6_TI_DEST_IGNORE_SET                            0x00000080
-      #define DMA6_TI_DEST_IGNORE_CLR                            0xffffff7f
-      #define DMA6_TI_DEST_IGNORE_MSB                            7
-      #define DMA6_TI_DEST_IGNORE_LSB                            7
-      #define DMA6_TI_DEST_DREQ_BITS                             6:6
-      #define DMA6_TI_DEST_DREQ_SET                              0x00000040
-      #define DMA6_TI_DEST_DREQ_CLR                              0xffffffbf
-      #define DMA6_TI_DEST_DREQ_MSB                              6
-      #define DMA6_TI_DEST_DREQ_LSB                              6
-      #define DMA6_TI_DEST_WIDTH_BITS                            5:5
-      #define DMA6_TI_DEST_WIDTH_SET                             0x00000020
-      #define DMA6_TI_DEST_WIDTH_CLR                             0xffffffdf
-      #define DMA6_TI_DEST_WIDTH_MSB                             5
-      #define DMA6_TI_DEST_WIDTH_LSB                             5
-      #define DMA6_TI_DEST_INC_BITS                              4:4
-      #define DMA6_TI_DEST_INC_SET                               0x00000010
-      #define DMA6_TI_DEST_INC_CLR                               0xffffffef
-      #define DMA6_TI_DEST_INC_MSB                               4
-      #define DMA6_TI_DEST_INC_LSB                               4
-      #define DMA6_TI_WAIT_RESP_BITS                             3:3
-      #define DMA6_TI_WAIT_RESP_SET                              0x00000008
-      #define DMA6_TI_WAIT_RESP_CLR                              0xfffffff7
-      #define DMA6_TI_WAIT_RESP_MSB                              3
-      #define DMA6_TI_WAIT_RESP_LSB                              3
-      #define DMA6_TI_TDMODE_BITS                                1:1
-      #define DMA6_TI_TDMODE_SET                                 0x00000002
-      #define DMA6_TI_TDMODE_CLR                                 0xfffffffd
-      #define DMA6_TI_TDMODE_MSB                                 1
-      #define DMA6_TI_TDMODE_LSB                                 1
-      #define DMA6_TI_INTEN_BITS                                 0:0
-      #define DMA6_TI_INTEN_SET                                  0x00000001
-      #define DMA6_TI_INTEN_CLR                                  0xfffffffe
-      #define DMA6_TI_INTEN_MSB                                  0
-      #define DMA6_TI_INTEN_LSB                                  0
-#define DMA6_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00760c ) 
-   #define DMA6_SOURCE_AD_MASK                                   0xffffffff
-   #define DMA6_SOURCE_AD_WIDTH                                  32
-      #define DMA6_SOURCE_AD_S_ADDR_BITS                         31:0
-      #define DMA6_SOURCE_AD_S_ADDR_SET                          0xffffffff
-      #define DMA6_SOURCE_AD_S_ADDR_CLR                          0x00000000
-      #define DMA6_SOURCE_AD_S_ADDR_MSB                          31
-      #define DMA6_SOURCE_AD_S_ADDR_LSB                          0
-#define DMA6_DEST_AD                                             HW_REGISTER_RO( 0x7e007610 ) 
-   #define DMA6_DEST_AD_MASK                                     0xffffffff
-   #define DMA6_DEST_AD_WIDTH                                    32
-      #define DMA6_DEST_AD_D_ADDR_BITS                           31:0
-      #define DMA6_DEST_AD_D_ADDR_SET                            0xffffffff
-      #define DMA6_DEST_AD_D_ADDR_CLR                            0x00000000
-      #define DMA6_DEST_AD_D_ADDR_MSB                            31
-      #define DMA6_DEST_AD_D_ADDR_LSB                            0
-#define DMA6_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007614 ) 
-   #define DMA6_TXFR_LEN_MASK                                    0x3fffffff
-   #define DMA6_TXFR_LEN_WIDTH                                   30
-      #define DMA6_TXFR_LEN_YLENGTH_BITS                         29:16
-      #define DMA6_TXFR_LEN_YLENGTH_SET                          0x3fff0000
-      #define DMA6_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
-      #define DMA6_TXFR_LEN_YLENGTH_MSB                          29
-      #define DMA6_TXFR_LEN_YLENGTH_LSB                          16
-      #define DMA6_TXFR_LEN_XLENGTH_BITS                         15:0
-      #define DMA6_TXFR_LEN_XLENGTH_SET                          0x0000ffff
-      #define DMA6_TXFR_LEN_XLENGTH_CLR                          0xffff0000
-      #define DMA6_TXFR_LEN_XLENGTH_MSB                          15
-      #define DMA6_TXFR_LEN_XLENGTH_LSB                          0
-#define DMA6_STRIDE                                              HW_REGISTER_RO( 0x7e007618 ) 
-   #define DMA6_STRIDE_MASK                                      0xffffffff
-   #define DMA6_STRIDE_WIDTH                                     32
-      #define DMA6_STRIDE_D_STRIDE_BITS                          31:16
-      #define DMA6_STRIDE_D_STRIDE_SET                           0xffff0000
-      #define DMA6_STRIDE_D_STRIDE_CLR                           0x0000ffff
-      #define DMA6_STRIDE_D_STRIDE_MSB                           31
-      #define DMA6_STRIDE_D_STRIDE_LSB                           16
-      #define DMA6_STRIDE_S_STRIDE_BITS                          15:0
-      #define DMA6_STRIDE_S_STRIDE_SET                           0x0000ffff
-      #define DMA6_STRIDE_S_STRIDE_CLR                           0xffff0000
-      #define DMA6_STRIDE_S_STRIDE_MSB                           15
-      #define DMA6_STRIDE_S_STRIDE_LSB                           0
-#define DMA6_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00761c ) 
-   #define DMA6_NEXTCONBK_MASK                                   0xffffffe0
-   #define DMA6_NEXTCONBK_WIDTH                                  32
-      #define DMA6_NEXTCONBK_ADDR_BITS                           31:5
-      #define DMA6_NEXTCONBK_ADDR_SET                            0xffffffe0
-      #define DMA6_NEXTCONBK_ADDR_CLR                            0x0000001f
-      #define DMA6_NEXTCONBK_ADDR_MSB                            31
-      #define DMA6_NEXTCONBK_ADDR_LSB                            5
-#define DMA6_DEBUG                                               HW_REGISTER_RW( 0x7e007620 ) 
-   #define DMA6_DEBUG_MASK                                       0x1ffffff7
-   #define DMA6_DEBUG_WIDTH                                      29
-   #define DMA6_DEBUG_RESET                                      0000000000
-      #define DMA6_DEBUG_LITE_BITS                               28:28
-      #define DMA6_DEBUG_LITE_SET                                0x10000000
-      #define DMA6_DEBUG_LITE_CLR                                0xefffffff
-      #define DMA6_DEBUG_LITE_MSB                                28
-      #define DMA6_DEBUG_LITE_LSB                                28
-      #define DMA6_DEBUG_VERSION_BITS                            27:25
-      #define DMA6_DEBUG_VERSION_SET                             0x0e000000
-      #define DMA6_DEBUG_VERSION_CLR                             0xf1ffffff
-      #define DMA6_DEBUG_VERSION_MSB                             27
-      #define DMA6_DEBUG_VERSION_LSB                             25
-      #define DMA6_DEBUG_DMA_STATE_BITS                          24:16
-      #define DMA6_DEBUG_DMA_STATE_SET                           0x01ff0000
-      #define DMA6_DEBUG_DMA_STATE_CLR                           0xfe00ffff
-      #define DMA6_DEBUG_DMA_STATE_MSB                           24
-      #define DMA6_DEBUG_DMA_STATE_LSB                           16
-      #define DMA6_DEBUG_DMA_ID_BITS                             15:8
-      #define DMA6_DEBUG_DMA_ID_SET                              0x0000ff00
-      #define DMA6_DEBUG_DMA_ID_CLR                              0xffff00ff
-      #define DMA6_DEBUG_DMA_ID_MSB                              15
-      #define DMA6_DEBUG_DMA_ID_LSB                              8
-      #define DMA6_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
-      #define DMA6_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
-      #define DMA6_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
-      #define DMA6_DEBUG_OUTSTANDING_WRITES_MSB                  7
-      #define DMA6_DEBUG_OUTSTANDING_WRITES_LSB                  4
-      #define DMA6_DEBUG_READ_ERROR_BITS                         2:2
-      #define DMA6_DEBUG_READ_ERROR_SET                          0x00000004
-      #define DMA6_DEBUG_READ_ERROR_CLR                          0xfffffffb
-      #define DMA6_DEBUG_READ_ERROR_MSB                          2
-      #define DMA6_DEBUG_READ_ERROR_LSB                          2
-      #define DMA6_DEBUG_FIFO_ERROR_BITS                         1:1
-      #define DMA6_DEBUG_FIFO_ERROR_SET                          0x00000002
-      #define DMA6_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
-      #define DMA6_DEBUG_FIFO_ERROR_MSB                          1
-      #define DMA6_DEBUG_FIFO_ERROR_LSB                          1
-      #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
-      #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
-      #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
-      #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
-      #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma7.h b/bcm2708_chip/axi_dma7.h
deleted file mode 100644 (file)
index e544821..0000000
+++ /dev/null
@@ -1,247 +0,0 @@
-// This file was generated by the create_regs script
-#define DMA7_BASE                                                0x7e007700
-#define DMA7_CS                                                  HW_REGISTER_RW( 0x7e007700 ) 
-   #define DMA7_CS_MASK                                          0xf0ff017f
-   #define DMA7_CS_WIDTH                                         32
-   #define DMA7_CS_RESET                                         0000000000
-      #define DMA7_CS_RESET_BITS                                 31:31
-      #define DMA7_CS_RESET_SET                                  0x80000000
-      #define DMA7_CS_RESET_CLR                                  0x7fffffff
-      #define DMA7_CS_RESET_MSB                                  31
-      #define DMA7_CS_RESET_LSB                                  31
-      #define DMA7_CS_ABORT_BITS                                 30:30
-      #define DMA7_CS_ABORT_SET                                  0x40000000
-      #define DMA7_CS_ABORT_CLR                                  0xbfffffff
-      #define DMA7_CS_ABORT_MSB                                  30
-      #define DMA7_CS_ABORT_LSB                                  30
-      #define DMA7_CS_DISDEBUG_BITS                              29:29
-      #define DMA7_CS_DISDEBUG_SET                               0x20000000
-      #define DMA7_CS_DISDEBUG_CLR                               0xdfffffff
-      #define DMA7_CS_DISDEBUG_MSB                               29
-      #define DMA7_CS_DISDEBUG_LSB                               29
-      #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
-      #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
-      #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
-      #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
-      #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
-      #define DMA7_CS_PANIC_PRIORITY_BITS                        23:20
-      #define DMA7_CS_PANIC_PRIORITY_SET                         0x00f00000
-      #define DMA7_CS_PANIC_PRIORITY_CLR                         0xff0fffff
-      #define DMA7_CS_PANIC_PRIORITY_MSB                         23
-      #define DMA7_CS_PANIC_PRIORITY_LSB                         20
-      #define DMA7_CS_PRIORITY_BITS                              19:16
-      #define DMA7_CS_PRIORITY_SET                               0x000f0000
-      #define DMA7_CS_PRIORITY_CLR                               0xfff0ffff
-      #define DMA7_CS_PRIORITY_MSB                               19
-      #define DMA7_CS_PRIORITY_LSB                               16
-      #define DMA7_CS_ERROR_BITS                                 8:8
-      #define DMA7_CS_ERROR_SET                                  0x00000100
-      #define DMA7_CS_ERROR_CLR                                  0xfffffeff
-      #define DMA7_CS_ERROR_MSB                                  8
-      #define DMA7_CS_ERROR_LSB                                  8
-      #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
-      #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
-      #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
-      #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
-      #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
-      #define DMA7_CS_DREQ_STOPS_DMA_BITS                        5:5
-      #define DMA7_CS_DREQ_STOPS_DMA_SET                         0x00000020
-      #define DMA7_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
-      #define DMA7_CS_DREQ_STOPS_DMA_MSB                         5
-      #define DMA7_CS_DREQ_STOPS_DMA_LSB                         5
-      #define DMA7_CS_PAUSED_BITS                                4:4
-      #define DMA7_CS_PAUSED_SET                                 0x00000010
-      #define DMA7_CS_PAUSED_CLR                                &n