Initial commit
authorkristina <kb@kbs-iMac.local>
Mon, 16 May 2016 02:01:46 +0000 (03:01 +0100)
committerkristina <kb@kbs-iMac.local>
Mon, 16 May 2016 02:01:46 +0000 (03:01 +0100)
140 files changed:
LICENSE [new file with mode: 0755]
Makefile [new file with mode: 0755]
README.md [new file with mode: 0755]
arm_chainloader/Makefile [new file with mode: 0755]
arm_chainloader/chainloader.h [new file with mode: 0755]
arm_chainloader/drivers/uart.c [new file with mode: 0755]
arm_chainloader/firmware_rendezvous.c [new file with mode: 0755]
arm_chainloader/linker.lds [new file with mode: 0755]
arm_chainloader/main.c [new file with mode: 0755]
arm_chainloader/start.s [new file with mode: 0755]
arm_loader.c [new file with mode: 0755]
bcm2708_chip/README.txt [new file with mode: 0755]
bcm2708_chip/apb_arbiter_control.h [new file with mode: 0755]
bcm2708_chip/apb_async_bridge_ctrl.h [new file with mode: 0755]
bcm2708_chip/arm_control.h [new file with mode: 0755]
bcm2708_chip/aux_io.h [new file with mode: 0755]
bcm2708_chip/ave_in.h [new file with mode: 0755]
bcm2708_chip/ave_out.h [new file with mode: 0755]
bcm2708_chip/axi_dma0.h [new file with mode: 0755]
bcm2708_chip/axi_dma1.h [new file with mode: 0755]
bcm2708_chip/axi_dma15.h [new file with mode: 0755]
bcm2708_chip/axi_dma2.h [new file with mode: 0755]
bcm2708_chip/axi_dma3.h [new file with mode: 0755]
bcm2708_chip/axi_dma4.h [new file with mode: 0755]
bcm2708_chip/axi_dma5.h [new file with mode: 0755]
bcm2708_chip/axi_dma6.h [new file with mode: 0755]
bcm2708_chip/axi_dma7.h [new file with mode: 0755]
bcm2708_chip/axi_dma8.h [new file with mode: 0755]
bcm2708_chip/axi_dma_lite10.h [new file with mode: 0755]
bcm2708_chip/axi_dma_lite11.h [new file with mode: 0755]
bcm2708_chip/axi_dma_lite12.h [new file with mode: 0755]
bcm2708_chip/axi_dma_lite13.h [new file with mode: 0755]
bcm2708_chip/axi_dma_lite14.h [new file with mode: 0755]
bcm2708_chip/axi_dma_lite7.h [new file with mode: 0755]
bcm2708_chip/axi_dma_lite8.h [new file with mode: 0755]
bcm2708_chip/axi_dma_lite9.h [new file with mode: 0755]
bcm2708_chip/axi_dma_top.h [new file with mode: 0755]
bcm2708_chip/axi_performance0.h [new file with mode: 0755]
bcm2708_chip/axi_performance1.h [new file with mode: 0755]
bcm2708_chip/cam0.h [new file with mode: 0755]
bcm2708_chip/cam0_a0.h [new file with mode: 0755]
bcm2708_chip/cam1.h [new file with mode: 0755]
bcm2708_chip/cam1_a0.h [new file with mode: 0755]
bcm2708_chip/camccp.h [new file with mode: 0755]
bcm2708_chip/ccp2tx.h [new file with mode: 0755]
bcm2708_chip/ccp2tx_a0.h [new file with mode: 0755]
bcm2708_chip/cdp.h [new file with mode: 0755]
bcm2708_chip/clkman_image.h [new file with mode: 0755]
bcm2708_chip/cpg.h [new file with mode: 0755]
bcm2708_chip/cpi.h [new file with mode: 0755]
bcm2708_chip/cpr_apb2wtap.h [new file with mode: 0755]
bcm2708_chip/cpr_apb2wtap_a0.h [new file with mode: 0755]
bcm2708_chip/cpr_clkman.h [new file with mode: 0755]
bcm2708_chip/cpr_clkman_a0.h [new file with mode: 0755]
bcm2708_chip/cpr_powman.h [new file with mode: 0755]
bcm2708_chip/cpr_powman_a0.h [new file with mode: 0755]
bcm2708_chip/cryptohw.h [new file with mode: 0755]
bcm2708_chip/csi2.h [new file with mode: 0755]
bcm2708_chip/dpi.h [new file with mode: 0755]
bcm2708_chip/dsi.h [new file with mode: 0755]
bcm2708_chip/dsi4.h [new file with mode: 0755]
bcm2708_chip/emmc.h [new file with mode: 0755]
bcm2708_chip/flow_config.tcl [new file with mode: 0755]
bcm2708_chip/fpga_microblaze.h [new file with mode: 0755]
bcm2708_chip/fpga_peripheral.h [new file with mode: 0755]
bcm2708_chip/gpio.h [new file with mode: 0755]
bcm2708_chip/h264.h [new file with mode: 0755]
bcm2708_chip/hardware.h [new file with mode: 0755]
bcm2708_chip/hdcp.h [new file with mode: 0755]
bcm2708_chip/hdmi.h [new file with mode: 0755]
bcm2708_chip/hdmicore.h [new file with mode: 0755]
bcm2708_chip/hvs.h [new file with mode: 0755]
bcm2708_chip/i2c0.h [new file with mode: 0755]
bcm2708_chip/i2c1.h [new file with mode: 0755]
bcm2708_chip/i2c2.h [new file with mode: 0755]
bcm2708_chip/i2c_spi_slv.h [new file with mode: 0755]
bcm2708_chip/intctrl0.h [new file with mode: 0755]
bcm2708_chip/intctrl1.h [new file with mode: 0755]
bcm2708_chip/isp.h [new file with mode: 0755]
bcm2708_chip/israel_bg_dctram.h [new file with mode: 0755]
bcm2708_chip/israel_bg_instr.h [new file with mode: 0755]
bcm2708_chip/israel_dsp_registers.h [new file with mode: 0755]
bcm2708_chip/jpeg_top.h [new file with mode: 0755]
bcm2708_chip/l2_cache_ctrl.h [new file with mode: 0755]
bcm2708_chip/mphi.h [new file with mode: 0755]
bcm2708_chip/multicore_sync.h [new file with mode: 0755]
bcm2708_chip/nexus_uba.h [new file with mode: 0755]
bcm2708_chip/otp.h [new file with mode: 0755]
bcm2708_chip/pcm.h [new file with mode: 0755]
bcm2708_chip/perfmon.h [new file with mode: 0755]
bcm2708_chip/peri_image_arb_ctrl.h [new file with mode: 0755]
bcm2708_chip/pixel_valve0.h [new file with mode: 0755]
bcm2708_chip/pixel_valve1.h [new file with mode: 0755]
bcm2708_chip/pixel_valve2.h [new file with mode: 0755]
bcm2708_chip/pwm.h [new file with mode: 0755]
bcm2708_chip/register_map.h [new file with mode: 0755]
bcm2708_chip/register_map_macros.h [new file with mode: 0755]
bcm2708_chip/rng.h [new file with mode: 0755]
bcm2708_chip/rng_a0.h [new file with mode: 0755]
bcm2708_chip/rnghw.h [new file with mode: 0755]
bcm2708_chip/sdc_addr_front.h [new file with mode: 0755]
bcm2708_chip/sdc_ctrl.h [new file with mode: 0755]
bcm2708_chip/sdc_dq_front.h [new file with mode: 0755]
bcm2708_chip/sdhost.h [new file with mode: 0755]
bcm2708_chip/slimbus.h [new file with mode: 0755]
bcm2708_chip/slimbus_a0.h [new file with mode: 0755]
bcm2708_chip/smi.h [new file with mode: 0755]
bcm2708_chip/spi_master.h [new file with mode: 0755]
bcm2708_chip/sv_chip_regmap.h [new file with mode: 0755]
bcm2708_chip/system_arbiter_ctrl.h [new file with mode: 0755]
bcm2708_chip/tectl.h [new file with mode: 0755]
bcm2708_chip/tectl_a0.h [new file with mode: 0755]
bcm2708_chip/tempsens.h [new file with mode: 0755]
bcm2708_chip/testbus.h [new file with mode: 0755]
bcm2708_chip/thread_ctrl.h [new file with mode: 0755]
bcm2708_chip/timer.h [new file with mode: 0755]
bcm2708_chip/txp.h [new file with mode: 0755]
bcm2708_chip/uart.h [new file with mode: 0755]
bcm2708_chip/usb.h [new file with mode: 0755]
bcm2708_chip/v3d.h [new file with mode: 0755]
bcm2708_chip/vcodec.h [new file with mode: 0755]
bcm2708_chip/vec.h [new file with mode: 0755]
bcm2708_chip/vpu_arb_ctrl.h [new file with mode: 0755]
bcm2708_chip/vpu_l1_cache_ctrl.h [new file with mode: 0755]
buildall.sh [new file with mode: 0755]
chainloader_inc.s [new file with mode: 0755]
ghetto.s [new file with mode: 0755]
hardware.h [new file with mode: 0755]
hardware_vc4.h [new file with mode: 0755]
lib/common.h [new file with mode: 0755]
lib/memcpy.c [new file with mode: 0755]
lib/panic.c [new file with mode: 0755]
lib/stdarg.h [new file with mode: 0755]
lib/udelay.c [new file with mode: 0755]
lib/xprintf.c [new file with mode: 0755]
lib/xprintf.h [new file with mode: 0755]
romstage.c [new file with mode: 0755]
sdram.c [new file with mode: 0755]
start.s [new file with mode: 0755]
trap.c [new file with mode: 0755]

diff --git a/LICENSE b/LICENSE
new file mode 100755 (executable)
index 0000000..2f6a216
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,241 @@
+Code copyrighted to Broadom Corporation is released under BSD 3-Clause License\r
+==============================================================================\r
+\r
+Copyright (c) 2009-2014, Broadcom Corporation All rights reserved. Redistribution and use in source\r
+and binary forms, with or without modification, are permitted provided that the following conditions\r
+are met:\r
+\r
+1. Redistributions of source code must retain the above copyright notice, this list of\r
+conditions and the following disclaimer.\r
+2. Redistributions in binary form must reproduce the above\r
+copyright notice, this list of conditions and the following disclaimer in the documentation and/or\r
+other materials provided with the distribution.\r
+3. Neither the name of the copyright holder nor the\r
+names of its contributors may be used to endorse or promote products derived from this software\r
+without specific prior written permission. \r
+\r
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND\r
+CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO\r
+EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+POSSIBILITY OF SUCH DAMAGE.\r
+\r
+All other code released under GPLv2+\r
+====================================\r
+\r
+GNU GENERAL PUBLIC LICENSE\r
+\r
+Version 2, June 1991\r
+\r
+Copyright (C) 1989, 1991 Free Software Foundation, Inc.   51 Franklin Street, Fifth Floor, Boston,\r
+MA  02110-1301, USA\r
+\r
+Everyone is permitted to copy and distribute verbatim copies of this license document, but changing\r
+it is not allowed. Preamble\r
+\r
+The licenses for most software are designed to take away your freedom to share and change it. By\r
+contrast, the GNU General Public License is intended to guarantee your freedom to share and change\r
+free software--to make sure the software is free for all its users. This General Public License\r
+applies to most of the Free Software Foundation's software and to any other program whose authors\r
+commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser\r
+General Public License instead.) You can apply it to your programs, too.\r
+\r
+When we speak of free software, we are referring to freedom, not price. Our General Public Licenses\r
+are designed to make sure that you have the freedom to distribute copies of free software (and\r
+charge for this service if you wish), that you receive source code or can get it if you want it,\r
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+do these things.\r
+\r
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+\r
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+\r
+Also, for each author's protection and ours, we want to make certain that everyone understands that\r
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+Finally, any free program is threatened constantly by software patents. We wish to avoid the danger\r
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+\r
+TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\r
+\r
+0. This License applies to any program or other work which contains a notice placed by the copyright\r
+holder saying it may be distributed under the terms of this General Public License. The "Program",\r
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+(Hereinafter, translation is included without limitation in the term "modification".) Each licensee\r
+is addressed as "you".\r
+\r
+Activities other than copying, distribution and modification are not covered by this License; they\r
+are outside its scope. The act of running the Program is not restricted, and the output from the\r
+Program is covered only if its contents constitute a work based on the Program (independent of\r
+having been made by running the Program). Whether that is true depends on what the Program does.\r
+\r
+1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in\r
+any medium, provided that you conspicuously and appropriately publish on each copy an appropriate\r
+copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License\r
+and to the absence of any warranty; and give any other recipients of the Program a copy of this\r
+License along with the Program.\r
+\r
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+\r
+2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based\r
+on the Program, and copy and distribute such modifications or work under the terms of Section 1\r
+above, provided that you also meet all of these conditions:\r
+\r
+a) You must cause the modified files to carry prominent notices stating that you changed the files\r
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+no charge to all third parties under the terms of this License. c) If the modified program normally\r
+reads commands interactively when run, you must cause it, when started running for such interactive\r
+use in the most ordinary way, to print or display an announcement including an appropriate copyright\r
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+users may redistribute the program under these conditions, and telling the user how to view a copy\r
+of this License. (Exception: if the Program itself is interactive but does not normally print such\r
+an announcement, your work based on the Program is not required to print an announcement.) These\r
+requirements apply to the modified work as a whole. If identifiable sections of that work are not\r
+derived from the Program, and can be reasonably considered independent and separate works in\r
+themselves, then this License, and its terms, do not apply to those sections when you distribute\r
+them as separate works. But when you distribute the same sections as part of a whole which is a work\r
+based on the Program, the distribution of the whole must be on the terms of this License, whose\r
+permissions for other licensees extend to the entire whole, and thus to each and every part\r
+regardless of who wrote it.\r
+\r
+Thus, it is not the intent of this section to claim rights or contest your rights to work written\r
+entirely by you; rather, the intent is to exercise the right to control the distribution of\r
+derivative or collective works based on the Program.\r
+\r
+In addition, mere aggregation of another work not based on the Program with the Program (or with a\r
+work based on the Program) on a volume of a storage or distribution medium does not bring the other\r
+work under the scope of this License.\r
+\r
+3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code\r
+or executable form under the terms of Sections 1 and 2 above provided that you also do one of the\r
+following:\r
+\r
+a) Accompany it with the complete corresponding machine-readable source code, which must be\r
+distributed under the terms of Sections 1 and 2 above on a medium customarily used for software\r
+interchange; or, b) Accompany it with a written offer, valid for at least three years, to give any\r
+third party, for a charge no more than your cost of physically performing source distribution, a\r
+complete machine-readable copy of the corresponding source code, to be distributed under the terms\r
+of Sections 1 and 2 above on a medium customarily used for software interchange; or, c) Accompany it\r
+with the information you received as to the offer to distribute corresponding source code. (This\r
+alternative is allowed only for noncommercial distribution and only if you received the program in\r
+object code or executable form with such an offer, in accord with Subsection b above.) The source\r
+code for a work means the preferred form of the work for making modifications to it. For an\r
+executable work, complete source code means all the source code for all modules it contains, plus\r
+any associated interface definition files, plus the scripts used to control compilation and\r
+installation of the executable. However, as a special exception, the source code distributed need\r
+not include anything that is normally distributed (in either source or binary form) with the major\r
+components (compiler, kernel, and so on) of the operating system on which the executable runs,\r
+unless that component itself accompanies the executable.\r
+\r
+If distribution of executable or object code is made by offering access to copy from a designated\r
+place, then offering equivalent access to copy the source code from the same place counts as\r
+distribution of the source code, even though third parties are not compelled to copy the source\r
+along with the object code.\r
+\r
+4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided\r
+under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is\r
+void, and will automatically terminate your rights under this License. However, parties who have\r
+received copies, or rights, from you under this License will not have their licenses terminated so\r
+long as such parties remain in full compliance.\r
+\r
+5. You are not required to accept this License, since you have not signed it. However, nothing else\r
+grants you permission to modify or distribute the Program or its derivative works. These actions are\r
+prohibited by law if you do not accept this License. Therefore, by modifying or distributing the\r
+Program (or any work based on the Program), you indicate your acceptance of this License to do so,\r
+and all its terms and conditions for copying, distributing or modifying the Program or works based\r
+on it.\r
+\r
+6. Each time you redistribute the Program (or any work based on the Program), the recipient\r
+automatically receives a license from the original licensor to copy, distribute or modify the\r
+Program subject to these terms and conditions. You may not impose any further restrictions on the\r
+recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance\r
+by third parties to this License.\r
+\r
+7. If, as a consequence of a court judgment or allegation of patent infringement or for any other\r
+reason (not limited to patent issues), conditions are imposed on you (whether by court order,\r
+agreement or otherwise) that contradict the conditions of this License, they do not excuse you from\r
+the conditions of this License. If you cannot distribute so as to satisfy simultaneously your\r
+obligations under this License and any other pertinent obligations, then as a consequence you may\r
+not distribute the Program at all. For example, if a patent license would not permit royalty-free\r
+redistribution of the Program by all those who receive copies directly or indirectly through you,\r
+then the only way you could satisfy both it and this License would be to refrain entirely from\r
+distribution of the Program.\r
+\r
+If any portion of this section is held invalid or unenforceable under any particular circumstance,\r
+the balance of the section is intended to apply and the section as a whole is intended to apply in\r
+other circumstances.\r
+\r
+It is not the purpose of this section to induce you to infringe any patents or other property right\r
+claims or to contest validity of any such claims; this section has the sole purpose of protecting\r
+the integrity of the free software distribution system, which is implemented by public license\r
+practices. Many people have made generous contributions to the wide range of software distributed\r
+through that system in reliance on consistent application of that system; it is up to the\r
+author/donor to decide if he or she is willing to distribute software through any other system and a\r
+licensee cannot impose that choice.\r
+\r
+This section is intended to make thoroughly clear what is believed to be a consequence of the rest\r
+of this License.\r
+\r
+8. If the distribution and/or use of the Program is restricted in certain countries either by\r
+patents or by copyrighted interfaces, the original copyright holder who places the Program under\r
+this License may add an explicit geographical distribution limitation excluding those countries, so\r
+that distribution is permitted only in or among countries not thus excluded. In such case, this\r
+License incorporates the limitation as if written in the body of this License.\r
+\r
+9. The Free Software Foundation may publish revised and/or new versions of the General Public\r
+License from time to time. Such new versions will be similar in spirit to the present version, but\r
+may differ in detail to address new problems or concerns.\r
+\r
+Each version is given a distinguishing version number. If the Program specifies a version number of\r
+this License which applies to it and "any later version", you have the option of following the terms\r
+and conditions either of that version or of any later version published by the Free Software\r
+Foundation. If the Program does not specify a version number of this License, you may choose any\r
+version ever published by the Free Software Foundation.\r
+\r
+10. If you wish to incorporate parts of the Program into other free programs whose distribution\r
+conditions are different, write to the author to ask for permission. For software which is\r
+copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes\r
+make exceptions for this. Our decision will be guided by the two goals of preserving the free status\r
+of all derivatives of our free software and of promoting the sharing and reuse of software\r
+generally.\r
+\r
+NO WARRANTY\r
+\r
+11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE\r
+EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS\r
+AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR\r
+IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
+PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.\r
+SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR\r
+CORRECTION.\r
+\r
+12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER,\r
+OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO\r
+YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF\r
+THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING\r
+RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO\r
+OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\r
+POSSIBILITY OF SUCH DAMAGES.\r
+\r
+END OF TERMS AND CONDITIONS\r
diff --git a/Makefile b/Makefile
new file mode 100755 (executable)
index 0000000..898bf05
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,81 @@
+
+TARGET_BOOTCODE = bootcode.bin
+
+#
+# when building bootcode.bin, always ensure start.s is at the top, providing
+# the 0x200 byte long header and some init code.
+# 
+SRCS = \
+       start.s \
+       romstage.c \
+       sdram.c \
+       arm_loader.c \
+       trap.c \
+       lib/xprintf.c \
+       lib/panic.c \
+       lib/udelay.c \
+       lib/memcpy.c \
+       chainloader_inc.s
+
+ARCH = vc4
+
+BUILD_DIR = build
+TARGET_BUILD_DIR = $(BUILD_DIR)/$(ARCH)-objects
+PRODUCT_DIRECTORY = $(BUILD_DIR)
+
+NO_COLOR=""
+OK_COLOR=""
+ERROR_COLOR=""
+WARN_COLOR=""
+
+.PHONY: default all clean create_build_directory device
+
+default: $(TARGET_BOOTCODE)
+
+OBJ := $(addprefix $(TARGET_BUILD_DIR)/, $(addsuffix .o, $(basename $(SRCS))))
+
+CROSS_COMPILE = /Developer/vc4-toolchain/prefix/bin/vc4-elf-
+CC = $(CROSS_COMPILE)gcc
+AS = $(CC)
+OBJCOPY = $(CROSS_COMPILE)objcopy
+LINKFLAGS = -nostdlib -nostartfiles
+CFLAGS = -c -nostdlib -std=c11
+ASFLAGS = -c -nostdlib -x assembler-with-cpp
+
+HEADERS := \
+       $(shell find . -type f -name '*.h') \
+       $(shell find . -type f -name '*.hpp')
+
+create_build_directory:
+       @mkdir -p $(TARGET_BUILD_DIR)
+       @mkdir -p $(PRODUCT_DIRECTORY)
+
+CREATE_SUBDIR = \
+       @DIR="$(dir $@)"; \
+       if [ ! -d $$DIR ]; then mkdir -p $$DIR; fi
+
+
+#
+# rules to build c/asm files.
+# 
+$(TARGET_BUILD_DIR)/%.o: %.c $(HEADERS)
+       $(CREATE_SUBDIR)
+       @echo $(WARN_COLOR)CC  $(NO_COLOR) $@
+       @$(CC) $(CFLAGS) $< -o $@
+
+$(TARGET_BUILD_DIR)/%.o: %.s $(HEADERS)
+       $(CREATE_SUBDIR)
+       @echo $(WARN_COLOR)AS  $(NO_COLOR) $@
+       @$(AS) $(ASFLAGS) $< -o $@
+
+.PRECIOUS: $(OBJ)
+
+$(TARGET_BOOTCODE): create_build_directory $(OBJ)
+       @echo $(WARN_COLOR)LD  $(NO_COLOR) $@.elf
+       @$(CC) $(LINKFLAGS) $(OBJ) -o $(PRODUCT_DIRECTORY)/$@.elf
+       @echo $(WARN_COLOR)OBJ$(NO_COLOR) $@
+       @$(OBJCOPY) -O binary $(PRODUCT_DIRECTORY)/$@.elf $(PRODUCT_DIRECTORY)/$@
+
+clean:
+       @echo $(ERROR_COLOR)CLEAN$(NO_COLOR)
+       @-rm -rf ./$(BUILD_DIR)
\ No newline at end of file
diff --git a/README.md b/README.md
new file mode 100755 (executable)
index 0000000..6cc1def
--- /dev/null
+++ b/README.md
@@ -0,0 +1,34 @@
+# Minimal Raspberry Pi VPU firmware\r
+This is a small firmware for RPi VPU (VideoCore4) versions 1/2/3 that is capable of initializing UART, VPU PLL (PLLC) and ARM itself. It's intended to be used instead of stock `bootcode.bin` on RPi's SD card. You **need** to have UART to see anything meaningful as far as output goes.\r
+\r
+This has been tested on RPi1 Model B (Hynix PoP DDR), RPi 2 Model B and RPi 3 Model B (both Elpida DDR). \r
+\r
+If you want to contact me because you're interested in contributing, you can message `kristina` on Freenode, but I would suggest talking in `#raspberrypi-internals` instead.\r
+\r
+## Building\r
+\r
+You need Julian Brown's VC4 toolchain to build this (https://github.com/puppeh/vc4-toolchain) as well as a arm-none-eabi-toolchain. You can tweak the paths to it in CROSS_COMPILE in `Makefile` (for VC4) and for ARM in `arm_chainloader/Makefile`. After you've done it, run `buildall.sh` and you should have a blob in `build/bootcode.bin`. \r
+\r
+## Technical Details\r
+The firmware is split into two parts, a VC4 part and and ARM part. The VC4 part initializes PLLC and moves VPU over to it, and then brings up UART. It then performs SDRAM initialization, making SDRAM available at `0xC0000000` (uncached alias). The ARM loader will do ARM initialization and then copy the ARM bootloader that's embedded in it to the alias. It will then map it to `0x0` in ARM's memory space and start ARM. The code under `arm_chainloader` is what will run on the ARM. \r
+\r
+The current makefiles in the ARM part of it aim at **RPi1** (ie. ARMv6) but they can be changed to ARMv7 if you want to build it for a newer model. I tested it on all RPi models and it works without any issues as far as I can tell (ARM can access peripherals and memory just fine as AXI supervisor).\r
+\r
+**Beware:** This doesn't handle SMP at the moment so if you run this on RPi2 and above, all ARM cores will start executing the ARM bootloader code at the start which could cause problems. I will fix this soon.\r
+\r
+## Issues\r
+ * PLL rate on ARM is slow, it's a bit annoying. Need to tweak the PLL rate later.\r
+ * Code that prints SDRAM capacity is a bit wrong, I need to fix it, but it makes no functional difference.\r
+ * At the moment the ARM side of the bootloader doesn't do anything aside from printing a line to UART. I'm going to add an SDHOST driver to load the next stage bootloader to it at some point.\r
+ * It only maps a small amount of memory at the moment. You can tweak it in `arm_loader.c` if you want.\r
+\r
+## Does/Will it boot Linux?\r
+\r
+Eventually maybe. Since `start.elf` is responsible for clock and power management (all registers in the `cpr` block), these drivers will have to be rewritten on ARM (or even on the open source VC4) to have any meaningful peripherals working properly (for example HDMI/DMA/Pixel Valve/Whatever). UART and GPIOs do work though.\r
+\r
+## Thanks To\r
+ * **Herman Hermitage** for his VC4 documentation and for helping me with working out suitable ARM PLL configurations.\r
+ * **Julian Brown** for reviewing my code and for his awesome VC4 toolchain.\r
+ * **phire** for reviewing my code.\r
+ * **Broadcom** for their header release.\r
+ * Various other people not mentioned here.
\ No newline at end of file
diff --git a/arm_chainloader/Makefile b/arm_chainloader/Makefile
new file mode 100755 (executable)
index 0000000..05b8945
--- /dev/null
@@ -0,0 +1,72 @@
+
+TARGET_ARM_CHAINLOADER = arm_chainloader.bin
+
+SRCS = \
+       start.s \
+       drivers/uart.c \
+       ../lib/xprintf.c \
+       firmware_rendezvous.c \
+       main.c
+
+ARCH = armv6zk
+
+BUILD_DIR = build
+TARGET_BUILD_DIR = $(BUILD_DIR)/$(ARCH)-objects
+PRODUCT_DIRECTORY = $(BUILD_DIR)
+
+NO_COLOR=""
+OK_COLOR=""
+ERROR_COLOR=""
+WARN_COLOR=""
+
+.PHONY: default all clean create_build_directory device
+
+default: $(TARGET_ARM_CHAINLOADER)
+
+OBJ := $(addprefix $(TARGET_BUILD_DIR)/, $(addsuffix .o, $(basename $(SRCS))))
+
+CROSS_COMPILE = arm-none-eabi-
+CC = $(CROSS_COMPILE)gcc
+AS = $(CC)
+OBJCOPY = $(CROSS_COMPILE)objcopy
+LINKFLAGS = -nostdlib -march=$(ARCH) -Wl,--build-id=none -T linker.lds
+COMMON_FLAGS = -c -nostdlib -nostartfiles -ffreestanding -march=$(ARCH) -I../ -I./ -mfpu=vfp -mfloat-abi=hard -mtune=arm1176jzf-s
+CFLAGS = $(COMMON_FLAGS) -std=c11 
+ASFLAGS = $(COMMON_FLAGS) -x assembler-with-cpp
+
+HEADERS := \
+       $(shell find . -type f -name '*.h') \
+       $(shell find . -type f -name '*.hpp')
+
+create_build_directory:
+       @mkdir -p $(TARGET_BUILD_DIR)
+       @mkdir -p $(PRODUCT_DIRECTORY)
+
+CREATE_SUBDIR = \
+       @DIR="$(dir $@)"; \
+       if [ ! -d $$DIR ]; then mkdir -p $$DIR; fi
+
+#
+# rules to build c/asm files.
+# 
+$(TARGET_BUILD_DIR)/%.o: %.c $(HEADERS)
+       $(CREATE_SUBDIR)
+       @echo $(WARN_COLOR)CC  $(NO_COLOR) $@
+       @$(CC) $(CFLAGS) $< -o $@
+
+$(TARGET_BUILD_DIR)/%.o: %.s $(HEADERS)
+       $(CREATE_SUBDIR)
+       @echo $(WARN_COLOR)AS  $(NO_COLOR) $@
+       @$(AS) $(ASFLAGS) $< -o $@
+
+.PRECIOUS: $(OBJ)
+
+$(TARGET_ARM_CHAINLOADER): create_build_directory $(OBJ)
+       @echo $(WARN_COLOR)LD  $(NO_COLOR) $@.elf
+       @$(CC) $(LINKFLAGS) $(OBJ) -o $(PRODUCT_DIRECTORY)/$@.elf -lgcc
+       @echo $(WARN_COLOR)OBJ$(NO_COLOR) $@
+       @$(OBJCOPY) -O binary $(PRODUCT_DIRECTORY)/$@.elf $(PRODUCT_DIRECTORY)/$@
+
+clean:
+       @echo $(ERROR_COLOR)CLEAN$(NO_COLOR)
+       @-rm -rf ./$(BUILD_DIR)
\ No newline at end of file
diff --git a/arm_chainloader/chainloader.h b/arm_chainloader/chainloader.h
new file mode 100755 (executable)
index 0000000..4aa7626
--- /dev/null
@@ -0,0 +1,5 @@
+#pragma once\r
+\r
+#include <lib/xprintf.h>\r
+\r
+#define printf xprintf
\ No newline at end of file
diff --git a/arm_chainloader/drivers/uart.c b/arm_chainloader/drivers/uart.c
new file mode 100755 (executable)
index 0000000..3b20ac1
--- /dev/null
@@ -0,0 +1,10 @@
+#include <hardware.h>\r
+\r
+void uart_putc(unsigned int ch)\r
+{\r
+       while(1) {\r
+               if (mmio_read32(AUX_MU_LSR_REG) & 0x20)\r
+                       break;\r
+       }\r
+       mmio_write32(AUX_MU_IO_REG, ch);\r
+}\r
diff --git a/arm_chainloader/firmware_rendezvous.c b/arm_chainloader/firmware_rendezvous.c
new file mode 100755 (executable)
index 0000000..0b8064a
--- /dev/null
@@ -0,0 +1,34 @@
+#include <stdint.h>\r
+#include <hardware.h>\r
+#include <chainloader.h>\r
+\r
+extern void main();\r
+extern void uart_putc(int c);\r
+\r
+void _firmware_rendezvous() {\r
+       /* Channels to talk to the firmware */\r
+       volatile uint32_t* arm_membase = (volatile uint32_t*)0x0;\r
+       volatile uint32_t* comm1 = arm_membase + 8;\r
+       volatile uint32_t* comm2 = arm_membase + 9;\r
+       volatile uint32_t* comm3 = arm_membase + 10;\r
+       volatile uint32_t* comm4 = arm_membase + 11;\r
+\r
+       *comm1 = 0xCAFEEEEE;\r
+\r
+       /* \r
+        * check if we have peripheral access\r
+        * if so, we don't need the VPU anymore\r
+        */\r
+       if (ARM_ID != ARM_IDVAL) {\r
+               *comm1 = 0xDEADCAFE;\r
+               return;\r
+       }\r
+\r
+       *comm4 = VPU_KILL_COMMAND;\r
+\r
+       /* stall for a bit to let the VPU commit suicide */\r
+       for (int i = 0; i < 0x10000; i++)\r
+               *comm2 = i;\r
+\r
+       main();\r
+}
\ No newline at end of file
diff --git a/arm_chainloader/linker.lds b/arm_chainloader/linker.lds
new file mode 100755 (executable)
index 0000000..672df5d
--- /dev/null
@@ -0,0 +1,10 @@
+MEMORY\r
+{\r
+    ram : ORIGIN = 0x0, LENGTH = 0x100000\r
+}\r
+\r
+SECTIONS\r
+{\r
+    .text : { *(.text*) } > ram\r
+    .bss : { *(.bss*) } > ram\r
+}
\ No newline at end of file
diff --git a/arm_chainloader/main.c b/arm_chainloader/main.c
new file mode 100755 (executable)
index 0000000..c6903e1
--- /dev/null
@@ -0,0 +1,7 @@
+#include <stdint.h>\r
+#include <chainloader.h>\r
+#include <hardware.h>\r
+\r
+void main() {\r
+       printf("%s: arm_chainloader started on ARM, continuing boot from here ...\n", __FUNCTION__);\r
+}
\ No newline at end of file
diff --git a/arm_chainloader/start.s b/arm_chainloader/start.s
new file mode 100755 (executable)
index 0000000..3d04b40
--- /dev/null
@@ -0,0 +1,24 @@
+.text\r
+.globl _start\r
+_start:\r
+       /* vectors */\r
+       nop\r
+       nop\r
+       nop\r
+       nop\r
+       nop\r
+       nop\r
+       nop\r
+       nop\r
+\r
+       /* comm chan */\r
+       nop\r
+       nop\r
+       nop\r
+       nop\r
+\r
+       mov sp, #0x2000000\r
+       b _firmware_rendezvous\r
+\r
+L_deadloop:\r
+       b L_deadloop\r
diff --git a/arm_loader.c b/arm_loader.c
new file mode 100755 (executable)
index 0000000..748a810
--- /dev/null
@@ -0,0 +1,276 @@
+/*=============================================================================\r
+Copyright (C) 2016 Kristina Brooks\r
+All rights reserved.\r
+\r
+This program is free software; you can redistribute it and/or\r
+modify it under the terms of the GNU General Public License\r
+as published by the Free Software Foundation; either version 2\r
+of the License, or (at your option) any later version.\r
+\r
+This program is distributed in the hope that it will be useful,\r
+but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+GNU General Public License for more details.\r
+\r
+FILE DESCRIPTION\r
+ARM initialization stuff.\r
+\r
+=============================================================================*/\r
+\r
+#include "lib/common.h"\r
+#include "hardware.h"\r
+\r
+\r
+extern char L_arm_code_start;\r
+extern char L_arm_code_end;\r
+\r
+#define ARM_MEMORY_BASE 0xC0000000\r
+#define ARM_BKPT_OPCODE 0xE1200070\r
+\r
+/* XXX: What is this? */\r
+#define PM_UNK_CFG_CLR 0xFFFCFFFF\r
+\r
+static bool arm_power_wait_bit(uint32_t bit) {\r
+       for (int i = 0; i < 20; i++) {\r
+               if (PM_PROC & bit) {\r
+                       return true;\r
+               }\r
+               udelay(100);\r
+       }\r
+       return false;\r
+}\r
+\r
+static inline void arm_assert_global_reset() {\r
+       printf("%s: RSTN ...\n", __FUNCTION__);\r
+       PM_PROC |= PM_PASSWORD | PM_PROC_ARMRSTN_SET;\r
+       udelay(300);\r
+}\r
+\r
+static void arm_enable_power() {\r
+       uint32_t pmv;\r
+\r
+       printf("%s: INIT PM_PROC: 0x%X\n", __FUNCTION__, PM_PROC);\r
+\r
+       printf("%s: requesting power up ...\n", __FUNCTION__);\r
+\r
+       /* deassert all reset lines */\r
+       pmv = ((PM_PROC & PM_PROC_ARMRSTN_CLR) & PM_UNK_CFG_CLR) | PM_PASSWORD;\r
+\r
+       PM_PROC = pmv;\r
+\r
+       pmv |= PM_PROC_POWUP_SET;\r
+       udelay(10);\r
+       PM_PROC = pmv;\r
+\r
+       printf("%s: POWUP PM_PROC: 0x%X\n", __FUNCTION__, PM_PROC); \r
+\r
+       /* wait for POWOK */\r
+       printf("%s: waiting for power up ...\n", __FUNCTION__);\r
+       for (int i = 1; i < 5; i++) {\r
+               if (!arm_power_wait_bit(PM_PROC_POWOK_SET)) {\r
+                       /* only go up to 3 */\r
+                       if (i == 4) {\r
+                               panic("timed out waiting for power up, state of PM_PROC is: 0x%X", PM_PROC);\r
+                       }\r
+\r
+                       pmv = (pmv & PM_UNK_CFG_CLR) | (i << PM_PROC_CFG_LSB);\r
+                       printf("%s: timed out, trying different CFG: 0x%X \n", __FUNCTION__, pmv);\r
+                       PM_PROC = pmv;\r
+               }\r
+       }\r
+       \r
+       pmv |= PM_PROC_ISPOW_SET;\r
+       PM_PROC = pmv;\r
+\r
+       pmv |= PM_PROC_MEMREP_SET;\r
+       PM_PROC = pmv;\r
+\r
+       printf("%s: waiting for MRDONE ...\n", __FUNCTION__);\r
+       if (!arm_power_wait_bit(PM_PROC_MRDONE_SET)) {\r
+               panic("timed out waiting for MRDONE, state of PM_PROC is: 0x%X", PM_PROC);\r
+       }\r
+\r
+       printf("%s: setting ISFUNC ...\n", __FUNCTION__);\r
+\r
+       pmv |= PM_PROC_ISFUNC_SET;\r
+       PM_PROC = pmv;\r
+\r
+       printf("%s: ARM power domain initialized succesfully, state of PM_PROC is: 0x%X!\n", __FUNCTION__, PM_PROC);\r
+}\r
+\r
+static void arm_bresp_cycle_write(uint32_t bits) {\r
+       ARM_CONTROL0 = (ARM_CONTROL0 & ~(ARM_C0_BRESP1|ARM_C0_BRESP2)) | bits;\r
+       printf("0x%X,", bits);\r
+       udelay(30);\r
+}\r
+\r
+static uint32_t g_BrespTab[] = {\r
+       0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x1C, 0x18, 0x1C, 0x18, 0x0,\r
+       0x10, 0x14, 0x10, 0x1C, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x0,\r
+       0x10, 0x14, 0x10, 0x1C, 0x18, 0x1C, 0x10, 0x14, 0x18, 0x1C, 0x10, 0x14, 0x10, 0x0,\r
+       0x10, 0x14, 0x18, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x0,\r
+       0x10, 0x14, 0x18, 0x14, 0x18, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x18, 0x0\r
+};\r
+static void arm_bresp_cycle() {\r
+       /* my little axi - peripherals are magic */\r
+       printf("Cycling AXI bits ...\n\t", __FUNCTION__);\r
+       \r
+       for (int i = 0; i < sizeof(g_BrespTab)/sizeof(g_BrespTab[0]); i++) {\r
+               arm_bresp_cycle_write(g_BrespTab[i]);\r
+\r
+               if (i && ((i % 14) == 0))\r
+                       printf("\n\t");\r
+       }\r
+\r
+       printf("\n");\r
+}\r
+\r
+void arm_setup_bridge(bool bresp_cycle) {\r
+       printf("%s: setting up async bridge ...\n", __FUNCTION__);\r
\r
+       if (bresp_cycle) {\r
+               arm_assert_global_reset();\r
+               arm_bresp_cycle();\r
+               arm_assert_global_reset();\r
+               udelay(300);\r
+       }\r
+\r
+       ARM_CONTROL1 &= ~ARM_C1_REQSTOP;\r
+       udelay(300);\r
+\r
+       if (!bresp_cycle) \r
+               arm_assert_global_reset();\r
+       \r
+       printf("%s: bridge init done, PM_PROC is now: 0x%X!\n", __FUNCTION__, PM_PROC);\r
+}\r
+\r
+static void arm_set_clock_source(unsigned int source) {\r
+       CM_ARMCTL = CM_PASSWORD | source | CM_ARMCTL_ENAB_SET;\r
+}\r
+\r
+static void arm_enable_clock() {\r
+       printf("%s: initializing PLLB ...\n", __FUNCTION__);\r
+\r
+       /* oscillator->pllb */\r
+       A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_PLLBEN_SET;\r
+\r
+       A2W_PLLB_FRAC = A2W_PASSWORD | 0xeaaa8;\r
+       A2W_PLLB_CTRL = A2W_PASSWORD | 48 | 0x1000;\r
+\r
+       CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET;\r
+       CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET;\r
+\r
+       A2W_PLLB_ANA3 = A2W_PASSWORD | 0x100;\r
+       A2W_PLLB_ANA2 = A2W_PASSWORD | 0x0;\r
+       A2W_PLLB_ANA1 = A2W_PASSWORD | 0x140000;\r
+       A2W_PLLB_ANA0 = A2W_PASSWORD | 0x0;\r
+\r
+       A2W_PLLB_DIG3 = A2W_PASSWORD | 0x0;\r
+       A2W_PLLB_DIG2 = A2W_PASSWORD | 0x400000;\r
+       A2W_PLLB_DIG1 = A2W_PASSWORD | 0x3a;\r
+       A2W_PLLB_DIG0 = A2W_PASSWORD | 48 | 0xAAA000;\r
+\r
+       A2W_PLLB_CTRL = A2W_PASSWORD | 48 | 0x21000;\r
+\r
+       A2W_PLLB_DIG3 = A2W_PASSWORD | 0x2;\r
+       A2W_PLLB_DIG2 = A2W_PASSWORD | 0x402401;\r
+       A2W_PLLB_DIG1 = A2W_PASSWORD | 0x403a;\r
+       A2W_PLLB_DIG0 = A2W_PASSWORD | 48 | 0xAAA000;\r
+\r
+       A2W_PLLB_ARM = A2W_PASSWORD | 2;\r
+\r
+       CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET | CM_PLLB_LOADARM_SET;\r
+       CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET;\r
+       CM_PLLB = CM_PASSWORD;\r
+\r
+       arm_set_clock_source(4);\r
+\r
+       printf("KAIP  = 0x%X\n", A2W_PLLB_ANA_KAIP);\r
+       printf("MULTI = 0x%X\n", A2W_PLLB_ANA_MULTI);\r
+\r
+       printf("%s: ARM clock succesfully initialized!\n", __FUNCTION__);\r
+}\r
+\r
+static void arm_load_code() {\r
+       uint32_t* mem = (uint32_t*)(ARM_MEMORY_BASE);\r
+\r
+       uint8_t* start = &L_arm_code_start;\r
+       uint8_t* end = &L_arm_code_end;\r
+       uint32_t size = (uint32_t)(end - start);\r
+\r
+       bcopy(start, mem, size);\r
+\r
+       printf("%s: copied %d bytes to 0x%X!\n", __FUNCTION__, size, ARM_MEMORY_BASE);\r
+\r
+       /* verify */\r
+       for (int i = 0; i < size; i++) {\r
+               uint8_t* mem8 = (uint8_t*)(mem);\r
+               if (start[i] != mem8[i])\r
+                       panic("copy failed at 0x%X expected 0x%X, got 0x%X", (uint32_t)&mem8[i],\r
+                               *((uint32_t*)&mem8[i]),\r
+                               *((uint32_t*)&start[i]));\r
+       }\r
+}\r
+\r
+static void arm_pmap_enter(uint32_t bus_address, uint32_t arm_address) {\r
+       volatile uint32_t* tte = &ARM_TRANSLATE;\r
+       uint32_t index = arm_address >> 24;\r
+       uint32_t pte = bus_address >> 21;\r
+\r
+       tte[index] = pte; \r
+\r
+       printf("Translation: [0x%X => 0x%X] 0x%X => 0x%X\n", index * 4, bus_address >> 21, bus_address, arm_address);\r
+}\r
+\r
+/*\r
+#define ARM_C0_PRIO_PER  0x00F00000 // per priority mask\r
+#define ARM_C0_PRIO_L2   0x0F000000\r
+#define ARM_C0_PRIO_UC   0xF0000000\r
+ */\r
+\r
+void arm_init() {\r
+       printf("ARM LOADER: build date %s %s\n", __DATE__, __TIME__);\r
+\r
+       printf("%s: starting ARM initialization!\n", __FUNCTION__);\r
+\r
+       arm_load_code();\r
+\r
+       printf("%s: original memstart: 0x%X\n", __FUNCTION__, *((volatile uint32_t*)ARM_MEMORY_BASE));\r
+\r
+       for (uint32_t i = 0; i < 6; i++) {\r
+               uint32_t offset = i * 0x1000000;\r
+               arm_pmap_enter(0xC0000000 + offset, 0x0 + offset);\r
+       }\r
+\r
+       arm_pmap_enter(VC4_PERIPH_BASE, ARM_PERIPH_BASE);\r
+\r
+       /* see if the ARM block is responding */\r
+       printf("%s: ARM ID: 0x%X C0: 0x%X\n", __FUNCTION__, ARM_ID, ARM_CONTROL0);\r
+\r
+       /*\r
+        * enable peripheral access, map arm secure bits to axi secure bits 1:1 and\r
+        * set the mem size for who knows what reason.\r
+        */\r
+       ARM_CONTROL0 |= 0x000 | ARM_C0_APROTSYST | ARM_C0_SIZ1G | ARM_C0_FULLPERI;\r
+\r
+       printf("%s: using C0: 0x%X\n", __FUNCTION__, ARM_CONTROL0);\r
+\r
+       arm_enable_clock();\r
+       arm_enable_power();\r
+       /* start io bridge */\r
+       arm_setup_bridge(true);\r
+       printf("%s: polling ARM state ...\n", __FUNCTION__);\r
+\r
+       volatile uint32_t* arm_membase = (volatile uint32_t*)ARM_MEMORY_BASE;\r
+\r
+       /* skip vectors and get to comm chan */\r
+       arm_membase += 8;\r
+\r
+       for (;;/*int i = 0; i < 10; i++*/) {\r
+               if (arm_membase[3] == VPU_KILL_COMMAND) {\r
+                       panic("ARM requested VPU halt, gooodbye VPU ...");\r
+               }\r
+               printf("0x%X 0x%X 0x%X 0x%X\n", arm_membase[0], arm_membase[1], arm_membase[2], arm_membase[3]);\r
+               udelay(5000);\r
+       }\r
+}
\ No newline at end of file
diff --git a/bcm2708_chip/README.txt b/bcm2708_chip/README.txt
new file mode 100755 (executable)
index 0000000..50d048b
--- /dev/null
@@ -0,0 +1,29 @@
+This dir contains all the register map files for the design
+The bulk of it is created with the create_regs script  (run create_regs)  which
+parses the *_regs files in the hdl dirs and creates the individual files
+
+The top level file is chip/hdl/bcm2708_regs.tcl which defines the contents
+and off sets of the chip level memory map.
+
+Create regs then searches the dir tree for each object mentioned in bcm2708_regs.tcl
+and locates its   "object_regs.tcl"  file
+
+It then generates all the .h .inc ... files.
+
+These are then all lumped together in a  register_map.h  register_map.inc etc file
+
+
+
+The general procedure to modify this is
+
+
+
+check out all of chip/verification/code/vcinclude
+run create_regs  in this dir
+revert all unchanged files in  vcinclude
+check the modified ones and checkl them in if they are ok.
+
+
+Note:
+If create regs cant find a _regs.tcl file it will crash
+If it finds two files with the same name it will crash
diff --git a/bcm2708_chip/apb_arbiter_control.h b/bcm2708_chip/apb_arbiter_control.h
new file mode 100755 (executable)
index 0000000..a0f04fa
--- /dev/null
@@ -0,0 +1,7 @@
+// This file was generated by the create_regs script
+#define ACR_BASE                                                 0x7e80a000
+#define ACR_APB_ID                                               0x61726272
+#define ACR_control                                              HW_REGISTER_RW( 0x7e80a000 ) 
+   #define ACR_control_MASK                                      0x0000ffff
+   #define ACR_control_WIDTH                                     16
+   #define ACR_control_RESET                                     0000000000
diff --git a/bcm2708_chip/apb_async_bridge_ctrl.h b/bcm2708_chip/apb_async_bridge_ctrl.h
new file mode 100755 (executable)
index 0000000..339f473
--- /dev/null
@@ -0,0 +1,245 @@
+// This file was generated by the create_regs script
+#define ASB_BASE                                                 0x7e00a000
+#define ASB_APB_ID                                               0x62726467
+#define ASB_AXI_BRDG_VERSION                                     HW_REGISTER_RW( 0x7e00a000 ) 
+   #define ASB_AXI_BRDG_VERSION_MASK                             0x000000ff
+   #define ASB_AXI_BRDG_VERSION_WIDTH                            8
+   #define ASB_AXI_BRDG_VERSION_RESET                            0000000000
+#define ASB_CPR_CTRL                                             HW_REGISTER_RW( 0x7e00a004 ) 
+   #define ASB_CPR_CTRL_MASK                                     0x00ffffff
+   #define ASB_CPR_CTRL_WIDTH                                    24
+   #define ASB_CPR_CTRL_RESET                                    0x00000007
+      #define ASB_CPR_CTRL_CLR_REQ_BITS                          0:0
+      #define ASB_CPR_CTRL_CLR_REQ_SET                           0x00000001
+      #define ASB_CPR_CTRL_CLR_REQ_CLR                           0xfffffffe
+      #define ASB_CPR_CTRL_CLR_REQ_MSB                           0
+      #define ASB_CPR_CTRL_CLR_REQ_LSB                           0
+      #define ASB_CPR_CTRL_CLR_ACK_BITS                          1:1
+      #define ASB_CPR_CTRL_CLR_ACK_SET                           0x00000002
+      #define ASB_CPR_CTRL_CLR_ACK_CLR                           0xfffffffd
+      #define ASB_CPR_CTRL_CLR_ACK_MSB                           1
+      #define ASB_CPR_CTRL_CLR_ACK_LSB                           1
+      #define ASB_CPR_CTRL_EMPTY_BITS                            2:2
+      #define ASB_CPR_CTRL_EMPTY_SET                             0x00000004
+      #define ASB_CPR_CTRL_EMPTY_CLR                             0xfffffffb
+      #define ASB_CPR_CTRL_EMPTY_MSB                             2
+      #define ASB_CPR_CTRL_EMPTY_LSB                             2
+      #define ASB_CPR_CTRL_FULL_BITS                             3:3
+      #define ASB_CPR_CTRL_FULL_SET                              0x00000008
+      #define ASB_CPR_CTRL_FULL_CLR                              0xfffffff7
+      #define ASB_CPR_CTRL_FULL_MSB                              3
+      #define ASB_CPR_CTRL_FULL_LSB                              3
+      #define ASB_CPR_CTRL_RCOUNT_BITS                           13:4
+      #define ASB_CPR_CTRL_RCOUNT_SET                            0x00003ff0
+      #define ASB_CPR_CTRL_RCOUNT_CLR                            0xffffc00f
+      #define ASB_CPR_CTRL_RCOUNT_MSB                            13
+      #define ASB_CPR_CTRL_RCOUNT_LSB                            4
+      #define ASB_CPR_CTRL_WCOUNT_BITS                           23:14
+      #define ASB_CPR_CTRL_WCOUNT_SET                            0x00ffc000
+      #define ASB_CPR_CTRL_WCOUNT_CLR                            0xff003fff
+      #define ASB_CPR_CTRL_WCOUNT_MSB                            23
+      #define ASB_CPR_CTRL_WCOUNT_LSB                            14
+#define ASB_V3D_S_CTRL                                           HW_REGISTER_RW( 0x7e00a008 ) 
+   #define ASB_V3D_S_CTRL_MASK                                   0x00ffffff
+   #define ASB_V3D_S_CTRL_WIDTH                                  24
+   #define ASB_V3D_S_CTRL_RESET                                  0x00000007
+      #define ASB_V3D_S_CTRL_CLR_REQ_BITS                        0:0
+      #define ASB_V3D_S_CTRL_CLR_REQ_SET                         0x00000001
+      #define ASB_V3D_S_CTRL_CLR_REQ_CLR                         0xfffffffe
+      #define ASB_V3D_S_CTRL_CLR_REQ_MSB                         0
+      #define ASB_V3D_S_CTRL_CLR_REQ_LSB                         0
+      #define ASB_V3D_S_CTRL_CLR_ACK_BITS                        1:1
+      #define ASB_V3D_S_CTRL_CLR_ACK_SET                         0x00000002
+      #define ASB_V3D_S_CTRL_CLR_ACK_CLR                         0xfffffffd
+      #define ASB_V3D_S_CTRL_CLR_ACK_MSB                         1
+      #define ASB_V3D_S_CTRL_CLR_ACK_LSB                         1
+      #define ASB_V3D_S_CTRL_EMPTY_BITS                          2:2
+      #define ASB_V3D_S_CTRL_EMPTY_SET                           0x00000004
+      #define ASB_V3D_S_CTRL_EMPTY_CLR                           0xfffffffb
+      #define ASB_V3D_S_CTRL_EMPTY_MSB                           2
+      #define ASB_V3D_S_CTRL_EMPTY_LSB                           2
+      #define ASB_V3D_S_CTRL_FULL_BITS                           3:3
+      #define ASB_V3D_S_CTRL_FULL_SET                            0x00000008
+      #define ASB_V3D_S_CTRL_FULL_CLR                            0xfffffff7
+      #define ASB_V3D_S_CTRL_FULL_MSB                            3
+      #define ASB_V3D_S_CTRL_FULL_LSB                            3
+      #define ASB_V3D_S_CTRL_RCOUNT_BITS                         13:4
+      #define ASB_V3D_S_CTRL_RCOUNT_SET                          0x00003ff0
+      #define ASB_V3D_S_CTRL_RCOUNT_CLR                          0xffffc00f
+      #define ASB_V3D_S_CTRL_RCOUNT_MSB                          13
+      #define ASB_V3D_S_CTRL_RCOUNT_LSB                          4
+      #define ASB_V3D_S_CTRL_WCOUNT_BITS                         23:14
+      #define ASB_V3D_S_CTRL_WCOUNT_SET                          0x00ffc000
+      #define ASB_V3D_S_CTRL_WCOUNT_CLR                          0xff003fff
+      #define ASB_V3D_S_CTRL_WCOUNT_MSB                          23
+      #define ASB_V3D_S_CTRL_WCOUNT_LSB                          14
+#define ASB_V3D_M_CTRL                                           HW_REGISTER_RW( 0x7e00a00c ) 
+   #define ASB_V3D_M_CTRL_MASK                                   0x00ffffff
+   #define ASB_V3D_M_CTRL_WIDTH                                  24
+   #define ASB_V3D_M_CTRL_RESET                                  0x00000007
+      #define ASB_V3D_M_CTRL_CLR_REQ_BITS                        0:0
+      #define ASB_V3D_M_CTRL_CLR_REQ_SET                         0x00000001
+      #define ASB_V3D_M_CTRL_CLR_REQ_CLR                         0xfffffffe
+      #define ASB_V3D_M_CTRL_CLR_REQ_MSB                         0
+      #define ASB_V3D_M_CTRL_CLR_REQ_LSB                         0
+      #define ASB_V3D_M_CTRL_CLR_ACK_BITS                        1:1
+      #define ASB_V3D_M_CTRL_CLR_ACK_SET                         0x00000002
+      #define ASB_V3D_M_CTRL_CLR_ACK_CLR                         0xfffffffd
+      #define ASB_V3D_M_CTRL_CLR_ACK_MSB                         1
+      #define ASB_V3D_M_CTRL_CLR_ACK_LSB                         1
+      #define ASB_V3D_M_CTRL_EMPTY_BITS                          2:2
+      #define ASB_V3D_M_CTRL_EMPTY_SET                           0x00000004
+      #define ASB_V3D_M_CTRL_EMPTY_CLR                           0xfffffffb
+      #define ASB_V3D_M_CTRL_EMPTY_MSB                           2
+      #define ASB_V3D_M_CTRL_EMPTY_LSB                           2
+      #define ASB_V3D_M_CTRL_FULL_BITS                           3:3
+      #define ASB_V3D_M_CTRL_FULL_SET                            0x00000008
+      #define ASB_V3D_M_CTRL_FULL_CLR                            0xfffffff7
+      #define ASB_V3D_M_CTRL_FULL_MSB                            3
+      #define ASB_V3D_M_CTRL_FULL_LSB                            3
+      #define ASB_V3D_M_CTRL_RCOUNT_BITS                         13:4
+      #define ASB_V3D_M_CTRL_RCOUNT_SET                          0x00003ff0
+      #define ASB_V3D_M_CTRL_RCOUNT_CLR                          0xffffc00f
+      #define ASB_V3D_M_CTRL_RCOUNT_MSB                          13
+      #define ASB_V3D_M_CTRL_RCOUNT_LSB                          4
+      #define ASB_V3D_M_CTRL_WCOUNT_BITS                         23:14
+      #define ASB_V3D_M_CTRL_WCOUNT_SET                          0x00ffc000
+      #define ASB_V3D_M_CTRL_WCOUNT_CLR                          0xff003fff
+      #define ASB_V3D_M_CTRL_WCOUNT_MSB                          23
+      #define ASB_V3D_M_CTRL_WCOUNT_LSB                          14
+#define ASB_ISP_S_CTRL                                           HW_REGISTER_RW( 0x7e00a010 ) 
+   #define ASB_ISP_S_CTRL_MASK                                   0x00ffffff
+   #define ASB_ISP_S_CTRL_WIDTH                                  24
+   #define ASB_ISP_S_CTRL_RESET                                  0x00000007
+      #define ASB_ISP_S_CTRL_CLR_REQ_BITS                        0:0
+      #define ASB_ISP_S_CTRL_CLR_REQ_SET                         0x00000001
+      #define ASB_ISP_S_CTRL_CLR_REQ_CLR                         0xfffffffe
+      #define ASB_ISP_S_CTRL_CLR_REQ_MSB                         0
+      #define ASB_ISP_S_CTRL_CLR_REQ_LSB                         0
+      #define ASB_ISP_S_CTRL_CLR_ACK_BITS                        1:1
+      #define ASB_ISP_S_CTRL_CLR_ACK_SET                         0x00000002
+      #define ASB_ISP_S_CTRL_CLR_ACK_CLR                         0xfffffffd
+      #define ASB_ISP_S_CTRL_CLR_ACK_MSB                         1
+      #define ASB_ISP_S_CTRL_CLR_ACK_LSB                         1
+      #define ASB_ISP_S_CTRL_EMPTY_BITS                          2:2
+      #define ASB_ISP_S_CTRL_EMPTY_SET                           0x00000004
+      #define ASB_ISP_S_CTRL_EMPTY_CLR                           0xfffffffb
+      #define ASB_ISP_S_CTRL_EMPTY_MSB                           2
+      #define ASB_ISP_S_CTRL_EMPTY_LSB                           2
+      #define ASB_ISP_S_CTRL_FULL_BITS                           3:3
+      #define ASB_ISP_S_CTRL_FULL_SET                            0x00000008
+      #define ASB_ISP_S_CTRL_FULL_CLR                            0xfffffff7
+      #define ASB_ISP_S_CTRL_FULL_MSB                            3
+      #define ASB_ISP_S_CTRL_FULL_LSB                            3
+      #define ASB_ISP_S_CTRL_RCOUNT_BITS                         13:4
+      #define ASB_ISP_S_CTRL_RCOUNT_SET                          0x00003ff0
+      #define ASB_ISP_S_CTRL_RCOUNT_CLR                          0xffffc00f
+      #define ASB_ISP_S_CTRL_RCOUNT_MSB                          13
+      #define ASB_ISP_S_CTRL_RCOUNT_LSB                          4
+      #define ASB_ISP_S_CTRL_WCOUNT_BITS                         23:14
+      #define ASB_ISP_S_CTRL_WCOUNT_SET                          0x00ffc000
+      #define ASB_ISP_S_CTRL_WCOUNT_CLR                          0xff003fff
+      #define ASB_ISP_S_CTRL_WCOUNT_MSB                          23
+      #define ASB_ISP_S_CTRL_WCOUNT_LSB                          14
+#define ASB_ISP_M_CTRL                                           HW_REGISTER_RW( 0x7e00a014 ) 
+   #define ASB_ISP_M_CTRL_MASK                                   0x00ffffff
+   #define ASB_ISP_M_CTRL_WIDTH                                  24
+   #define ASB_ISP_M_CTRL_RESET                                  0x00000007
+      #define ASB_ISP_M_CTRL_CLR_REQ_BITS                        0:0
+      #define ASB_ISP_M_CTRL_CLR_REQ_SET                         0x00000001
+      #define ASB_ISP_M_CTRL_CLR_REQ_CLR                         0xfffffffe
+      #define ASB_ISP_M_CTRL_CLR_REQ_MSB                         0
+      #define ASB_ISP_M_CTRL_CLR_REQ_LSB                         0
+      #define ASB_ISP_M_CTRL_CLR_ACK_BITS                        1:1
+      #define ASB_ISP_M_CTRL_CLR_ACK_SET                         0x00000002
+      #define ASB_ISP_M_CTRL_CLR_ACK_CLR                         0xfffffffd
+      #define ASB_ISP_M_CTRL_CLR_ACK_MSB                         1
+      #define ASB_ISP_M_CTRL_CLR_ACK_LSB                         1
+      #define ASB_ISP_M_CTRL_EMPTY_BITS                          2:2
+      #define ASB_ISP_M_CTRL_EMPTY_SET                           0x00000004
+      #define ASB_ISP_M_CTRL_EMPTY_CLR                           0xfffffffb
+      #define ASB_ISP_M_CTRL_EMPTY_MSB                           2
+      #define ASB_ISP_M_CTRL_EMPTY_LSB                           2
+      #define ASB_ISP_M_CTRL_FULL_BITS                           3:3
+      #define ASB_ISP_M_CTRL_FULL_SET                            0x00000008
+      #define ASB_ISP_M_CTRL_FULL_CLR                            0xfffffff7
+      #define ASB_ISP_M_CTRL_FULL_MSB                            3
+      #define ASB_ISP_M_CTRL_FULL_LSB                            3
+      #define ASB_ISP_M_CTRL_RCOUNT_BITS                         13:4
+      #define ASB_ISP_M_CTRL_RCOUNT_SET                          0x00003ff0
+      #define ASB_ISP_M_CTRL_RCOUNT_CLR                          0xffffc00f
+      #define ASB_ISP_M_CTRL_RCOUNT_MSB                          13
+      #define ASB_ISP_M_CTRL_RCOUNT_LSB                          4
+      #define ASB_ISP_M_CTRL_WCOUNT_BITS                         23:14
+      #define ASB_ISP_M_CTRL_WCOUNT_SET                          0x00ffc000
+      #define ASB_ISP_M_CTRL_WCOUNT_CLR                          0xff003fff
+      #define ASB_ISP_M_CTRL_WCOUNT_MSB                          23
+      #define ASB_ISP_M_CTRL_WCOUNT_LSB                          14
+#define ASB_H264_S_CTRL                                          HW_REGISTER_RW( 0x7e00a018 ) 
+   #define ASB_H264_S_CTRL_MASK                                  0x00ffffff
+   #define ASB_H264_S_CTRL_WIDTH                                 24
+   #define ASB_H264_S_CTRL_RESET                                 0x00000007
+      #define ASB_H264_S_CTRL_CLR_REQ_BITS                       0:0
+      #define ASB_H264_S_CTRL_CLR_REQ_SET                        0x00000001
+      #define ASB_H264_S_CTRL_CLR_REQ_CLR                        0xfffffffe
+      #define ASB_H264_S_CTRL_CLR_REQ_MSB                        0
+      #define ASB_H264_S_CTRL_CLR_REQ_LSB                        0
+      #define ASB_H264_S_CTRL_CLR_ACK_BITS                       1:1
+      #define ASB_H264_S_CTRL_CLR_ACK_SET                        0x00000002
+      #define ASB_H264_S_CTRL_CLR_ACK_CLR                        0xfffffffd
+      #define ASB_H264_S_CTRL_CLR_ACK_MSB                        1
+      #define ASB_H264_S_CTRL_CLR_ACK_LSB                        1
+      #define ASB_H264_S_CTRL_EMPTY_BITS                         2:2
+      #define ASB_H264_S_CTRL_EMPTY_SET                          0x00000004
+      #define ASB_H264_S_CTRL_EMPTY_CLR                          0xfffffffb
+      #define ASB_H264_S_CTRL_EMPTY_MSB                          2
+      #define ASB_H264_S_CTRL_EMPTY_LSB                          2
+      #define ASB_H264_S_CTRL_FULL_BITS                          3:3
+      #define ASB_H264_S_CTRL_FULL_SET                           0x00000008
+      #define ASB_H264_S_CTRL_FULL_CLR                           0xfffffff7
+      #define ASB_H264_S_CTRL_FULL_MSB                           3
+      #define ASB_H264_S_CTRL_FULL_LSB                           3
+      #define ASB_H264_S_CTRL_RCOUNT_BITS                        13:4
+      #define ASB_H264_S_CTRL_RCOUNT_SET                         0x00003ff0
+      #define ASB_H264_S_CTRL_RCOUNT_CLR                         0xffffc00f
+      #define ASB_H264_S_CTRL_RCOUNT_MSB                         13
+      #define ASB_H264_S_CTRL_RCOUNT_LSB                         4
+      #define ASB_H264_S_CTRL_WCOUNT_BITS                        23:14
+      #define ASB_H264_S_CTRL_WCOUNT_SET                         0x00ffc000
+      #define ASB_H264_S_CTRL_WCOUNT_CLR                         0xff003fff
+      #define ASB_H264_S_CTRL_WCOUNT_MSB                         23
+      #define ASB_H264_S_CTRL_WCOUNT_LSB                         14
+#define ASB_H264_M_CTRL                                          HW_REGISTER_RW( 0x7e00a01c ) 
+   #define ASB_H264_M_CTRL_MASK                                  0x00ffffff
+   #define ASB_H264_M_CTRL_WIDTH                                 24
+   #define ASB_H264_M_CTRL_RESET                                 0x00000007
+      #define ASB_H264_M_CTRL_CLR_REQ_BITS                       0:0
+      #define ASB_H264_M_CTRL_CLR_REQ_SET                        0x00000001
+      #define ASB_H264_M_CTRL_CLR_REQ_CLR                        0xfffffffe
+      #define ASB_H264_M_CTRL_CLR_REQ_MSB                        0
+      #define ASB_H264_M_CTRL_CLR_REQ_LSB                        0
+      #define ASB_H264_M_CTRL_CLR_ACK_BITS                       1:1
+      #define ASB_H264_M_CTRL_CLR_ACK_SET                        0x00000002
+      #define ASB_H264_M_CTRL_CLR_ACK_CLR                        0xfffffffd
+      #define ASB_H264_M_CTRL_CLR_ACK_MSB                        1
+      #define ASB_H264_M_CTRL_CLR_ACK_LSB                        1
+      #define ASB_H264_M_CTRL_EMPTY_BITS                         2:2
+      #define ASB_H264_M_CTRL_EMPTY_SET                          0x00000004
+      #define ASB_H264_M_CTRL_EMPTY_CLR                          0xfffffffb
+      #define ASB_H264_M_CTRL_EMPTY_MSB                          2
+      #define ASB_H264_M_CTRL_EMPTY_LSB                          2
+      #define ASB_H264_M_CTRL_FULL_BITS                          3:3
+      #define ASB_H264_M_CTRL_FULL_SET                           0x00000008
+      #define ASB_H264_M_CTRL_FULL_CLR                           0xfffffff7
+      #define ASB_H264_M_CTRL_FULL_MSB                           3
+      #define ASB_H264_M_CTRL_FULL_LSB                           3
+      #define ASB_H264_M_CTRL_RCOUNT_BITS                        13:4
+      #define ASB_H264_M_CTRL_RCOUNT_SET                         0x00003ff0
+      #define ASB_H264_M_CTRL_RCOUNT_CLR                         0xffffc00f
+      #define ASB_H264_M_CTRL_RCOUNT_MSB                         13
+      #define ASB_H264_M_CTRL_RCOUNT_LSB                         4
+      #define ASB_H264_M_CTRL_WCOUNT_BITS                        23:14
+      #define ASB_H264_M_CTRL_WCOUNT_SET                         0x00ffc000
+      #define ASB_H264_M_CTRL_WCOUNT_CLR                         0xff003fff
+      #define ASB_H264_M_CTRL_WCOUNT_MSB                         23
+      #define ASB_H264_M_CTRL_WCOUNT_LSB                         14
diff --git a/bcm2708_chip/arm_control.h b/bcm2708_chip/arm_control.h
new file mode 100755 (executable)
index 0000000..8d249dc
--- /dev/null
@@ -0,0 +1,404 @@
+//
+// Definitions and addresses forthe ARM CONTROL logic
+// This file is manually generated.
+//
+//
+
+#define ARM_BASE  0x7E00B000
+
+// Basic configuration
+#define ARM_CONTROL0  HW_REGISTER_RW(ARM_BASE+0x000)
+#define ARM_C0_SIZ128M   0x00000000
+#define ARM_C0_SIZ256M   0x00000001
+#define ARM_C0_SIZ512M   0x00000002
+#define ARM_C0_SIZ1G     0x00000003
+#define ARM_C0_BRESP0    0x00000000
+#define ARM_C0_BRESP1    0x00000004
+#define ARM_C0_BRESP2    0x00000008
+#define ARM_C0_BOOTHI    0x00000010
+#define ARM_C0_UNUSED05  0x00000020 // free
+#define ARM_C0_FULLPERI  0x00000040
+#define ARM_C0_UNUSED78  0x00000180 // free
+#define ARM_C0_JTAGMASK  0x00000E00
+#define ARM_C0_JTAGOFF   0x00000000
+#define ARM_C0_JTAGBASH  0x00000800 // Debug on GPIO off
+#define ARM_C0_JTAGGPIO  0x00000C00 // Debug on GPIO on
+#define ARM_C0_APROTMSK  0x0000F000
+#define ARM_C0_DBG0SYNC  0x00010000 // VPU0 halt sync
+#define ARM_C0_DBG1SYNC  0x00020000 // VPU1 halt sync
+#define ARM_C0_SWDBGREQ  0x00040000 // HW debug request
+#define ARM_C0_PASSHALT  0x00080000 // ARM halt passed to debugger
+#define ARM_C0_PRIO_PER  0x00F00000 // per priority mask
+#define ARM_C0_PRIO_L2   0x0F000000
+#define ARM_C0_PRIO_UC   0xF0000000
+
+#define ARM_C0_APROTPASS  0x0000A000 // Translate 1:1
+#define ARM_C0_APROTUSER  0x00000000 // Only user mode
+#define ARM_C0_APROTSYST  0x0000F000 // Only system mode
+
+
+#define ARM_CONTROL1  HW_REGISTER_RW(ARM_BASE+0x440)
+#define ARM_C1_TIMER     0x00000001 // re-route timer IRQ  to VC
+#define ARM_C1_MAIL      0x00000002 // re-route Mail IRQ   to VC
+#define ARM_C1_BELL0     0x00000004 // re-route Doorbell 0 to VC
+#define ARM_C1_BELL1     0x00000008 // re-route Doorbell 1 to VC
+#define ARM_C1_PERSON    0x00000100 // peripherals on
+#define ARM_C1_REQSTOP   0x00000200 // ASYNC bridge request stop
+
+#define ARM_STATUS    HW_REGISTER_RW(ARM_BASE+0x444)
+#define ARM_S_ACKSTOP    0x80000000 // Bridge stopped
+#define ARM_S_READPEND   0x000003FF // pending reads counter
+#define ARM_S_WRITPEND   0x000FFC00 // pending writes counter
+
+#define ARM_ERRHALT   HW_REGISTER_RW(ARM_BASE+0x448)
+#define ARM_EH_PERIBURST  0x00000001 // Burst write seen on peri bus
+#define ARM_EH_ILLADDRS1  0x00000002 // Address bits 25-27 error
+#define ARM_EH_ILLADDRS2  0x00000004 // Address bits 31-28 error
+#define ARM_EH_VPU0HALT   0x00000008 // VPU0 halted & in debug mode
+#define ARM_EH_VPU1HALT   0x00000010 // VPU1 halted & in debug mode
+#define ARM_EH_ARMHALT    0x00000020 // ARM in halted debug mode
+
+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
+#define ARM_ID        HW_REGISTER_RW(ARM_BASE+0x44C)
+#define ARM_IDVAL        0x364D5241
+
+// Translation memory
+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
+// 32 locations: 0x100.. 0x17F
+// 32 spare means we CAN go to 64 pages....
+
+
+// Interrupts
+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200)        // Top IRQ bits
+#define ARM_I0_TIMER    0x00000001 // timer IRQ
+#define ARM_I0_MAIL     0x00000002 // Mail IRQ
+#define ARM_I0_BELL0    0x00000004 // Doorbell 0
+#define ARM_I0_BELL1    0x00000008 // Doorbell 1
+#define ARM_I0_BANK1    0x00000100 // Bank1 IRQ
+#define ARM_I0_BANK2    0x00000200 // Bank2 IRQ
+
+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) // All bank1 IRQ bits
+// todo: all I1_interrupt sources
+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) // All bank2 IRQ bits
+// todo: all I2_interrupt sources
+
+#define ARM_IRQ_FAST  HW_REGISTER_RW(ARM_BASE+0x20C) // FIQ control
+#define ARM_IF_INDEX    0x0000007F     // FIQ select
+#define ARM_IF_ENABLE   0x00000080     // FIQ enable
+#define ARM_IF_VCMASK   0x0000003F     // FIQ = (index from VC source)
+#define ARM_IF_TIMER    0x00000040     // FIQ = ARM timer
+#define ARM_IF_MAIL     0x00000041     // FIQ = ARM Mail
+#define ARM_IF_BELL0    0x00000042     // FIQ = ARM Doorbell 0
+#define ARM_IF_BELL1    0x00000043     // FIQ = ARM Doorbell 1
+#define ARM_IF_VP0HALT  0x00000044     // FIQ = VPU0 Halt seen
+#define ARM_IF_VP1HALT  0x00000045     // FIQ = VPU1 Halt seen
+#define ARM_IF_ILLEGAL  0x00000046     // FIQ = Illegal access seen
+
+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) // Bank1 enable bits
+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) // Bank2 enable bits
+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) // ARM irqs enable bits
+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) // Bank1 disable bits
+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) // Bank2 disable bits
+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) // ARM irqs disable bits
+#define ARM_IE_TIMER    0x00000001     // Timer IRQ
+#define ARM_IE_MAIL     0x00000002     // Mail IRQ
+#define ARM_IE_BELL0    0x00000004     // Doorbell 0
+#define ARM_IE_BELL1    0x00000008     // Doorbell 1
+#define ARM_IE_VP0HALT  0x00000010     // VPU0 Halt
+#define ARM_IE_VP1HALT  0x00000020     // VPU1 Halt
+#define ARM_IE_ILLEGAL  0x00000040     // Illegal access seen
+
+// Timer
+// For reg. fields see sp804 spec.
+#define ARM_T_LOAD    HW_REGISTER_RW(ARM_BASE+0x400)
+#define ARM_T_VALUE   HW_REGISTER_RW(ARM_BASE+0x404)
+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
+#define ARM_T_RAWIRQ  HW_REGISTER_RW(ARM_BASE+0x410)
+#define ARM_T_MSKIRQ  HW_REGISTER_RW(ARM_BASE+0x414)
+#define ARM_T_RELOAD  HW_REGISTER_RW(ARM_BASE+0x418)
+#define ARM_T_PREDIV  HW_REGISTER_RW(ARM_BASE+0x41c)
+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
+
+#define TIMER_CTRL_ONESHOT  (1 << 0)
+#define TIMER_CTRL_32BIT    (1 << 1)
+#define TIMER_CTRL_DIV1     (0 << 2)
+#define TIMER_CTRL_DIV16    (1 << 2)
+#define TIMER_CTRL_DIV256   (2 << 2)
+#define TIMER_CTRL_IE       (1 << 5)
+#define TIMER_CTRL_PERIODIC (1 << 6)
+#define TIMER_CTRL_ENABLE   (1 << 7)
+#define TIMER_CTRL_DBGHALT  (1 << 8)
+#define TIMER_CTRL_ENAFREE  (1 << 9)
+#define TIMER_CTRL_FREEDIV_SHIFT 16)
+#define TIMER_CTRL_FREEDIV_MASK  0xff
+
+//
+// Semaphores, Doorbells, Mailboxes
+#define ARM_SBM_OWN0  (ARM_BASE+0x800)
+#define ARM_SBM_OWN1  (ARM_BASE+0x900)
+#define ARM_SBM_OWN2  (ARM_BASE+0xA00)
+#define ARM_SBM_OWN3  (ARM_BASE+0xB00)
+
+//
+// MAILBOXES
+// Register flags are common across all
+// owner registers. See end of this section
+//=========================================
+// Semaphores, Doorbells, Mailboxes Owner 0
+//=========================================
+#define ARM_0_SEMS       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
+#define ARM_0_SEM0       HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
+#define ARM_0_SEM1       HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
+#define ARM_0_SEM2       HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
+#define ARM_0_SEM3       HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
+#define ARM_0_SEM4       HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
+#define ARM_0_SEM5       HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
+#define ARM_0_SEM6       HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
+#define ARM_0_SEM7       HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
+#define ARM_0_BELL0      HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
+#define ARM_0_BELL1      HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
+#define ARM_0_BELL2      HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
+#define ARM_0_BELL3      HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
+// MAILBOX 0 access in Owner 0 area
+// Some addresses should ONLY be used by owner 0
+#define ARM_0_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  // .. 0x8C (4 locations)
+#define ARM_0_MAIL0_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0x80)  // .. 0x8C (4 locations) Normal read
+#define ARM_0_MAIL0_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0x90)  // none-pop read
+#define ARM_0_MAIL0_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0x94)  // Sender read (only LS 2 bits)
+#define ARM_0_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0x98)  // Status read
+#define ARM_0_MAIL0_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0x9C)  // Config read/write
+// MAILBOX 1 access in Owner 0 area
+// Owner 0 should only WRITE to this mailbox
+#define ARM_0_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN0+0xA0)   // .. 0xAC (4 locations)
+//#define ARM_0_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) // DO NOT USE THIS !!!!!
+//#define ARM_0_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) // DO NOT USE THIS !!!!!
+//#define ARM_0_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) // DO NOT USE THIS !!!!!
+#define ARM_0_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN0+0xB8)   // Status read
+//#define ARM_0_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) // DO NOT USE THIS !!!!!
+// General SEM, BELL, MAIL config/status
+#define ARM_0_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN0+0xE0)  // semaphore clear/debug register
+#define ARM_0_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN0+0xE4)  // Doorbells clear/debug register
+#define ARM_0_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN0+0xF8)  // ALL interrupts
+#define ARM_0_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN0+0xFC)  // IRQS pending for owner 0
+
+// Semaphores, Doorbells, Mailboxes Owner 1
+//=========================================
+#define ARM_1_SEMS       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
+#define ARM_1_SEM0       HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
+#define ARM_1_SEM1       HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
+#define ARM_1_SEM2       HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
+#define ARM_1_SEM3       HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
+#define ARM_1_SEM4       HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
+#define ARM_1_SEM5       HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
+#define ARM_1_SEM6       HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
+#define ARM_1_SEM7       HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
+#define ARM_1_BELL0      HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
+#define ARM_1_BELL1      HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
+#define ARM_1_BELL2      HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
+#define ARM_1_BELL3      HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
+// MAILBOX 0 access in Owner 0 area
+// Owner 1 should only WRITE to this mailbox
+#define ARM_1_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0x80)  // .. 0x8C (4 locations)
+//#define ARM_1_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN1+0x80) // DO NOT USE THIS !!!!!
+//#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) // DO NOT USE THIS !!!!!
+//#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) // DO NOT USE THIS !!!!!
+#define ARM_1_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0x98)  // Status read
+//#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) // DO NOT USE THIS !!!!!
+// MAILBOX 1 access in Owner 0 area
+#define ARM_1_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  // .. 0xAC (4 locations)
+#define ARM_1_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN1+0xA0)  // .. 0xAC (4 locations) Normal read
+#define ARM_1_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN1+0xB0)  // none-pop read
+#define ARM_1_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN1+0xB4)  // Sender read (only LS 2 bits)
+#define ARM_1_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN1+0xB8)  // Status read
+#define ARM_1_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
+// General SEM, BELL, MAIL config/status
+#define ARM_1_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN1+0xE0)  // semaphore clear/debug register
+#define ARM_1_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN1+0xE4)  // Doorbells clear/debug register
+#define ARM_1_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN1+0xFC)  // IRQS pending for owner 1
+#define ARM_1_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN1+0xF8)  // ALL interrupts
+
+// Semaphores, Doorbells, Mailboxes Owner 2
+//=========================================
+#define ARM_2_SEMS       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
+#define ARM_2_SEM0       HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
+#define ARM_2_SEM1       HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
+#define ARM_2_SEM2       HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
+#define ARM_2_SEM3       HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
+#define ARM_2_SEM4       HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
+#define ARM_2_SEM5       HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
+#define ARM_2_SEM6       HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
+#define ARM_2_SEM7       HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
+#define ARM_2_BELL0      HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
+#define ARM_2_BELL1      HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
+#define ARM_2_BELL2      HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
+#define ARM_2_BELL3      HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
+// MAILBOX 0 access in Owner 2 area
+// Owner 2 should only WRITE to this mailbox
+#define ARM_2_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)   // .. 0x8C (4 locations)
+//#define ARM_2_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN2+0x80)  // DO NOT USE THIS !!!!!
+//#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90)  // DO NOT USE THIS !!!!!
+//#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94)  // DO NOT USE THIS !!!!!
+#define ARM_2_MAIL0_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0x98)   // Status read
+//#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C)  // DO NOT USE THIS !!!!!
+// MAILBOX 1 access in Owner 2 area
+// Owner 2 should only WRITE to this mailbox
+#define ARM_2_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN2+0xA0)   // .. 0xAC (4 locations)
+//#define ARM_2_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) // DO NOT USE THIS !!!!!
+//#define ARM_2_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) // DO NOT USE THIS !!!!!
+//#define ARM_2_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) // DO NOT USE THIS !!!!!
+#define ARM_2_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN2+0xB8)   // Status read
+//#define ARM_2_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) // DO NOT USE THIS !!!!!
+// General SEM, BELL, MAIL config/status
+#define ARM_2_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN2+0xE0)  // semaphore clear/debug register
+#define ARM_2_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN2+0xE4)  // Doorbells clear/debug register
+#define ARM_2_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN2+0xFC)  // IRQS pending for owner 2
+#define ARM_2_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN2+0xF8)  // ALL interrupts
+
+// Semaphores, Doorbells, Mailboxes Owner 3
+//=========================================
+#define ARM_3_SEMS       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
+#define ARM_3_SEM0       HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
+#define ARM_3_SEM1       HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
+#define ARM_3_SEM2       HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
+#define ARM_3_SEM3       HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
+#define ARM_3_SEM4       HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
+#define ARM_3_SEM5       HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
+#define ARM_3_SEM6       HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
+#define ARM_3_SEM7       HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
+#define ARM_3_BELL0      HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
+#define ARM_3_BELL1      HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
+#define ARM_3_BELL2      HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
+#define ARM_3_BELL3      HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
+// MAILBOX 0 access in Owner 3 area
+// Owner 3 should only WRITE to this mailbox
+#define ARM_3_MAIL0_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)   // .. 0x8C (4 locations)
+//#define ARM_3_MAIL0_RD  HW_REGISTER_RW(ARM_SBM_OWN3+0x80)  // DO NOT USE THIS !!!!!
+//#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90)  // DO NOT USE THIS !!!!!
+//#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94)  // DO NOT USE THIS !!!!!
+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98)    // Status read
+//#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C)  // DO NOT USE THIS !!!!!
+// MAILBOX 1 access in Owner 3 area
+// Owner 3 should only WRITE to this mailbox
+#define ARM_3_MAIL1_WRT  HW_REGISTER_RW(ARM_SBM_OWN3+0xA0)   // .. 0xAC (4 locations)
+//#define ARM_3_MAIL1_RD   HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) // DO NOT USE THIS !!!!!
+//#define ARM_3_MAIL1_POL  HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) // DO NOT USE THIS !!!!!
+//#define ARM_3_MAIL1_SND  HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) // DO NOT USE THIS !!!!!
+#define ARM_3_MAIL1_STA  HW_REGISTER_RW(ARM_SBM_OWN3+0xB8)   // Status read
+//#define ARM_3_MAIL1_CNF  HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) // DO NOT USE THIS !!!!!
+// General SEM, BELL, MAIL config/status
+#define ARM_3_SEMCLRDBG   HW_REGISTER_RW(ARM_SBM_OWN3+0xE0)  // semaphore clear/debug register
+#define ARM_3_BELLCLRDBG  HW_REGISTER_RW(ARM_SBM_OWN3+0xE4)  // Doorbells clear/debug register
+#define ARM_3_MY_IRQS     HW_REGISTER_RW(ARM_SBM_OWN3+0xFC)  // IRQS pending for owner 3
+#define ARM_3_ALL_IRQS    HW_REGISTER_RW(ARM_SBM_OWN3+0xF8)  // ALL interrupts
+
+
+
+///////////////////////////////////////////
+//  MAILBOX FLAGS. VALID FOR ALL OWNERS  //
+///////////////////////////////////////////
+
+// MAILBOX status register (...0x98)
+#define ARM_MS_FULL       0x80000000
+#define ARM_MS_EMPTY      0x40000000
+#define ARM_MS_LEVEL      0x400000FF // Max. value depdnds on mailbox depth parameter
+
+// MAILBOX config/status register (...0x9C)
+// ANY write to this register clears the error bits!
+#define ARM_MC_IHAVEDATAIRQEN    0x00000001 // mailbox irq enable:  has data
+#define ARM_MC_IHAVESPACEIRQEN   0x00000002 // mailbox irq enable:  has space
+#define ARM_MC_OPPISEMPTYIRQEN   0x00000004 // mailbox irq enable: Opp. is empty
+#define ARM_MC_MAIL_CLEAR        0x00000008 // mailbox clear write 1, then  0
+#define ARM_MC_IHAVEDATAIRQPEND  0x00000010 // mailbox irq pending:  has space
+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 // mailbox irq pending: Opp. is empty
+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 // mailbox irq pending
+// Bit 7 is unused
+#define ARM_MC_ERRNOOWN   0x00000100 // error : none owner read from mailbox
+#define ARM_MC_ERROVERFLW 0x00000200 // error : write to fill mailbox
+#define ARM_MC_ERRUNDRFLW 0x00000400 // error : read from empty mailbox
+
+// Semaphore clear/debug register (...0xE0)
+#define ARM_SD_OWN0      0x00000003  // Owner of sem 0
+#define ARM_SD_OWN1      0x0000000C  // Owner of sem 1
+#define ARM_SD_OWN2      0x00000030  // Owner of sem 2
+#define ARM_SD_OWN3      0x000000C0  // Owner of sem 3
+#define ARM_SD_OWN4      0x00000300  // Owner of sem 4
+#define ARM_SD_OWN5      0x00000C00  // Owner of sem 5
+#define ARM_SD_OWN6      0x00003000  // Owner of sem 6
+#define ARM_SD_OWN7      0x0000C000  // Owner of sem 7
+#define ARM_SD_SEM0      0x00010000  // Status of sem 0
+#define ARM_SD_SEM1      0x00020000  // Status of sem 1
+#define ARM_SD_SEM2      0x00040000  // Status of sem 2
+#define ARM_SD_SEM3      0x00080000  // Status of sem 3
+#define ARM_SD_SEM4      0x00100000  // Status of sem 4
+#define ARM_SD_SEM5      0x00200000  // Status of sem 5
+#define ARM_SD_SEM6      0x00400000  // Status of sem 6
+#define ARM_SD_SEM7      0x00800000  // Status of sem 7
+
+// Doorbell status registers (...0x40-4C)
+#define ARM_DS_ACTIVE    0x00000004  // Doorbell rung since last read?
+#define ARM_DS_OWNER     0x00000003  // Owner
+
+// Doorbells clear/debug register (...0xE4)
+#define ARM_BD_OWN0      0x00000003  // Owner of doorbell 0
+#define ARM_BD_OWN1      0x0000000C  // Owner of doorbell 1
+#define ARM_BD_OWN2      0x00000030  // Owner of doorbell 2
+#define ARM_BD_OWN3      0x000000C0  // Owner of doorbell 3
+#define ARM_BD_BELL0     0x00000100  // Status of doorbell 0
+#define ARM_BD_BELL1     0x00000200  // Status of doorbell 1
+#define ARM_BD_BELL2     0x00000400  // Status of doorbell 2
+#define ARM_BD_BELL3     0x00000800  // Status of doorbell 3
+
+// MY IRQS register (...0xF8)
+#define ARM_MYIRQ_BELL   0x00000001  // This owner has a doorbell IRQ
+#define ARM_MYIRQ_MAIL   0x00000002  // This owner has a mailbox  IRQ
+
+// ALL IRQS register (...0xF8)
+#define ARM_AIS_BELL0 0x00000001  // Doorbell 0 IRQ pending
+#define ARM_AIS_BELL1 0x00000002  // Doorbell 1 IRQ pending
+#define ARM_AIS_BELL2 0x00000004  // Doorbell 2 IRQ pending
+#define ARM_AIS_BELL3 0x00000008  // Doorbell 3 IRQ pending
+#define ARM_AIS0_HAVEDATA 0x00000010  // MAIL 0 has data IRQ pending
+#define ARM_AIS0_HAVESPAC 0x00000020  // MAIL 0 has space IRQ pending
+#define ARM_AIS0_OPPEMPTY 0x00000040  // MAIL 0 opposite is empty IRQ
+#define ARM_AIS1_HAVEDATA 0x00000080  // MAIL 1 has data IRQ pending
+#define ARM_AIS1_HAVESPAC 0x00000100  // MAIL 1 has space IRQ pending
+#define ARM_AIS1_OPPEMPTY 0x00000200  // MAIL 1 opposite is empty IRQ
+// Note   that bell-0, bell-1 and MAIL0 IRQ go only to the ARM
+// Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC
+//
+// ARM JTAG BASH
+//
+#define AJB_BASE 0x7e2000c0
+
+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
+#define   AJB_BITS0    0x000000
+#define   AJB_BITS4    0x000004
+#define   AJB_BITS8    0x000008
+#define   AJB_BITS12   0x00000C
+#define   AJB_BITS16   0x000010
+#define   AJB_BITS20   0x000014
+#define   AJB_BITS24   0x000018
+#define   AJB_BITS28   0x00001C
+#define   AJB_BITS32   0x000020
+#define   AJB_BITS34   0x000022
+#define   AJB_OUT_MS   0x000040
+#define   AJB_OUT_LS   0x000000
+#define   AJB_INV_CLK  0x000080
+#define   AJB_D0_RISE  0x000100
+#define   AJB_D0_FALL  0x000000
+#define   AJB_D1_RISE  0x000200
+#define   AJB_D1_FALL  0x000000
+#define   AJB_IN_RISE  0x000400
+#define   AJB_IN_FALL  0x000000
+#define   AJB_ENABLE   0x000800
+#define   AJB_HOLD0    0x000000
+#define   AJB_HOLD1    0x001000
+#define   AJB_HOLD2    0x002000
+#define   AJB_HOLD3    0x003000
+#define   AJB_RESETN   0x004000
+#define   AJB_CLKSHFT  16
+#define   AJB_BUSY     0x80000000
+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
diff --git a/bcm2708_chip/aux_io.h b/bcm2708_chip/aux_io.h
new file mode 100755 (executable)
index 0000000..ff4fe9a
--- /dev/null
@@ -0,0 +1,170 @@
+//
+// Auxiliary I/O header file
+//
+
+#define AUX_IO_BASE               0x7E215000
+#define AUX_IRQ                   (AUX_IO_BASE+0x000)
+#define AUX_ENABLES               (AUX_IO_BASE+0x004)
+#define    AUX_ENABLE_MINIUART    0x01
+#define    AUX_ENABLE_SPI0        0x02
+#define    AUX_ENABLE_SPI1        0x04
+
+
+//
+// Micro UART
+//
+// Baud rate = sysclk/(8*(BAUD_REG+1))
+
+#define AUX_MU_IO_REG             (AUX_IO_BASE+0x040) // Write=TX read=RX
+#define AUX_MU_BDLS_REG           (AUX_IO_BASE+0x040) // Baudrate LS
+#define AUX_MU_BDMS_REG           (AUX_IO_BASE+0x044) // Baudrate MS.
+
+#define AUX_MU_IER_REG            (AUX_IO_BASE+0x044) // IRQ enbl. reg.
+#define    AUX_MU_IER_RXIRQEN     0x01  //
+#define    AUX_MU_IER_TXIRQEN     0x02  //
+// Line interrupts are not supported
+
+#define AUX_MU_IIR_REG            (AUX_IO_BASE+0x048) // IRQ status reg
+#define    AUX_MU_IIR_NOIRQS      0x01  // No irq pending
+#define    AUX_MU_IIR_IRQ         0x06  // 10 = rec irq, 01 = tx irq
+// Timeout is not supported
+
+#define AUX_MU_FCR_REG            (AUX_IO_BASE+0x048) // FIFO control reg
+#define    AUX_MU_FCR_RXCLR       0x02  // Flush receive FF
+#define    AUX_MU_FCR_TXCLR       0x04  // Flush transmit fifo
+
+
+#define AUX_MU_LCR_REG            (AUX_IO_BASE+0x04C) // Line control reg.
+#define    AUX_MU_LCR_7BITS       0x02 // 7 bits mode
+#define    AUX_MU_LCR_8BITS       0x03 // 8 bits mode
+#define    AUX_MU_LCR_BREAK       0x40 // send break
+#define    AUX_MU_LCR_DLAB        0x80 // DLAB access
+// 5 & 6 bits are not supported
+// 2 stop bits are not supported
+// Parity bits are not supported
+
+#define AUX_MU_MCR_REG            (AUX_IO_BASE+0x050) // Modem control reg.
+#define    AUX_MU_MCR_RTS         0x02 // Set RTS high
+// DTR is not supported
+// Out1/2 are not supported
+// Loopback is not supported
+
+#define AUX_MU_LSR_REG            (AUX_IO_BASE+0x054) // Line status reg.
+#define    AUX_MU_LSR_DR          0x01 // Receive Data ready
+#define    AUX_MU_LSR_OE          0x02 // Receiver overrun error
+#define    AUX_MU_LSR_THRE        0x20 // Transmitter holding register
+#define    AUX_MU_LSR_TEMT        0x40 // Transmitter empty
+// Parity bits (and thus errors) are not supported
+// Framing errors are not detected
+// Break detect is not (yet) supported
+
+#define AUX_MU_MSR_REG            (AUX_IO_BASE+0x058) // Modem status reg.
+#define    AUX_MU_MSR_CTS         0x10
+// Delta CTS not supported
+// DCE,DCD not supportred
+
+#define AUX_MU_SCRATCH            (AUX_IO_BASE+0x05C) // Scratch reg.
+
+// None 16550 features
+#define AUX_MU_CNTL_REG           (AUX_IO_BASE+0x060) // AUX control reg.
+#define    AUX_MU_CNTL_REC_ENBL   0x01 // receiver enable
+#define    AUX_MU_CNTL_TRN_ENBL   0x02 // transmitter enable
+#define    AUX_MU_CNTL_AUTO_RTR   0x04 // RTR set by RX FF level
+#define    AUX_MU_CNTL_AUTO_CTS   0x08 // CTS auto stops transmitter
+#define    AUX_MU_CNTL_FLOW3      0x00 // Stop on RX FF 3 entries left
+#define    AUX_MU_CNTL_FLOW2      0x10 // Stop on RX FF 2 entries left
+#define    AUX_MU_CNTL_FLOW1      0x20 // Stop on RX FF 1 entries left
+#define    AUX_MU_CNTL_FLOW4      0x30 // Stop on RX FF 4 entries left
+#define    AUX_MU_CNTL_AURTRINV   0x40 // Invert AUTO RTR polarity
+#define    AUX_MU_CNTL_AUCTSINV   0x80 // Invert AUTO CTS polarity
+
+
+#define AUX_MU_STAT_REG           (AUX_IO_BASE+0x064) // AUX status reg.
+#define    AUX_MU_STAT_RX_DATA    0x00000001 // RX FF has value
+#define    AUX_MU_STAT_TX_SPACE   0x00000002 // TX FF has space (not full)
+#define    AUX_MU_STAT_RX_IDLE    0x00000004 // Receiver is idle
+#define    AUX_MU_STAT_TX_IDLE    0x00000008 // Transmitter is idle
+#define    AUX_MU_STAT_RX_OFLW    0x00000010 // Receiver FF overflow error
+#define    AUX_MU_STAT_TX_FULL    0x00000020 // Transmit FF full
+#define    AUX_MU_STAT_RTR        0x00000040 // Status of the RTR line
+#define    AUX_MU_STAT_CTS        0x00000080 // Status of the CTS line (fully synced)
+#define    AUX_MU_STAT_TXEMPTY    0x00000100 // TX FF is empty
+#define    AUX_MU_STAT_TXDONE     0x00000200  // TX FF is empty and TX is idle
+#define    AUX_MU_STAT_RXFILL     0x00FF0000 // RX FF fill level
+#define    AUX_MU_STAT_TXFILL     0xFF000000 // TX FF fill level
+
+#define AUX_MU_BAUD_REG           (AUX_IO_BASE+0x068) // Baudrate reg (16 bits)
+                                             // Baud rate = sysclk/(8*(BAUD_REG+1))
+
+//
+// SPI 0 (SPI1 in the device!)
+//
+#define AUX_SPI0_CNTL0_REG        (AUX_IO_BASE+0x080) // control reg 0
+#define   AUX_SPI_CNTL0_BITS      0x0000003F // Number of bits to send/receive
+#define   AUX_SPI_CNTL0_OUTMS     0x00000040 // Shift MS bit out first)
+#define   AUX_SPI_CNTL0_INVCLK    0x00000080 // Invert SPI_CLK
+#define   AUX_SPI_CNTL0_OUTRISE   0x00000100 // data out leaves on rising clock edge
+#define   AUX_SPI_CNTL0_OUTFALL   0x00000000 // data out leaves on falling clock edge
+#define   AUX_SPI_CNTL0_FFCLR     0x00000200 // Reset fifos (Set and clear bit)
+#define   AUX_SPI_CNTL0_INRISE    0x00000400 // data in on rising clock edge
+#define   AUX_SPI_CNTL0_INFALL    0x00000000 // data in on falling clock edge
+#define   AUX_SPI_CNTL0_SERENBL   0x00000800 // Serial enable (does not disable FFs)
+#define   AUX_SPI_CNTL0_HOLD0     0x00000000 // Dout hold 0 sys clock cycles
+#define   AUX_SPI_CNTL0_HOLD4     0x00001000 // Dout hold 4 sys clock cycle
+#define   AUX_SPI_CNTL0_HOLD7     0x00002000 // Dout hold 7 sys clock cycles
+#define   AUX_SPI_CNTL0_HOLD10    0x00003000 // Dout hold 10 sys clock cycles
+#define   AUX_SPI_CNTL0_VARWID    0x00004000 // Variable width mode (din[15-12]=bits)
+#define   AUX_SPI_CNTL0_CSFROMFF  0x00008000 // CS pattern comesfrom MS 3 TX FIFO bits
+#define   AUX_SPI_CNTL0_POSTIN    0x00010000 // Load last bit after cycles finished
+#define   AUX_SPI_CNTL0_CS_HIGH   0x000E0000 // All CS are high
+#define   AUX_SPI_CNTL0_CS0_N     0x000C0000 // CS 0 low
+#define   AUX_SPI_CNTL0_CS1_N     0x000A0000 // CS 1 low
+#define   AUX_SPI_CNTL0_CS2_N     0x00060000 // CS 2 low
+#define   AUX_SPI_CNTL0_CSA_N     0x00000000 // ALL CS low (test only)
+#define   AUX_SPI_CNTL0_SPEED     0xFFF00000 // SPI clock = sysclock/(2xspeed)
+#define   AUX_SPI_CNTL0_SPEEDSHFT 20         // Speed shift left value
+
+#define AUX_SPI0_CNTL1_REG        (AUX_IO_BASE+0x084) // control reg 1
+#define   AUX_SPI_CNTL1_HOLDIN    0x00000001 // Do not clear DIN register at start
+#define   AUX_SPI_CNTL1_INMS      0x00000002 // Shift data in MS first MS--->LS
+//#define   AUX_SPI_CNTL1_CS_NOW    0x00000004 // Assert CS pattern now
+#define   AUX_SPI_CNTL1_EMPTYIRQ  0x00000040 // IRQ on TX Fifo empty
+#define   AUX_SPI_CNTL1_DONEIRQ   0x00000080 // IRQ on IDLE AND TxFifo empty
+#define   AUX_SPI_CNTL1_CSPLUS1   0x00000100 // CS HI plus 1 bit
+#define   AUX_SPI_CNTL1_CSPLUS2   0x00000200 // CS HI plus 2 bit
+#define   AUX_SPI_CNTL1_CSPLUS3   0x00000300 // CS HI plus 3 bit
+#define   AUX_SPI_CNTL1_CSPLUS4   0x00000400 // CS HI plus 4 bit
+#define   AUX_SPI_CNTL1_CSPLUS5   0x00000500 // CS HI plus 5 bit
+#define   AUX_SPI_CNTL1_CSPLUS6   0x00000600 // CS HI plus 6 bit
+#define   AUX_SPI_CNTL1_CSPLUS7   0x00000700 // CS HI plus 7 bit
+
+#define AUX_SPI0_STAT_REG         (AUX_IO_BASE+0x088) // Status reg.
+#define    AUX_SPI_STAT_BITCNT    0x0000003F // Bits remaining to be shifted out
+#define    AUX_SPI_STAT_BUSY      0x00000040 // FSM is busy
+#define    AUX_SPI_STAT_RXEMPTY   0x00000080 // RX FF is empty
+#define    AUX_SPI_STAT_RXFULL    0x00000100 // RX FF is full
+#define    AUX_SPI_STAT_TXEMPTY   0x00000200 // TX FF is empyt
+#define    AUX_SPI_STAT_TXFULL    0x00000400 // TX FF is full
+#define    AUX_SPI_STAT_RXFILL    0x000F0000 // RX FF fill level
+#define    AUX_SPI_STAT_TXFILL    0x0F000000 // TX FF fill level
+#define AUX_SPI0_PEEK_REG         (AUX_IO_BASE+0x08C) // Read but do not take from FF
+#define AUX_SPI0_IO_REG           (AUX_IO_BASE+0x0A0) // Write = TX, read=RX
+#define AUX_SPI0_TXHOLD_REG       (AUX_IO_BASE+0x0B0) // Write = TX keep cs, read=RX
+
+
+
+//
+// SPI 1 (SPI2 in the device!)
+//
+#define AUX_SPI1_CNTL0_REG        (AUX_IO_BASE+0x0C0)
+#define AUX_SPI1_CNTL1_REG        (AUX_IO_BASE+0x0C4)
+#define AUX_SPI1_STAT_REG         (AUX_IO_BASE+0x0C8)
+#define AUX_SPI1_PEEK_REG         (AUX_IO_BASE+0x0CC)
+#define AUX_SPI1_IO_REG           (AUX_IO_BASE+0x0E0)
+#define AUX_SPI1_TXHOLD_REG       (AUX_IO_BASE+0x0F0) // Write = TX keep cs, read=RX
+
+//
+//  Some usefull GPIO macros
+//
+#define CLR_GPIO(g) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))&= ~(7<<(((g)%10)*3))
+#define SET_GPIO_ALT(g,a) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))|= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
diff --git a/bcm2708_chip/ave_in.h b/bcm2708_chip/ave_in.h
new file mode 100755 (executable)
index 0000000..d35fccf
--- /dev/null
@@ -0,0 +1,334 @@
+// This file was generated by the create_regs script
+#define AVE_IN_BASE                                              0x7e910000
+#define AVE_IN_APB_ID                                            0x61766530
+#define AVE_IN_CTRL                                              HW_REGISTER_RW( 0x7e910000 ) 
+   #define AVE_IN_CTRL_MASK                                      0x87ffffff
+   #define AVE_IN_CTRL_WIDTH                                     32
+   #define AVE_IN_CTRL_RESET                                     0x08000080
+      #define AVE_IN_CTRL_ENABLE_BITS                            31:31
+      #define AVE_IN_CTRL_ENABLE_SET                             0x80000000
+      #define AVE_IN_CTRL_ENABLE_CLR                             0x7fffffff
+      #define AVE_IN_CTRL_ENABLE_MSB                             31
+      #define AVE_IN_CTRL_ENABLE_LSB                             31
+      #define AVE_IN_CTRL_PRIORITY_LIMIT_BITS                    26:24
+      #define AVE_IN_CTRL_PRIORITY_LIMIT_SET                     0x07000000
+      #define AVE_IN_CTRL_PRIORITY_LIMIT_CLR                     0xf8ffffff
+      #define AVE_IN_CTRL_PRIORITY_LIMIT_MSB                     26
+      #define AVE_IN_CTRL_PRIORITY_LIMIT_LSB                     24
+      #define AVE_IN_CTRL_HIGH_PRIORITY_BITS                     23:20
+      #define AVE_IN_CTRL_HIGH_PRIORITY_SET                      0x00f00000
+      #define AVE_IN_CTRL_HIGH_PRIORITY_CLR                      0xff0fffff
+      #define AVE_IN_CTRL_HIGH_PRIORITY_MSB                      23
+      #define AVE_IN_CTRL_HIGH_PRIORITY_LSB                      20
+      #define AVE_IN_CTRL_LOW_PRIORITY_BITS                      19:16
+      #define AVE_IN_CTRL_LOW_PRIORITY_SET                       0x000f0000
+      #define AVE_IN_CTRL_LOW_PRIORITY_CLR                       0xfff0ffff
+      #define AVE_IN_CTRL_LOW_PRIORITY_MSB                       19
+      #define AVE_IN_CTRL_LOW_PRIORITY_LSB                       16
+      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_BITS                  15:15
+      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_SET                   0x00008000
+      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_CLR                   0xffff7fff
+      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_MSB                   15
+      #define AVE_IN_CTRL_EN_OVERRUN_ABORT_LSB                   15
+      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_BITS             14:14
+      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_SET              0x00004000
+      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_CLR              0xffffbfff
+      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_MSB              14
+      #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_LSB              14
+      #define AVE_IN_CTRL_BYTE_ORDER_BITS                        13:11
+      #define AVE_IN_CTRL_BYTE_ORDER_SET                         0x00003800
+      #define AVE_IN_CTRL_BYTE_ORDER_CLR                         0xffffc7ff
+      #define AVE_IN_CTRL_BYTE_ORDER_MSB                         13
+      #define AVE_IN_CTRL_BYTE_ORDER_LSB                         11
+      #define AVE_IN_CTRL_FRAME_MODE_BITS                        10:9
+      #define AVE_IN_CTRL_FRAME_MODE_SET                         0x00000600
+      #define AVE_IN_CTRL_FRAME_MODE_CLR                         0xfffff9ff
+      #define AVE_IN_CTRL_FRAME_MODE_MSB                         10
+      #define AVE_IN_CTRL_FRAME_MODE_LSB                         9
+      #define AVE_IN_CTRL_LENGTH_IN_PXLS_BITS                    8:8
+      #define AVE_IN_CTRL_LENGTH_IN_PXLS_SET                     0x00000100
+      #define AVE_IN_CTRL_LENGTH_IN_PXLS_CLR                     0xfffffeff
+      #define AVE_IN_CTRL_LENGTH_IN_PXLS_MSB                     8
+      #define AVE_IN_CTRL_LENGTH_IN_PXLS_LSB                     8
+      #define AVE_IN_CTRL_PRIV_MODE_BITS                         7:7
+      #define AVE_IN_CTRL_PRIV_MODE_SET                          0x00000080
+      #define AVE_IN_CTRL_PRIV_MODE_CLR                          0xffffff7f
+      #define AVE_IN_CTRL_PRIV_MODE_MSB                          7
+      #define AVE_IN_CTRL_PRIV_MODE_LSB                          7
+      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_BITS                 6:6
+      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_SET                  0x00000040
+      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_CLR                  0xffffffbf
+      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_MSB                  6
+      #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_LSB                  6
+      #define AVE_IN_CTRL_HSYNC_IRQ_EN_BITS                      5:5
+      #define AVE_IN_CTRL_HSYNC_IRQ_EN_SET                       0x00000020
+      #define AVE_IN_CTRL_HSYNC_IRQ_EN_CLR                       0xffffffdf
+      #define AVE_IN_CTRL_HSYNC_IRQ_EN_MSB                       5
+      #define AVE_IN_CTRL_HSYNC_IRQ_EN_LSB                       5
+      #define AVE_IN_CTRL_LINE_IRQ_EN_BITS                       4:4
+      #define AVE_IN_CTRL_LINE_IRQ_EN_SET                        0x00000010
+      #define AVE_IN_CTRL_LINE_IRQ_EN_CLR                        0xffffffef
+      #define AVE_IN_CTRL_LINE_IRQ_EN_MSB                        4
+      #define AVE_IN_CTRL_LINE_IRQ_EN_LSB                        4
+      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_BITS                    3:3
+      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_SET                     0x00000008
+      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_CLR                     0xfffffff7
+      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_MSB                     3
+      #define AVE_IN_CTRL_BUF_SER_IRQ_EN_LSB                     3
+      #define AVE_IN_CTRL_BUF1_IRQ_EN_BITS                       2:2
+      #define AVE_IN_CTRL_BUF1_IRQ_EN_SET                        0x00000004
+      #define AVE_IN_CTRL_BUF1_IRQ_EN_CLR                        0xfffffffb
+      #define AVE_IN_CTRL_BUF1_IRQ_EN_MSB                        2
+      #define AVE_IN_CTRL_BUF1_IRQ_EN_LSB                        2
+      #define AVE_IN_CTRL_BUF0_IRQ_EN_BITS                       1:1
+      #define AVE_IN_CTRL_BUF0_IRQ_EN_SET                        0x00000002
+      #define AVE_IN_CTRL_BUF0_IRQ_EN_CLR                        0xfffffffd
+      #define AVE_IN_CTRL_BUF0_IRQ_EN_MSB                        1
+      #define AVE_IN_CTRL_BUF0_IRQ_EN_LSB                        1
+      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_BITS                    0:0
+      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_SET                     0x00000001
+      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_CLR                     0xfffffffe
+      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_MSB                     0
+      #define AVE_IN_CTRL_OVERRUN_IRQ_EN_LSB                     0
+#define AVE_IN_STATUS                                            HW_REGISTER_RW( 0x7e910004 ) 
+   #define AVE_IN_STATUS_MASK                                    0x9f733f7f
+   #define AVE_IN_STATUS_WIDTH                                   32
+   #define AVE_IN_STATUS_RESET                                   0000000000
+      #define AVE_IN_STATUS_CAPTURING_BITS                       31:31
+      #define AVE_IN_STATUS_CAPTURING_SET                        0x80000000
+      #define AVE_IN_STATUS_CAPTURING_CLR                        0x7fffffff
+      #define AVE_IN_STATUS_CAPTURING_MSB                        31
+      #define AVE_IN_STATUS_CAPTURING_LSB                        31
+      #define AVE_IN_STATUS_OVERRUN_CNT_BITS                     28:24
+      #define AVE_IN_STATUS_OVERRUN_CNT_SET                      0x1f000000
+      #define AVE_IN_STATUS_OVERRUN_CNT_CLR                      0xe0ffffff
+      #define AVE_IN_STATUS_OVERRUN_CNT_MSB                      28
+      #define AVE_IN_STATUS_OVERRUN_CNT_LSB                      24
+      #define AVE_IN_STATUS_AXI_STATE_BITS                       22:20
+      #define AVE_IN_STATUS_AXI_STATE_SET                        0x00700000
+      #define AVE_IN_STATUS_AXI_STATE_CLR                        0xff8fffff
+      #define AVE_IN_STATUS_AXI_STATE_MSB                        22
+      #define AVE_IN_STATUS_AXI_STATE_LSB                        20
+      #define AVE_IN_STATUS_CURRENT_BUF_BITS                     17:17
+      #define AVE_IN_STATUS_CURRENT_BUF_SET                      0x00020000
+      #define AVE_IN_STATUS_CURRENT_BUF_CLR                      0xfffdffff
+      #define AVE_IN_STATUS_CURRENT_BUF_MSB                      17
+      #define AVE_IN_STATUS_CURRENT_BUF_LSB                      17
+      #define AVE_IN_STATUS_MAX_HIT_BITS                         16:16
+      #define AVE_IN_STATUS_MAX_HIT_SET                          0x00010000
+      #define AVE_IN_STATUS_MAX_HIT_CLR                          0xfffeffff
+      #define AVE_IN_STATUS_MAX_HIT_MSB                          16
+      #define AVE_IN_STATUS_MAX_HIT_LSB                          16
+      #define AVE_IN_STATUS_CSYNC_FIELD_BITS                     13:13
+      #define AVE_IN_STATUS_CSYNC_FIELD_SET                      0x00002000
+      #define AVE_IN_STATUS_CSYNC_FIELD_CLR                      0xffffdfff
+      #define AVE_IN_STATUS_CSYNC_FIELD_MSB                      13
+      #define AVE_IN_STATUS_CSYNC_FIELD_LSB                      13
+      #define AVE_IN_STATUS_VFORM_FIELD_BITS                     12:12
+      #define AVE_IN_STATUS_VFORM_FIELD_SET                      0x00001000
+      #define AVE_IN_STATUS_VFORM_FIELD_CLR                      0xffffefff
+      #define AVE_IN_STATUS_VFORM_FIELD_MSB                      12
+      #define AVE_IN_STATUS_VFORM_FIELD_LSB                      12
+      #define AVE_IN_STATUS_EVEN_FIELD_BITS                      11:11
+      #define AVE_IN_STATUS_EVEN_FIELD_SET                       0x00000800
+      #define AVE_IN_STATUS_EVEN_FIELD_CLR                       0xfffff7ff
+      #define AVE_IN_STATUS_EVEN_FIELD_MSB                       11
+      #define AVE_IN_STATUS_EVEN_FIELD_LSB                       11
+      #define AVE_IN_STATUS_INTERLACED_BITS                      10:10
+      #define AVE_IN_STATUS_INTERLACED_SET                       0x00000400
+      #define AVE_IN_STATUS_INTERLACED_CLR                       0xfffffbff
+      #define AVE_IN_STATUS_INTERLACED_MSB                       10
+      #define AVE_IN_STATUS_INTERLACED_LSB                       10
+      #define AVE_IN_STATUS_FRAME_RATE_BITS                      9:8
+      #define AVE_IN_STATUS_FRAME_RATE_SET                       0x00000300
+      #define AVE_IN_STATUS_FRAME_RATE_CLR                       0xfffffcff
+      #define AVE_IN_STATUS_FRAME_RATE_MSB                       9
+      #define AVE_IN_STATUS_FRAME_RATE_LSB                       8
+      #define AVE_IN_STATUS_FRAME_RATE_DET_BITS                  6:6
+      #define AVE_IN_STATUS_FRAME_RATE_DET_SET                   0x00000040
+      #define AVE_IN_STATUS_FRAME_RATE_DET_CLR                   0xffffffbf
+      #define AVE_IN_STATUS_FRAME_RATE_DET_MSB                   6
+      #define AVE_IN_STATUS_FRAME_RATE_DET_LSB                   6
+      #define AVE_IN_STATUS_HSYNC_DET_BITS                       5:5
+      #define AVE_IN_STATUS_HSYNC_DET_SET                        0x00000020
+      #define AVE_IN_STATUS_HSYNC_DET_CLR                        0xffffffdf
+      #define AVE_IN_STATUS_HSYNC_DET_MSB                        5
+      #define AVE_IN_STATUS_HSYNC_DET_LSB                        5
+      #define AVE_IN_STATUS_LINE_NUM_HIT_BITS                    4:4
+      #define AVE_IN_STATUS_LINE_NUM_HIT_SET                     0x00000010
+      #define AVE_IN_STATUS_LINE_NUM_HIT_CLR                     0xffffffef
+      #define AVE_IN_STATUS_LINE_NUM_HIT_MSB                     4
+      #define AVE_IN_STATUS_LINE_NUM_HIT_LSB                     4
+      #define AVE_IN_STATUS_BUF_NOT_SERV_BITS                    3:3
+      #define AVE_IN_STATUS_BUF_NOT_SERV_SET                     0x00000008
+      #define AVE_IN_STATUS_BUF_NOT_SERV_CLR                     0xfffffff7
+      #define AVE_IN_STATUS_BUF_NOT_SERV_MSB                     3
+      #define AVE_IN_STATUS_BUF_NOT_SERV_LSB                     3
+      #define AVE_IN_STATUS_BUF1_COMPL_BITS                      2:2
+      #define AVE_IN_STATUS_BUF1_COMPL_SET                       0x00000004
+      #define AVE_IN_STATUS_BUF1_COMPL_CLR                       0xfffffffb
+      #define AVE_IN_STATUS_BUF1_COMPL_MSB                       2
+      #define AVE_IN_STATUS_BUF1_COMPL_LSB                       2
+      #define AVE_IN_STATUS_BUF0_COMPL_BITS                      1:1
+      #define AVE_IN_STATUS_BUF0_COMPL_SET                       0x00000002
+      #define AVE_IN_STATUS_BUF0_COMPL_CLR                       0xfffffffd
+      #define AVE_IN_STATUS_BUF0_COMPL_MSB                       1
+      #define AVE_IN_STATUS_BUF0_COMPL_LSB                       1
+      #define AVE_IN_STATUS_OVERRUN_DET_BITS                     0:0
+      #define AVE_IN_STATUS_OVERRUN_DET_SET                      0x00000001
+      #define AVE_IN_STATUS_OVERRUN_DET_CLR                      0xfffffffe
+      #define AVE_IN_STATUS_OVERRUN_DET_MSB                      0
+      #define AVE_IN_STATUS_OVERRUN_DET_LSB                      0
+#define AVE_IN_BUF0_ADDRESS                                      HW_REGISTER_RW( 0x7e910008 ) 
+   #define AVE_IN_BUF0_ADDRESS_MASK                              0xffffffff
+   #define AVE_IN_BUF0_ADDRESS_WIDTH                             32
+   #define AVE_IN_BUF0_ADDRESS_RESET                             0000000000
+      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_BITS                 31:0
+      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_SET                  0xffffffff
+      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_CLR                  0x00000000
+      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_MSB                  31
+      #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_LSB                  0
+#define AVE_IN_BUF1_ADDRESS                                      HW_REGISTER_RW( 0x7e91000c ) 
+   #define AVE_IN_BUF1_ADDRESS_MASK                              0xffffffff
+   #define AVE_IN_BUF1_ADDRESS_WIDTH                             32
+   #define AVE_IN_BUF1_ADDRESS_RESET                             0000000000
+      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_BITS                 31:0
+      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_SET                  0xffffffff
+      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_CLR                  0x00000000
+      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_MSB                  31
+      #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_LSB                  0
+#define AVE_IN_MAX_TRANSFER                                      HW_REGISTER_RW( 0x7e910010 ) 
+   #define AVE_IN_MAX_TRANSFER_MASK                              0xffffffff
+   #define AVE_IN_MAX_TRANSFER_WIDTH                             32
+   #define AVE_IN_MAX_TRANSFER_RESET                             0000000000
+      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_BITS              31:0
+      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_SET               0xffffffff
+      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_CLR               0x00000000
+      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_MSB               31
+      #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_LSB               0
+#define AVE_IN_LINE_LENGTH                                       HW_REGISTER_RW( 0x7e910014 ) 
+   #define AVE_IN_LINE_LENGTH_MASK                               0x00000fff
+   #define AVE_IN_LINE_LENGTH_WIDTH                              12
+   #define AVE_IN_LINE_LENGTH_RESET                              0000000000
+      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_BITS                11:0
+      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_SET                 0x00000fff
+      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_CLR                 0xfffff000
+      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_MSB                 11
+      #define AVE_IN_LINE_LENGTH_LINE_LENGTH_LSB                 0
+#define AVE_IN_CURRENT_ADDRESS                                   HW_REGISTER_RW( 0x7e910018 ) 
+   #define AVE_IN_CURRENT_ADDRESS_MASK                           0xffffffff
+   #define AVE_IN_CURRENT_ADDRESS_WIDTH                          32
+   #define AVE_IN_CURRENT_ADDRESS_RESET                          0000000000
+      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_BITS               31:0
+      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_SET                0xffffffff
+      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_CLR                0x00000000
+      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_MSB                31
+      #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_LSB                0
+#define AVE_IN_CURRENT_LINE_BUF0                                 HW_REGISTER_RW( 0x7e91001c ) 
+   #define AVE_IN_CURRENT_LINE_BUF0_MASK                         0x80000fff
+   #define AVE_IN_CURRENT_LINE_BUF0_WIDTH                        32
+   #define AVE_IN_CURRENT_LINE_BUF0_RESET                        0000000000
+      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_BITS         11:0
+      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_SET          0x00000fff
+      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_CLR          0xfffff000
+      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_MSB          11
+      #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_LSB          0
+      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_BITS           31:31
+      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_SET            0x80000000
+      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_CLR            0x7fffffff
+      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_MSB            31
+      #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_LSB            31
+#define AVE_IN_CURRENT_LINE_BUF1                                 HW_REGISTER_RW( 0x7e910020 ) 
+   #define AVE_IN_CURRENT_LINE_BUF1_MASK                         0x80000fff
+   #define AVE_IN_CURRENT_LINE_BUF1_WIDTH                        32
+   #define AVE_IN_CURRENT_LINE_BUF1_RESET                        0000000000
+      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_BITS         11:0
+      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_SET          0x00000fff
+      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_CLR          0xfffff000
+      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_MSB          11
+      #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_LSB          0
+      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_BITS           31:31
+      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_SET            0x80000000
+      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_CLR            0x7fffffff
+      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_MSB            31
+      #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_LSB            31
+#define AVE_IN_CURRENT_LINE_NUM                                  HW_REGISTER_RW( 0x7e910024 ) 
+   #define AVE_IN_CURRENT_LINE_NUM_MASK                          0xe0000fff
+   #define AVE_IN_CURRENT_LINE_NUM_WIDTH                         32
+   #define AVE_IN_CURRENT_LINE_NUM_RESET                         0000000000
+      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_BITS          11:0
+      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_SET           0x00000fff
+      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_CLR           0xfffff000
+      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_MSB           11
+      #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_LSB           0
+      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_BITS        29:29
+      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_SET         0x20000000
+      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_CLR         0xdfffffff
+      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_MSB         29
+      #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_LSB         29
+      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_BITS            30:30
+      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_SET             0x40000000
+      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_CLR             0xbfffffff
+      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_MSB             30
+      #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_LSB             30
+      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_BITS            31:31
+      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_SET             0x80000000
+      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_CLR             0x7fffffff
+      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_MSB             31
+      #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_LSB             31
+#define AVE_IN_OVERRUN_ADDRESS                                   HW_REGISTER_RW( 0x7e910028 ) 
+   #define AVE_IN_OVERRUN_ADDRESS_MASK                           0xffffffff
+   #define AVE_IN_OVERRUN_ADDRESS_WIDTH                          32
+   #define AVE_IN_OVERRUN_ADDRESS_RESET                          0000000000
+      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_BITS           31:0
+      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_SET            0xffffffff
+      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_CLR            0x00000000
+      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_MSB            31
+      #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_LSB            0
+#define AVE_IN_LINE_NUM_INT                                      HW_REGISTER_RW( 0x7e91002c ) 
+   #define AVE_IN_LINE_NUM_INT_MASK                              0x00000fff
+   #define AVE_IN_LINE_NUM_INT_WIDTH                             12
+   #define AVE_IN_LINE_NUM_INT_RESET                             0000000000
+      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_BITS              11:0
+      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_SET               0x00000fff
+      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_CLR               0xfffff000
+      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_MSB               11
+      #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_LSB               0
+#define AVE_IN_CALC_LINE_STEP                                    HW_REGISTER_RW( 0x7e910030 ) 
+   #define AVE_IN_CALC_LINE_STEP_MASK                            0x00000fff
+   #define AVE_IN_CALC_LINE_STEP_WIDTH                           12
+   #define AVE_IN_CALC_LINE_STEP_RESET                           0000000000
+      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_BITS          11:0
+      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_SET           0x00000fff
+      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_CLR           0xfffff000
+      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_MSB           11
+      #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_LSB           0
+#define AVE_IN_OUTSTANDING_BUFF0                                 HW_REGISTER_RW( 0x7e910034 ) 
+   #define AVE_IN_OUTSTANDING_BUFF0_MASK                         0x000000ff
+   #define AVE_IN_OUTSTANDING_BUFF0_WIDTH                        8
+   #define AVE_IN_OUTSTANDING_BUFF0_RESET                        0000000000
+#define AVE_IN_OUTSTANDING_BUFF1                                 HW_REGISTER_RW( 0x7e910038 ) 
+   #define AVE_IN_OUTSTANDING_BUFF1_MASK                         0x000000ff
+   #define AVE_IN_OUTSTANDING_BUFF1_WIDTH                        8
+   #define AVE_IN_OUTSTANDING_BUFF1_RESET                        0000000000
+#define AVE_IN_CHAR_CTRL                                         HW_REGISTER_RW( 0x7e91003c ) 
+   #define AVE_IN_CHAR_CTRL_MASK                                 0x8000000f
+   #define AVE_IN_CHAR_CTRL_WIDTH                                32
+   #define AVE_IN_CHAR_CTRL_RESET                                0000000000
+#define AVE_IN_SYNC_CTRL                                         HW_REGISTER_RW( 0x7e910040 ) 
+   #define AVE_IN_SYNC_CTRL_MASK                                 0x0000008f
+   #define AVE_IN_SYNC_CTRL_WIDTH                                8
+   #define AVE_IN_SYNC_CTRL_RESET                                0000000000
+#define AVE_IN_FRAME_NUM                                         HW_REGISTER_RW( 0x7e910044 ) 
+   #define AVE_IN_FRAME_NUM_MASK                                 0x00000fff
+   #define AVE_IN_FRAME_NUM_WIDTH                                12
+   #define AVE_IN_FRAME_NUM_RESET                                0000000000
+      #define AVE_IN_FRAME_NUM_FRAME_NUM_BITS                    11:0
+      #define AVE_IN_FRAME_NUM_FRAME_NUM_SET                     0x00000fff
+      #define AVE_IN_FRAME_NUM_FRAME_NUM_CLR                     0xfffff000
+      #define AVE_IN_FRAME_NUM_FRAME_NUM_MSB                     11
+      #define AVE_IN_FRAME_NUM_FRAME_NUM_LSB                     0
+#define AVE_IN_BLOCK_ID                                          HW_REGISTER_RW( 0x7e910060 ) 
+   #define AVE_IN_BLOCK_ID_MASK                                  0xffffffff
+   #define AVE_IN_BLOCK_ID_WIDTH                                 32
+   #define AVE_IN_BLOCK_ID_RESET                                 0x61766530
diff --git a/bcm2708_chip/ave_out.h b/bcm2708_chip/ave_out.h
new file mode 100755 (executable)
index 0000000..ab7262e
--- /dev/null
@@ -0,0 +1,216 @@
+// This file was generated by the create_regs script
+#define AVE_OUT_BASE                                             0x7e240000
+#define AVE_OUT_APB_ID                                           0x61766538
+#define AVE_OUT_CTRL                                             HW_REGISTER_RW( 0x7e240000 ) 
+   #define AVE_OUT_CTRL_MASK                                     0xc0fff13f
+   #define AVE_OUT_CTRL_WIDTH                                    32
+   #define AVE_OUT_CTRL_RESET                                    0x40000100
+      #define AVE_OUT_CTRL_ENABLE_BITS                           31:31
+      #define AVE_OUT_CTRL_ENABLE_SET                            0x80000000
+      #define AVE_OUT_CTRL_ENABLE_CLR                            0x7fffffff
+      #define AVE_OUT_CTRL_ENABLE_MSB                            31
+      #define AVE_OUT_CTRL_ENABLE_LSB                            31
+      #define AVE_OUT_CTRL_SOFT_RESET_BITS                       30:30
+      #define AVE_OUT_CTRL_SOFT_RESET_SET                        0x40000000
+      #define AVE_OUT_CTRL_SOFT_RESET_CLR                        0xbfffffff
+      #define AVE_OUT_CTRL_SOFT_RESET_MSB                        30
+      #define AVE_OUT_CTRL_SOFT_RESET_LSB                        30
+      #define AVE_OUT_CTRL_BYTE_SWAP_BITS                        23:19
+      #define AVE_OUT_CTRL_BYTE_SWAP_SET                         0x00f80000
+      #define AVE_OUT_CTRL_BYTE_SWAP_CLR                         0xff07ffff
+      #define AVE_OUT_CTRL_BYTE_SWAP_MSB                         23
+      #define AVE_OUT_CTRL_BYTE_SWAP_LSB                         19
+      #define AVE_OUT_CTRL_INVERT_DSYNC_BITS                     18:18
+      #define AVE_OUT_CTRL_INVERT_DSYNC_SET                      0x00040000
+      #define AVE_OUT_CTRL_INVERT_DSYNC_CLR                      0xfffbffff
+      #define AVE_OUT_CTRL_INVERT_DSYNC_MSB                      18
+      #define AVE_OUT_CTRL_INVERT_DSYNC_LSB                      18
+      #define AVE_OUT_CTRL_INVERT_CSYNC_BITS                     17:17
+      #define AVE_OUT_CTRL_INVERT_CSYNC_SET                      0x00020000
+      #define AVE_OUT_CTRL_INVERT_CSYNC_CLR                      0xfffdffff
+      #define AVE_OUT_CTRL_INVERT_CSYNC_MSB                      17
+      #define AVE_OUT_CTRL_INVERT_CSYNC_LSB                      17
+      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_BITS                16:16
+      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_SET                 0x00010000
+      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_CLR                 0xfffeffff
+      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_MSB                 16
+      #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_LSB                 16
+      #define AVE_OUT_CTRL_INVERT_VSYNC_BITS                     15:15
+      #define AVE_OUT_CTRL_INVERT_VSYNC_SET                      0x00008000
+      #define AVE_OUT_CTRL_INVERT_VSYNC_CLR                      0xffff7fff
+      #define AVE_OUT_CTRL_INVERT_VSYNC_MSB                      15
+      #define AVE_OUT_CTRL_INVERT_VSYNC_LSB                      15
+      #define AVE_OUT_CTRL_INVERT_HSYNC_BITS                     14:14
+      #define AVE_OUT_CTRL_INVERT_HSYNC_SET                      0x00004000
+      #define AVE_OUT_CTRL_INVERT_HSYNC_CLR                      0xffffbfff
+      #define AVE_OUT_CTRL_INVERT_HSYNC_MSB                      14
+      #define AVE_OUT_CTRL_INVERT_HSYNC_LSB                      14
+      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_BITS                   13:13
+      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_SET                    0x00002000
+      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_CLR                    0xffffdfff
+      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_MSB                    13
+      #define AVE_OUT_CTRL_NTSC_PAL_IDENT_LSB                    13
+      #define AVE_OUT_CTRL_INTERLEAVE_BITS                       12:12
+      #define AVE_OUT_CTRL_INTERLEAVE_SET                        0x00001000
+      #define AVE_OUT_CTRL_INTERLEAVE_CLR                        0xffffefff
+      #define AVE_OUT_CTRL_INTERLEAVE_MSB                        12
+      #define AVE_OUT_CTRL_INTERLEAVE_LSB                        12
+      #define AVE_OUT_CTRL_PRIV_ACCESS_BITS                      8:8
+      #define AVE_OUT_CTRL_PRIV_ACCESS_SET                       0x00000100
+      #define AVE_OUT_CTRL_PRIV_ACCESS_CLR                       0xfffffeff
+      #define AVE_OUT_CTRL_PRIV_ACCESS_MSB                       8
+      #define AVE_OUT_CTRL_PRIV_ACCESS_LSB                       8
+      #define AVE_OUT_CTRL_MODE_BITS                             5:4
+      #define AVE_OUT_CTRL_MODE_SET                              0x00000030
+      #define AVE_OUT_CTRL_MODE_CLR                              0xffffffcf
+      #define AVE_OUT_CTRL_MODE_MSB                              5
+      #define AVE_OUT_CTRL_MODE_LSB                              4
+      #define AVE_OUT_CTRL_REFRESH_RATE_BITS                     3:2
+      #define AVE_OUT_CTRL_REFRESH_RATE_SET                      0x0000000c
+      #define AVE_OUT_CTRL_REFRESH_RATE_CLR                      0xfffffff3
+      #define AVE_OUT_CTRL_REFRESH_RATE_MSB                      3
+      #define AVE_OUT_CTRL_REFRESH_RATE_LSB                      2
+      #define AVE_OUT_CTRL_COEFF_IRQ_EN_BITS                     1:1
+      #define AVE_OUT_CTRL_COEFF_IRQ_EN_SET                      0x00000002
+      #define AVE_OUT_CTRL_COEFF_IRQ_EN_CLR                      0xfffffffd
+      #define AVE_OUT_CTRL_COEFF_IRQ_EN_MSB                      1
+      #define AVE_OUT_CTRL_COEFF_IRQ_EN_LSB                      1
+      #define AVE_OUT_CTRL_ERROR_IRQ_EN_BITS                     0:0
+      #define AVE_OUT_CTRL_ERROR_IRQ_EN_SET                      0x00000001
+      #define AVE_OUT_CTRL_ERROR_IRQ_EN_CLR                      0xfffffffe
+      #define AVE_OUT_CTRL_ERROR_IRQ_EN_MSB                      0
+      #define AVE_OUT_CTRL_ERROR_IRQ_EN_LSB                      0
+#define AVE_OUT_STATUS                                           HW_REGISTER_RW( 0x7e240004 ) 
+   #define AVE_OUT_STATUS_MASK                                   0x000003f7
+   #define AVE_OUT_STATUS_WIDTH                                  10
+   #define AVE_OUT_STATUS_RESET                                  0000000000
+      #define AVE_OUT_STATUS_VSYNC_BITS                          9:9
+      #define AVE_OUT_STATUS_VSYNC_SET                           0x00000200
+      #define AVE_OUT_STATUS_VSYNC_CLR                           0xfffffdff
+      #define AVE_OUT_STATUS_VSYNC_MSB                           9
+      #define AVE_OUT_STATUS_VSYNC_LSB                           9
+      #define AVE_OUT_STATUS_VBACK_PORCH_BITS                    8:8
+      #define AVE_OUT_STATUS_VBACK_PORCH_SET                     0x00000100
+      #define AVE_OUT_STATUS_VBACK_PORCH_CLR                     0xfffffeff
+      #define AVE_OUT_STATUS_VBACK_PORCH_MSB                     8
+      #define AVE_OUT_STATUS_VBACK_PORCH_LSB                     8
+      #define AVE_OUT_STATUS_VFRONT_PORCH_BITS                   7:7
+      #define AVE_OUT_STATUS_VFRONT_PORCH_SET                    0x00000080
+      #define AVE_OUT_STATUS_VFRONT_PORCH_CLR                    0xffffff7f
+      #define AVE_OUT_STATUS_VFRONT_PORCH_MSB                    7
+      #define AVE_OUT_STATUS_VFRONT_PORCH_LSB                    7
+      #define AVE_OUT_STATUS_HSYNC_BITS                          6:6
+      #define AVE_OUT_STATUS_HSYNC_SET                           0x00000040
+      #define AVE_OUT_STATUS_HSYNC_CLR                           0xffffffbf
+      #define AVE_OUT_STATUS_HSYNC_MSB                           6
+      #define AVE_OUT_STATUS_HSYNC_LSB                           6
+      #define AVE_OUT_STATUS_HBACK_PORCH_BITS                    5:5
+      #define AVE_OUT_STATUS_HBACK_PORCH_SET                     0x00000020
+      #define AVE_OUT_STATUS_HBACK_PORCH_CLR                     0xffffffdf
+      #define AVE_OUT_STATUS_HBACK_PORCH_MSB                     5
+      #define AVE_OUT_STATUS_HBACK_PORCH_LSB                     5
+      #define AVE_OUT_STATUS_HFRONT_PORCH_BITS                   4:4
+      #define AVE_OUT_STATUS_HFRONT_PORCH_SET                    0x00000010
+      #define AVE_OUT_STATUS_HFRONT_PORCH_CLR                    0xffffffef
+      #define AVE_OUT_STATUS_HFRONT_PORCH_MSB                    4
+      #define AVE_OUT_STATUS_HFRONT_PORCH_LSB                    4
+      #define AVE_OUT_STATUS_COEFF_ERROR_BITS                    2:2
+      #define AVE_OUT_STATUS_COEFF_ERROR_SET                     0x00000004
+      #define AVE_OUT_STATUS_COEFF_ERROR_CLR                     0xfffffffb
+      #define AVE_OUT_STATUS_COEFF_ERROR_MSB                     2
+      #define AVE_OUT_STATUS_COEFF_ERROR_LSB                     2
+      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_BITS               1:1
+      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_SET                0x00000002
+      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_CLR                0xfffffffd
+      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_MSB                1
+      #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_LSB                1
+      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_BITS               0:0
+      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_SET                0x00000001
+      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_CLR                0xfffffffe
+      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_MSB                0
+      #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_LSB                0
+#define AVE_OUT_OFFSET                                           HW_REGISTER_RW( 0x7e240008 ) 
+   #define AVE_OUT_OFFSET_MASK                                   0x80ffffff
+   #define AVE_OUT_OFFSET_WIDTH                                  32
+   #define AVE_OUT_OFFSET_RESET                                  0x80109090
+      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_BITS              31:31
+      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_SET               0x80000000
+      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_CLR               0x7fffffff
+      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_MSB               31
+      #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_LSB               31
+      #define AVE_OUT_OFFSET_RED_OFFSET_BITS                     23:16
+      #define AVE_OUT_OFFSET_RED_OFFSET_SET                      0x00ff0000
+      #define AVE_OUT_OFFSET_RED_OFFSET_CLR                      0xff00ffff
+      #define AVE_OUT_OFFSET_RED_OFFSET_MSB                      23
+      #define AVE_OUT_OFFSET_RED_OFFSET_LSB                      16
+      #define AVE_OUT_OFFSET_GREEN_OFFSET_BITS                   15:8
+      #define AVE_OUT_OFFSET_GREEN_OFFSET_SET                    0x0000ff00
+      #define AVE_OUT_OFFSET_GREEN_OFFSET_CLR                    0xffff00ff
+      #define AVE_OUT_OFFSET_GREEN_OFFSET_MSB                    15
+      #define AVE_OUT_OFFSET_GREEN_OFFSET_LSB                    8
+      #define AVE_OUT_OFFSET_BLUE_OFFSET_BITS                    7:0
+      #define AVE_OUT_OFFSET_BLUE_OFFSET_SET                     0x000000ff
+      #define AVE_OUT_OFFSET_BLUE_OFFSET_CLR                     0xffffff00
+      #define AVE_OUT_OFFSET_BLUE_OFFSET_MSB                     7
+      #define AVE_OUT_OFFSET_BLUE_OFFSET_LSB                     0
+#define AVE_OUT_Y_COEFF                                          HW_REGISTER_RW( 0x7e24000c ) 
+   #define AVE_OUT_Y_COEFF_MASK                                  0x3fffffff
+   #define AVE_OUT_Y_COEFF_WIDTH                                 30
+   #define AVE_OUT_Y_COEFF_RESET                                 0x0994b43a
+      #define AVE_OUT_Y_COEFF_RED_COEFF_BITS                     29:20
+      #define AVE_OUT_Y_COEFF_RED_COEFF_SET                      0x3ff00000
+      #define AVE_OUT_Y_COEFF_RED_COEFF_CLR                      0xc00fffff
+      #define AVE_OUT_Y_COEFF_RED_COEFF_MSB                      29
+      #define AVE_OUT_Y_COEFF_RED_COEFF_LSB                      20
+      #define AVE_OUT_Y_COEFF_GREEN_COEFF_BITS                   19:10
+      #define AVE_OUT_Y_COEFF_GREEN_COEFF_SET                    0x000ffc00
+      #define AVE_OUT_Y_COEFF_GREEN_COEFF_CLR                    0xfff003ff
+      #define AVE_OUT_Y_COEFF_GREEN_COEFF_MSB                    19
+      #define AVE_OUT_Y_COEFF_GREEN_COEFF_LSB                    10
+      #define AVE_OUT_Y_COEFF_BLUE_COEFF_BITS                    9:0
+      #define AVE_OUT_Y_COEFF_BLUE_COEFF_SET                     0x000003ff
+      #define AVE_OUT_Y_COEFF_BLUE_COEFF_CLR                     0xfffffc00
+      #define AVE_OUT_Y_COEFF_BLUE_COEFF_MSB                     9
+      #define AVE_OUT_Y_COEFF_BLUE_COEFF_LSB                     0
+#define AVE_OUT_CB_COEFF                                         HW_REGISTER_RW( 0x7e240010 ) 
+   #define AVE_OUT_CB_COEFF_MASK                                 0x3fffffff
+   #define AVE_OUT_CB_COEFF_WIDTH                                30
+   #define AVE_OUT_CB_COEFF_RESET                                0x3a9d5900
+      #define AVE_OUT_CB_COEFF_RED_COEFF_BITS                    29:20
+      #define AVE_OUT_CB_COEFF_RED_COEFF_SET                     0x3ff00000
+      #define AVE_OUT_CB_COEFF_RED_COEFF_CLR                     0xc00fffff
+      #define AVE_OUT_CB_COEFF_RED_COEFF_MSB                     29
+      #define AVE_OUT_CB_COEFF_RED_COEFF_LSB                     20
+      #define AVE_OUT_CB_COEFF_GREEN_COEFF_BITS                  19:10
+      #define AVE_OUT_CB_COEFF_GREEN_COEFF_SET                   0x000ffc00
+      #define AVE_OUT_CB_COEFF_GREEN_COEFF_CLR                   0xfff003ff
+      #define AVE_OUT_CB_COEFF_GREEN_COEFF_MSB                   19
+      #define AVE_OUT_CB_COEFF_GREEN_COEFF_LSB                   10
+      #define AVE_OUT_CB_COEFF_BLUE_COEFF_BITS                   9:0
+      #define AVE_OUT_CB_COEFF_BLUE_COEFF_SET                    0x000003ff
+      #define AVE_OUT_CB_COEFF_BLUE_COEFF_CLR                    0xfffffc00
+      #define AVE_OUT_CB_COEFF_BLUE_COEFF_MSB                    9
+      #define AVE_OUT_CB_COEFF_BLUE_COEFF_LSB                    0
+#define AVE_OUT_CR_COEFF                                         HW_REGISTER_RW( 0x7e240014 ) 
+   #define AVE_OUT_CR_COEFF_MASK                                 0x3fffffff
+   #define AVE_OUT_CR_COEFF_WIDTH                                30
+   #define AVE_OUT_CR_COEFF_RESET                                0x100ca7d6
+      #define AVE_OUT_CR_COEFF_RED_COEFF_BITS                    29:20
+      #define AVE_OUT_CR_COEFF_RED_COEFF_SET                     0x3ff00000
+      #define AVE_OUT_CR_COEFF_RED_COEFF_CLR                     0xc00fffff
+      #define AVE_OUT_CR_COEFF_RED_COEFF_MSB                     29
+      #define AVE_OUT_CR_COEFF_RED_COEFF_LSB                     20
+      #define AVE_OUT_CR_COEFF_GREEN_COEFF_BITS                  19:10
+      #define AVE_OUT_CR_COEFF_GREEN_COEFF_SET                   0x000ffc00
+      #define AVE_OUT_CR_COEFF_GREEN_COEFF_CLR                   0xfff003ff
+      #define AVE_OUT_CR_COEFF_GREEN_COEFF_MSB                   19
+      #define AVE_OUT_CR_COEFF_GREEN_COEFF_LSB                   10
+      #define AVE_OUT_CR_COEFF_BLUE_COEFF_BITS                   9:0
+      #define AVE_OUT_CR_COEFF_BLUE_COEFF_SET                    0x000003ff
+      #define AVE_OUT_CR_COEFF_BLUE_COEFF_CLR                    0xfffffc00
+      #define AVE_OUT_CR_COEFF_BLUE_COEFF_MSB                    9
+      #define AVE_OUT_CR_COEFF_BLUE_COEFF_LSB                    0
+#define AVE_OUT_BLOCK_ID                                         HW_REGISTER_RW( 0x7e240060 ) 
+   #define AVE_OUT_BLOCK_ID_MASK                                 0xffffffff
+   #define AVE_OUT_BLOCK_ID_WIDTH                                32
+   #define AVE_OUT_BLOCK_ID_RESET                                0x61766538
diff --git a/bcm2708_chip/axi_dma0.h b/bcm2708_chip/axi_dma0.h
new file mode 100755 (executable)
index 0000000..897e88b
--- /dev/null
@@ -0,0 +1,257 @@
+// This file was generated by the create_regs script
+#define DMA0_BASE                                                0x7e007000
+#define DMA0_CS                                                  HW_REGISTER_RW( 0x7e007000 ) 
+   #define DMA0_CS_MASK                                          0xf0ff017f
+   #define DMA0_CS_WIDTH                                         32
+   #define DMA0_CS_RESET                                         0000000000
+      #define DMA0_CS_RESET_BITS                                 31:31
+      #define DMA0_CS_RESET_SET                                  0x80000000
+      #define DMA0_CS_RESET_CLR                                  0x7fffffff
+      #define DMA0_CS_RESET_MSB                                  31
+      #define DMA0_CS_RESET_LSB                                  31
+      #define DMA0_CS_ABORT_BITS                                 30:30
+      #define DMA0_CS_ABORT_SET                                  0x40000000
+      #define DMA0_CS_ABORT_CLR                                  0xbfffffff
+      #define DMA0_CS_ABORT_MSB                                  30
+      #define DMA0_CS_ABORT_LSB                                  30
+      #define DMA0_CS_DISDEBUG_BITS                              29:29
+      #define DMA0_CS_DISDEBUG_SET                               0x20000000
+      #define DMA0_CS_DISDEBUG_CLR                               0xdfffffff
+      #define DMA0_CS_DISDEBUG_MSB                               29
+      #define DMA0_CS_DISDEBUG_LSB                               29
+      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
+      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
+      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
+      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
+      #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
+      #define DMA0_CS_PANIC_PRIORITY_BITS                        23:20
+      #define DMA0_CS_PANIC_PRIORITY_SET                         0x00f00000
+      #define DMA0_CS_PANIC_PRIORITY_CLR                         0xff0fffff
+      #define DMA0_CS_PANIC_PRIORITY_MSB                         23
+      #define DMA0_CS_PANIC_PRIORITY_LSB                         20
+      #define DMA0_CS_PRIORITY_BITS                              19:16
+      #define DMA0_CS_PRIORITY_SET                               0x000f0000
+      #define DMA0_CS_PRIORITY_CLR                               0xfff0ffff
+      #define DMA0_CS_PRIORITY_MSB                               19
+      #define DMA0_CS_PRIORITY_LSB                               16
+      #define DMA0_CS_ERROR_BITS                                 8:8
+      #define DMA0_CS_ERROR_SET                                  0x00000100
+      #define DMA0_CS_ERROR_CLR                                  0xfffffeff
+      #define DMA0_CS_ERROR_MSB                                  8
+      #define DMA0_CS_ERROR_LSB                                  8
+      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
+      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
+      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
+      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
+      #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
+      #define DMA0_CS_DREQ_STOPS_DMA_BITS                        5:5
+      #define DMA0_CS_DREQ_STOPS_DMA_SET                         0x00000020
+      #define DMA0_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
+      #define DMA0_CS_DREQ_STOPS_DMA_MSB                         5
+      #define DMA0_CS_DREQ_STOPS_DMA_LSB                         5
+      #define DMA0_CS_PAUSED_BITS                                4:4
+      #define DMA0_CS_PAUSED_SET                                 0x00000010
+      #define DMA0_CS_PAUSED_CLR                                 0xffffffef
+      #define DMA0_CS_PAUSED_MSB                                 4
+      #define DMA0_CS_PAUSED_LSB                                 4
+      #define DMA0_CS_DREQ_BITS                                  3:3
+      #define DMA0_CS_DREQ_SET                                   0x00000008
+      #define DMA0_CS_DREQ_CLR                                   0xfffffff7
+      #define DMA0_CS_DREQ_MSB                                   3
+      #define DMA0_CS_DREQ_LSB                                   3
+      #define DMA0_CS_INT_BITS                                   2:2
+      #define DMA0_CS_INT_SET                                    0x00000004
+      #define DMA0_CS_INT_CLR                                    0xfffffffb
+      #define DMA0_CS_INT_MSB                                    2
+      #define DMA0_CS_INT_LSB                                    2
+      #define DMA0_CS_END_BITS                                   1:1
+      #define DMA0_CS_END_SET                                    0x00000002
+      #define DMA0_CS_END_CLR                                    0xfffffffd
+      #define DMA0_CS_END_MSB                                    1
+      #define DMA0_CS_END_LSB                                    1
+      #define DMA0_CS_ACTIVE_BITS                                0:0
+      #define DMA0_CS_ACTIVE_SET                                 0x00000001
+      #define DMA0_CS_ACTIVE_CLR                                 0xfffffffe
+      #define DMA0_CS_ACTIVE_MSB                                 0
+      #define DMA0_CS_ACTIVE_LSB                                 0
+#define DMA0_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007004 ) 
+   #define DMA0_CONBLK_AD_MASK                                   0xffffffe0
+   #define DMA0_CONBLK_AD_WIDTH                                  32
+   #define DMA0_CONBLK_AD_RESET                                  0000000000
+      #define DMA0_CONBLK_AD_SCB_ADDR_BITS                       31:5
+      #define DMA0_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
+      #define DMA0_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
+      #define DMA0_CONBLK_AD_SCB_ADDR_MSB                        31
+      #define DMA0_CONBLK_AD_SCB_ADDR_LSB                        5
+#define DMA0_TI                                                  HW_REGISTER_RO( 0x7e007008 ) 
+   #define DMA0_TI_MASK                                          0x07fffffb
+   #define DMA0_TI_WIDTH                                         27
+      #define DMA0_TI_NO_WIDE_BURSTS_BITS                        26:26
+      #define DMA0_TI_NO_WIDE_BURSTS_SET                         0x04000000
+      #define DMA0_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
+      #define DMA0_TI_NO_WIDE_BURSTS_MSB                         26
+      #define DMA0_TI_NO_WIDE_BURSTS_LSB                         26
+      #define DMA0_TI_WAITS_BITS                                 25:21
+      #define DMA0_TI_WAITS_SET                                  0x03e00000
+      #define DMA0_TI_WAITS_CLR                                  0xfc1fffff
+      #define DMA0_TI_WAITS_MSB                                  25
+      #define DMA0_TI_WAITS_LSB                                  21
+      #define DMA0_TI_PERMAP_BITS                                20:16
+      #define DMA0_TI_PERMAP_SET                                 0x001f0000
+      #define DMA0_TI_PERMAP_CLR                                 0xffe0ffff
+      #define DMA0_TI_PERMAP_MSB                                 20
+      #define DMA0_TI_PERMAP_LSB                                 16
+      #define DMA0_TI_BURST_LENGTH_BITS                          15:12
+      #define DMA0_TI_BURST_LENGTH_SET                           0x0000f000
+      #define DMA0_TI_BURST_LENGTH_CLR                           0xffff0fff
+      #define DMA0_TI_BURST_LENGTH_MSB                           15
+      #define DMA0_TI_BURST_LENGTH_LSB                           12
+      #define DMA0_TI_SRC_IGNORE_BITS                            11:11
+      #define DMA0_TI_SRC_IGNORE_SET                             0x00000800
+      #define DMA0_TI_SRC_IGNORE_CLR                             0xfffff7ff
+      #define DMA0_TI_SRC_IGNORE_MSB                             11
+      #define DMA0_TI_SRC_IGNORE_LSB                             11
+      #define DMA0_TI_SRC_DREQ_BITS                              10:10
+      #define DMA0_TI_SRC_DREQ_SET                               0x00000400
+      #define DMA0_TI_SRC_DREQ_CLR                               0xfffffbff
+      #define DMA0_TI_SRC_DREQ_MSB                               10
+      #define DMA0_TI_SRC_DREQ_LSB                               10
+      #define DMA0_TI_SRC_WIDTH_BITS                             9:9
+      #define DMA0_TI_SRC_WIDTH_SET                              0x00000200
+      #define DMA0_TI_SRC_WIDTH_CLR                              0xfffffdff
+      #define DMA0_TI_SRC_WIDTH_MSB                              9
+      #define DMA0_TI_SRC_WIDTH_LSB                              9
+      #define DMA0_TI_SRC_INC_BITS                               8:8
+      #define DMA0_TI_SRC_INC_SET                                0x00000100
+      #define DMA0_TI_SRC_INC_CLR                                0xfffffeff
+      #define DMA0_TI_SRC_INC_MSB                                8
+      #define DMA0_TI_SRC_INC_LSB                                8
+      #define DMA0_TI_DEST_IGNORE_BITS                           7:7
+      #define DMA0_TI_DEST_IGNORE_SET                            0x00000080
+      #define DMA0_TI_DEST_IGNORE_CLR                            0xffffff7f
+      #define DMA0_TI_DEST_IGNORE_MSB                            7
+      #define DMA0_TI_DEST_IGNORE_LSB                            7
+      #define DMA0_TI_DEST_DREQ_BITS                             6:6
+      #define DMA0_TI_DEST_DREQ_SET                              0x00000040
+      #define DMA0_TI_DEST_DREQ_CLR                              0xffffffbf
+      #define DMA0_TI_DEST_DREQ_MSB                              6
+      #define DMA0_TI_DEST_DREQ_LSB                              6
+      #define DMA0_TI_DEST_WIDTH_BITS                            5:5
+      #define DMA0_TI_DEST_WIDTH_SET                             0x00000020
+      #define DMA0_TI_DEST_WIDTH_CLR                             0xffffffdf
+      #define DMA0_TI_DEST_WIDTH_MSB                             5
+      #define DMA0_TI_DEST_WIDTH_LSB                             5
+      #define DMA0_TI_DEST_INC_BITS                              4:4
+      #define DMA0_TI_DEST_INC_SET                               0x00000010
+      #define DMA0_TI_DEST_INC_CLR                               0xffffffef
+      #define DMA0_TI_DEST_INC_MSB                               4
+      #define DMA0_TI_DEST_INC_LSB                               4
+      #define DMA0_TI_WAIT_RESP_BITS                             3:3
+      #define DMA0_TI_WAIT_RESP_SET                              0x00000008
+      #define DMA0_TI_WAIT_RESP_CLR                              0xfffffff7
+      #define DMA0_TI_WAIT_RESP_MSB                              3
+      #define DMA0_TI_WAIT_RESP_LSB                              3
+      #define DMA0_TI_TDMODE_BITS                                1:1
+      #define DMA0_TI_TDMODE_SET                                 0x00000002
+      #define DMA0_TI_TDMODE_CLR                                 0xfffffffd
+      #define DMA0_TI_TDMODE_MSB                                 1
+      #define DMA0_TI_TDMODE_LSB                                 1
+      #define DMA0_TI_INTEN_BITS                                 0:0
+      #define DMA0_TI_INTEN_SET                                  0x00000001
+      #define DMA0_TI_INTEN_CLR                                  0xfffffffe
+      #define DMA0_TI_INTEN_MSB                                  0
+      #define DMA0_TI_INTEN_LSB                                  0
+#define DMA0_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00700c ) 
+   #define DMA0_SOURCE_AD_MASK                                   0xffffffff
+   #define DMA0_SOURCE_AD_WIDTH                                  32
+      #define DMA0_SOURCE_AD_S_ADDR_BITS                         31:0
+      #define DMA0_SOURCE_AD_S_ADDR_SET                          0xffffffff
+      #define DMA0_SOURCE_AD_S_ADDR_CLR                          0x00000000
+      #define DMA0_SOURCE_AD_S_ADDR_MSB                          31
+      #define DMA0_SOURCE_AD_S_ADDR_LSB                          0
+#define DMA0_DEST_AD                                             HW_REGISTER_RO( 0x7e007010 ) 
+   #define DMA0_DEST_AD_MASK                                     0xffffffff
+   #define DMA0_DEST_AD_WIDTH                                    32
+      #define DMA0_DEST_AD_D_ADDR_BITS                           31:0
+      #define DMA0_DEST_AD_D_ADDR_SET                            0xffffffff
+      #define DMA0_DEST_AD_D_ADDR_CLR                            0x00000000
+      #define DMA0_DEST_AD_D_ADDR_MSB                            31
+      #define DMA0_DEST_AD_D_ADDR_LSB                            0
+#define DMA0_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007014 ) 
+   #define DMA0_TXFR_LEN_MASK                                    0x3fffffff
+   #define DMA0_TXFR_LEN_WIDTH                                   30
+      #define DMA0_TXFR_LEN_YLENGTH_BITS                         29:16
+      #define DMA0_TXFR_LEN_YLENGTH_SET                          0x3fff0000
+      #define DMA0_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
+      #define DMA0_TXFR_LEN_YLENGTH_MSB                          29
+      #define DMA0_TXFR_LEN_YLENGTH_LSB                          16
+      #define DMA0_TXFR_LEN_XLENGTH_BITS                         15:0
+      #define DMA0_TXFR_LEN_XLENGTH_SET                          0x0000ffff
+      #define DMA0_TXFR_LEN_XLENGTH_CLR                          0xffff0000
+      #define DMA0_TXFR_LEN_XLENGTH_MSB                          15
+      #define DMA0_TXFR_LEN_XLENGTH_LSB                          0
+#define DMA0_STRIDE                                              HW_REGISTER_RO( 0x7e007018 ) 
+   #define DMA0_STRIDE_MASK                                      0xffffffff
+   #define DMA0_STRIDE_WIDTH                                     32
+      #define DMA0_STRIDE_D_STRIDE_BITS                          31:16
+      #define DMA0_STRIDE_D_STRIDE_SET                           0xffff0000
+      #define DMA0_STRIDE_D_STRIDE_CLR                           0x0000ffff
+      #define DMA0_STRIDE_D_STRIDE_MSB                           31
+      #define DMA0_STRIDE_D_STRIDE_LSB                           16
+      #define DMA0_STRIDE_S_STRIDE_BITS                          15:0
+      #define DMA0_STRIDE_S_STRIDE_SET                           0x0000ffff
+      #define DMA0_STRIDE_S_STRIDE_CLR                           0xffff0000
+      #define DMA0_STRIDE_S_STRIDE_MSB                           15
+      #define DMA0_STRIDE_S_STRIDE_LSB                           0
+#define DMA0_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00701c ) 
+   #define DMA0_NEXTCONBK_MASK                                   0xffffffe0
+   #define DMA0_NEXTCONBK_WIDTH                                  32
+      #define DMA0_NEXTCONBK_ADDR_BITS                           31:5
+      #define DMA0_NEXTCONBK_ADDR_SET                            0xffffffe0
+      #define DMA0_NEXTCONBK_ADDR_CLR                            0x0000001f
+      #define DMA0_NEXTCONBK_ADDR_MSB                            31
+      #define DMA0_NEXTCONBK_ADDR_LSB                            5
+#define DMA0_DEBUG                                               HW_REGISTER_RW( 0x7e007020 ) 
+   #define DMA0_DEBUG_MASK                                       0x1ffffff7
+   #define DMA0_DEBUG_WIDTH                                      29
+   #define DMA0_DEBUG_RESET                                      0000000000
+      #define DMA0_DEBUG_LITE_BITS                               28:28
+      #define DMA0_DEBUG_LITE_SET                                0x10000000
+      #define DMA0_DEBUG_LITE_CLR                                0xefffffff
+      #define DMA0_DEBUG_LITE_MSB                                28
+      #define DMA0_DEBUG_LITE_LSB                                28
+      #define DMA0_DEBUG_VERSION_BITS                            27:25
+      #define DMA0_DEBUG_VERSION_SET                             0x0e000000
+      #define DMA0_DEBUG_VERSION_CLR                             0xf1ffffff
+      #define DMA0_DEBUG_VERSION_MSB                             27
+      #define DMA0_DEBUG_VERSION_LSB                             25
+      #define DMA0_DEBUG_DMA_STATE_BITS                          24:16
+      #define DMA0_DEBUG_DMA_STATE_SET                           0x01ff0000
+      #define DMA0_DEBUG_DMA_STATE_CLR                           0xfe00ffff
+      #define DMA0_DEBUG_DMA_STATE_MSB                           24
+      #define DMA0_DEBUG_DMA_STATE_LSB                           16
+      #define DMA0_DEBUG_DMA_ID_BITS                             15:8
+      #define DMA0_DEBUG_DMA_ID_SET                              0x0000ff00
+      #define DMA0_DEBUG_DMA_ID_CLR                              0xffff00ff
+      #define DMA0_DEBUG_DMA_ID_MSB                              15
+      #define DMA0_DEBUG_DMA_ID_LSB                              8
+      #define DMA0_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
+      #define DMA0_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
+      #define DMA0_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
+      #define DMA0_DEBUG_OUTSTANDING_WRITES_MSB                  7
+      #define DMA0_DEBUG_OUTSTANDING_WRITES_LSB                  4
+      #define DMA0_DEBUG_READ_ERROR_BITS                         2:2
+      #define DMA0_DEBUG_READ_ERROR_SET                          0x00000004
+      #define DMA0_DEBUG_READ_ERROR_CLR                          0xfffffffb
+      #define DMA0_DEBUG_READ_ERROR_MSB                          2
+      #define DMA0_DEBUG_READ_ERROR_LSB                          2
+      #define DMA0_DEBUG_FIFO_ERROR_BITS                         1:1
+      #define DMA0_DEBUG_FIFO_ERROR_SET                          0x00000002
+      #define DMA0_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
+      #define DMA0_DEBUG_FIFO_ERROR_MSB                          1
+      #define DMA0_DEBUG_FIFO_ERROR_LSB                          1
+      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
+      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
+      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
+      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
+      #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma1.h b/bcm2708_chip/axi_dma1.h
new file mode 100755 (executable)
index 0000000..fa68999
--- /dev/null
@@ -0,0 +1,257 @@
+// This file was generated by the create_regs script
+#define DMA1_BASE                                                0x7e007100
+#define DMA1_CS                                                  HW_REGISTER_RW( 0x7e007100 ) 
+   #define DMA1_CS_MASK                                          0xf0ff017f
+   #define DMA1_CS_WIDTH                                         32
+   #define DMA1_CS_RESET                                         0000000000
+      #define DMA1_CS_RESET_BITS                                 31:31
+      #define DMA1_CS_RESET_SET                                  0x80000000
+      #define DMA1_CS_RESET_CLR                                  0x7fffffff
+      #define DMA1_CS_RESET_MSB                                  31
+      #define DMA1_CS_RESET_LSB                                  31
+      #define DMA1_CS_ABORT_BITS                                 30:30
+      #define DMA1_CS_ABORT_SET                                  0x40000000
+      #define DMA1_CS_ABORT_CLR                                  0xbfffffff
+      #define DMA1_CS_ABORT_MSB                                  30
+      #define DMA1_CS_ABORT_LSB                                  30
+      #define DMA1_CS_DISDEBUG_BITS                              29:29
+      #define DMA1_CS_DISDEBUG_SET                               0x20000000
+      #define DMA1_CS_DISDEBUG_CLR                               0xdfffffff
+      #define DMA1_CS_DISDEBUG_MSB                               29
+      #define DMA1_CS_DISDEBUG_LSB                               29
+      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
+      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
+      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
+      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
+      #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
+      #define DMA1_CS_PANIC_PRIORITY_BITS                        23:20
+      #define DMA1_CS_PANIC_PRIORITY_SET                         0x00f00000
+      #define DMA1_CS_PANIC_PRIORITY_CLR                         0xff0fffff
+      #define DMA1_CS_PANIC_PRIORITY_MSB                         23
+      #define DMA1_CS_PANIC_PRIORITY_LSB                         20
+      #define DMA1_CS_PRIORITY_BITS                              19:16
+      #define DMA1_CS_PRIORITY_SET                               0x000f0000
+      #define DMA1_CS_PRIORITY_CLR                               0xfff0ffff
+      #define DMA1_CS_PRIORITY_MSB                               19
+      #define DMA1_CS_PRIORITY_LSB                               16
+      #define DMA1_CS_ERROR_BITS                                 8:8
+      #define DMA1_CS_ERROR_SET                                  0x00000100
+      #define DMA1_CS_ERROR_CLR                                  0xfffffeff
+      #define DMA1_CS_ERROR_MSB                                  8
+      #define DMA1_CS_ERROR_LSB                                  8
+      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
+      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
+      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
+      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
+      #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
+      #define DMA1_CS_DREQ_STOPS_DMA_BITS                        5:5
+      #define DMA1_CS_DREQ_STOPS_DMA_SET                         0x00000020
+      #define DMA1_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
+      #define DMA1_CS_DREQ_STOPS_DMA_MSB                         5
+      #define DMA1_CS_DREQ_STOPS_DMA_LSB                         5
+      #define DMA1_CS_PAUSED_BITS                                4:4
+      #define DMA1_CS_PAUSED_SET                                 0x00000010
+      #define DMA1_CS_PAUSED_CLR                                 0xffffffef
+      #define DMA1_CS_PAUSED_MSB                                 4
+      #define DMA1_CS_PAUSED_LSB                                 4
+      #define DMA1_CS_DREQ_BITS                                  3:3
+      #define DMA1_CS_DREQ_SET                                   0x00000008
+      #define DMA1_CS_DREQ_CLR                                   0xfffffff7
+      #define DMA1_CS_DREQ_MSB                                   3
+      #define DMA1_CS_DREQ_LSB                                   3
+      #define DMA1_CS_INT_BITS                                   2:2
+      #define DMA1_CS_INT_SET                                    0x00000004
+      #define DMA1_CS_INT_CLR                                    0xfffffffb
+      #define DMA1_CS_INT_MSB                                    2
+      #define DMA1_CS_INT_LSB                                    2
+      #define DMA1_CS_END_BITS                                   1:1
+      #define DMA1_CS_END_SET                                    0x00000002
+      #define DMA1_CS_END_CLR                                    0xfffffffd
+      #define DMA1_CS_END_MSB                                    1
+      #define DMA1_CS_END_LSB                                    1
+      #define DMA1_CS_ACTIVE_BITS                                0:0
+      #define DMA1_CS_ACTIVE_SET                                 0x00000001
+      #define DMA1_CS_ACTIVE_CLR                                 0xfffffffe
+      #define DMA1_CS_ACTIVE_MSB                                 0
+      #define DMA1_CS_ACTIVE_LSB                                 0
+#define DMA1_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007104 ) 
+   #define DMA1_CONBLK_AD_MASK                                   0xffffffe0
+   #define DMA1_CONBLK_AD_WIDTH                                  32
+   #define DMA1_CONBLK_AD_RESET                                  0000000000
+      #define DMA1_CONBLK_AD_SCB_ADDR_BITS                       31:5
+      #define DMA1_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
+      #define DMA1_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
+      #define DMA1_CONBLK_AD_SCB_ADDR_MSB                        31
+      #define DMA1_CONBLK_AD_SCB_ADDR_LSB                        5
+#define DMA1_TI                                                  HW_REGISTER_RO( 0x7e007108 ) 
+   #define DMA1_TI_MASK                                          0x07fffffb
+   #define DMA1_TI_WIDTH                                         27
+      #define DMA1_TI_NO_WIDE_BURSTS_BITS                        26:26
+      #define DMA1_TI_NO_WIDE_BURSTS_SET                         0x04000000
+      #define DMA1_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
+      #define DMA1_TI_NO_WIDE_BURSTS_MSB                         26
+      #define DMA1_TI_NO_WIDE_BURSTS_LSB                         26
+      #define DMA1_TI_WAITS_BITS                                 25:21
+      #define DMA1_TI_WAITS_SET                                  0x03e00000
+      #define DMA1_TI_WAITS_CLR                                  0xfc1fffff
+      #define DMA1_TI_WAITS_MSB                                  25
+      #define DMA1_TI_WAITS_LSB                                  21
+      #define DMA1_TI_PERMAP_BITS                                20:16
+      #define DMA1_TI_PERMAP_SET                                 0x001f0000
+      #define DMA1_TI_PERMAP_CLR                                 0xffe0ffff
+      #define DMA1_TI_PERMAP_MSB                                 20
+      #define DMA1_TI_PERMAP_LSB                                 16
+      #define DMA1_TI_BURST_LENGTH_BITS                          15:12
+      #define DMA1_TI_BURST_LENGTH_SET                           0x0000f000
+      #define DMA1_TI_BURST_LENGTH_CLR                           0xffff0fff
+      #define DMA1_TI_BURST_LENGTH_MSB                           15
+      #define DMA1_TI_BURST_LENGTH_LSB                           12
+      #define DMA1_TI_SRC_IGNORE_BITS                            11:11
+      #define DMA1_TI_SRC_IGNORE_SET                             0x00000800
+      #define DMA1_TI_SRC_IGNORE_CLR                             0xfffff7ff
+      #define DMA1_TI_SRC_IGNORE_MSB                             11
+      #define DMA1_TI_SRC_IGNORE_LSB                             11
+      #define DMA1_TI_SRC_DREQ_BITS                              10:10
+      #define DMA1_TI_SRC_DREQ_SET                               0x00000400
+      #define DMA1_TI_SRC_DREQ_CLR                               0xfffffbff
+      #define DMA1_TI_SRC_DREQ_MSB                               10
+      #define DMA1_TI_SRC_DREQ_LSB                               10
+      #define DMA1_TI_SRC_WIDTH_BITS                             9:9
+      #define DMA1_TI_SRC_WIDTH_SET                              0x00000200
+      #define DMA1_TI_SRC_WIDTH_CLR                              0xfffffdff
+      #define DMA1_TI_SRC_WIDTH_MSB                              9
+      #define DMA1_TI_SRC_WIDTH_LSB                              9
+      #define DMA1_TI_SRC_INC_BITS                               8:8
+      #define DMA1_TI_SRC_INC_SET                                0x00000100
+      #define DMA1_TI_SRC_INC_CLR                                0xfffffeff
+      #define DMA1_TI_SRC_INC_MSB                                8
+      #define DMA1_TI_SRC_INC_LSB                                8
+      #define DMA1_TI_DEST_IGNORE_BITS                           7:7
+      #define DMA1_TI_DEST_IGNORE_SET                            0x00000080
+      #define DMA1_TI_DEST_IGNORE_CLR                            0xffffff7f
+      #define DMA1_TI_DEST_IGNORE_MSB                            7
+      #define DMA1_TI_DEST_IGNORE_LSB                            7
+      #define DMA1_TI_DEST_DREQ_BITS                             6:6
+      #define DMA1_TI_DEST_DREQ_SET                              0x00000040
+      #define DMA1_TI_DEST_DREQ_CLR                              0xffffffbf
+      #define DMA1_TI_DEST_DREQ_MSB                              6
+      #define DMA1_TI_DEST_DREQ_LSB                              6
+      #define DMA1_TI_DEST_WIDTH_BITS                            5:5
+      #define DMA1_TI_DEST_WIDTH_SET                             0x00000020
+      #define DMA1_TI_DEST_WIDTH_CLR                             0xffffffdf
+      #define DMA1_TI_DEST_WIDTH_MSB                             5
+      #define DMA1_TI_DEST_WIDTH_LSB                             5
+      #define DMA1_TI_DEST_INC_BITS                              4:4
+      #define DMA1_TI_DEST_INC_SET                               0x00000010
+      #define DMA1_TI_DEST_INC_CLR                               0xffffffef
+      #define DMA1_TI_DEST_INC_MSB                               4
+      #define DMA1_TI_DEST_INC_LSB                               4
+      #define DMA1_TI_WAIT_RESP_BITS                             3:3
+      #define DMA1_TI_WAIT_RESP_SET                              0x00000008
+      #define DMA1_TI_WAIT_RESP_CLR                              0xfffffff7
+      #define DMA1_TI_WAIT_RESP_MSB                              3
+      #define DMA1_TI_WAIT_RESP_LSB                              3
+      #define DMA1_TI_TDMODE_BITS                                1:1
+      #define DMA1_TI_TDMODE_SET                                 0x00000002
+      #define DMA1_TI_TDMODE_CLR                                 0xfffffffd
+      #define DMA1_TI_TDMODE_MSB                                 1
+      #define DMA1_TI_TDMODE_LSB                                 1
+      #define DMA1_TI_INTEN_BITS                                 0:0
+      #define DMA1_TI_INTEN_SET                                  0x00000001
+      #define DMA1_TI_INTEN_CLR                                  0xfffffffe
+      #define DMA1_TI_INTEN_MSB                                  0
+      #define DMA1_TI_INTEN_LSB                                  0
+#define DMA1_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00710c ) 
+   #define DMA1_SOURCE_AD_MASK                                   0xffffffff
+   #define DMA1_SOURCE_AD_WIDTH                                  32
+      #define DMA1_SOURCE_AD_S_ADDR_BITS                         31:0
+      #define DMA1_SOURCE_AD_S_ADDR_SET                          0xffffffff
+      #define DMA1_SOURCE_AD_S_ADDR_CLR                          0x00000000
+      #define DMA1_SOURCE_AD_S_ADDR_MSB                          31
+      #define DMA1_SOURCE_AD_S_ADDR_LSB                          0
+#define DMA1_DEST_AD                                             HW_REGISTER_RO( 0x7e007110 ) 
+   #define DMA1_DEST_AD_MASK                                     0xffffffff
+   #define DMA1_DEST_AD_WIDTH                                    32
+      #define DMA1_DEST_AD_D_ADDR_BITS                           31:0
+      #define DMA1_DEST_AD_D_ADDR_SET                            0xffffffff
+      #define DMA1_DEST_AD_D_ADDR_CLR                            0x00000000
+      #define DMA1_DEST_AD_D_ADDR_MSB                            31
+      #define DMA1_DEST_AD_D_ADDR_LSB                            0
+#define DMA1_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007114 ) 
+   #define DMA1_TXFR_LEN_MASK                                    0x3fffffff
+   #define DMA1_TXFR_LEN_WIDTH                                   30
+      #define DMA1_TXFR_LEN_YLENGTH_BITS                         29:16
+      #define DMA1_TXFR_LEN_YLENGTH_SET                          0x3fff0000
+      #define DMA1_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
+      #define DMA1_TXFR_LEN_YLENGTH_MSB                          29
+      #define DMA1_TXFR_LEN_YLENGTH_LSB                          16
+      #define DMA1_TXFR_LEN_XLENGTH_BITS                         15:0
+      #define DMA1_TXFR_LEN_XLENGTH_SET                          0x0000ffff
+      #define DMA1_TXFR_LEN_XLENGTH_CLR                          0xffff0000
+      #define DMA1_TXFR_LEN_XLENGTH_MSB                          15
+      #define DMA1_TXFR_LEN_XLENGTH_LSB                          0
+#define DMA1_STRIDE                                              HW_REGISTER_RO( 0x7e007118 ) 
+   #define DMA1_STRIDE_MASK                                      0xffffffff
+   #define DMA1_STRIDE_WIDTH                                     32
+      #define DMA1_STRIDE_D_STRIDE_BITS                          31:16
+      #define DMA1_STRIDE_D_STRIDE_SET                           0xffff0000
+      #define DMA1_STRIDE_D_STRIDE_CLR                           0x0000ffff
+      #define DMA1_STRIDE_D_STRIDE_MSB                           31
+      #define DMA1_STRIDE_D_STRIDE_LSB                           16
+      #define DMA1_STRIDE_S_STRIDE_BITS                          15:0
+      #define DMA1_STRIDE_S_STRIDE_SET                           0x0000ffff
+      #define DMA1_STRIDE_S_STRIDE_CLR                           0xffff0000
+      #define DMA1_STRIDE_S_STRIDE_MSB                           15
+      #define DMA1_STRIDE_S_STRIDE_LSB                           0
+#define DMA1_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00711c ) 
+   #define DMA1_NEXTCONBK_MASK                                   0xffffffe0
+   #define DMA1_NEXTCONBK_WIDTH                                  32
+      #define DMA1_NEXTCONBK_ADDR_BITS                           31:5
+      #define DMA1_NEXTCONBK_ADDR_SET                            0xffffffe0
+      #define DMA1_NEXTCONBK_ADDR_CLR                            0x0000001f
+      #define DMA1_NEXTCONBK_ADDR_MSB                            31
+      #define DMA1_NEXTCONBK_ADDR_LSB                            5
+#define DMA1_DEBUG                                               HW_REGISTER_RW( 0x7e007120 ) 
+   #define DMA1_DEBUG_MASK                                       0x1ffffff7
+   #define DMA1_DEBUG_WIDTH                                      29
+   #define DMA1_DEBUG_RESET                                      0000000000
+      #define DMA1_DEBUG_LITE_BITS                               28:28
+      #define DMA1_DEBUG_LITE_SET                                0x10000000
+      #define DMA1_DEBUG_LITE_CLR                                0xefffffff
+      #define DMA1_DEBUG_LITE_MSB                                28
+      #define DMA1_DEBUG_LITE_LSB                                28
+      #define DMA1_DEBUG_VERSION_BITS                            27:25
+      #define DMA1_DEBUG_VERSION_SET                             0x0e000000
+      #define DMA1_DEBUG_VERSION_CLR                             0xf1ffffff
+      #define DMA1_DEBUG_VERSION_MSB                             27
+      #define DMA1_DEBUG_VERSION_LSB                             25
+      #define DMA1_DEBUG_DMA_STATE_BITS                          24:16
+      #define DMA1_DEBUG_DMA_STATE_SET                           0x01ff0000
+      #define DMA1_DEBUG_DMA_STATE_CLR                           0xfe00ffff
+      #define DMA1_DEBUG_DMA_STATE_MSB                           24
+      #define DMA1_DEBUG_DMA_STATE_LSB                           16
+      #define DMA1_DEBUG_DMA_ID_BITS                             15:8
+      #define DMA1_DEBUG_DMA_ID_SET                              0x0000ff00
+      #define DMA1_DEBUG_DMA_ID_CLR                              0xffff00ff
+      #define DMA1_DEBUG_DMA_ID_MSB                              15
+      #define DMA1_DEBUG_DMA_ID_LSB                              8
+      #define DMA1_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
+      #define DMA1_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
+      #define DMA1_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
+      #define DMA1_DEBUG_OUTSTANDING_WRITES_MSB                  7
+      #define DMA1_DEBUG_OUTSTANDING_WRITES_LSB                  4
+      #define DMA1_DEBUG_READ_ERROR_BITS                         2:2
+      #define DMA1_DEBUG_READ_ERROR_SET                          0x00000004
+      #define DMA1_DEBUG_READ_ERROR_CLR                          0xfffffffb
+      #define DMA1_DEBUG_READ_ERROR_MSB                          2
+      #define DMA1_DEBUG_READ_ERROR_LSB                          2
+      #define DMA1_DEBUG_FIFO_ERROR_BITS                         1:1
+      #define DMA1_DEBUG_FIFO_ERROR_SET                          0x00000002
+      #define DMA1_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
+      #define DMA1_DEBUG_FIFO_ERROR_MSB                          1
+      #define DMA1_DEBUG_FIFO_ERROR_LSB                          1
+      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
+      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
+      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
+      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
+      #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma15.h b/bcm2708_chip/axi_dma15.h
new file mode 100755 (executable)
index 0000000..170f80c
--- /dev/null
@@ -0,0 +1,257 @@
+// This file was generated by the create_regs script
+#define DMA15_BASE                                               0x7ee05000
+#define DMA15_CS                                                 HW_REGISTER_RW( 0x7ee05000 ) 
+   #define DMA15_CS_MASK                                         0xf0ff017f
+   #define DMA15_CS_WIDTH                                        32
+   #define DMA15_CS_RESET                                        0000000000
+      #define DMA15_CS_RESET_BITS                                31:31
+      #define DMA15_CS_RESET_SET                                 0x80000000
+      #define DMA15_CS_RESET_CLR                                 0x7fffffff
+      #define DMA15_CS_RESET_MSB                                 31
+      #define DMA15_CS_RESET_LSB                                 31
+      #define DMA15_CS_ABORT_BITS                                30:30
+      #define DMA15_CS_ABORT_SET                                 0x40000000
+      #define DMA15_CS_ABORT_CLR                                 0xbfffffff
+      #define DMA15_CS_ABORT_MSB                                 30
+      #define DMA15_CS_ABORT_LSB                                 30
+      #define DMA15_CS_DISDEBUG_BITS                             29:29
+      #define DMA15_CS_DISDEBUG_SET                              0x20000000
+      #define DMA15_CS_DISDEBUG_CLR                              0xdfffffff
+      #define DMA15_CS_DISDEBUG_MSB                              29
+      #define DMA15_CS_DISDEBUG_LSB                              29
+      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS          28:28
+      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_SET           0x10000000
+      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR           0xefffffff
+      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB           28
+      #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB           28
+      #define DMA15_CS_PANIC_PRIORITY_BITS                       23:20
+      #define DMA15_CS_PANIC_PRIORITY_SET                        0x00f00000
+      #define DMA15_CS_PANIC_PRIORITY_CLR                        0xff0fffff
+      #define DMA15_CS_PANIC_PRIORITY_MSB                        23
+      #define DMA15_CS_PANIC_PRIORITY_LSB                        20
+      #define DMA15_CS_PRIORITY_BITS                             19:16
+      #define DMA15_CS_PRIORITY_SET                              0x000f0000
+      #define DMA15_CS_PRIORITY_CLR                              0xfff0ffff
+      #define DMA15_CS_PRIORITY_MSB                              19
+      #define DMA15_CS_PRIORITY_LSB                              16
+      #define DMA15_CS_ERROR_BITS                                8:8
+      #define DMA15_CS_ERROR_SET                                 0x00000100
+      #define DMA15_CS_ERROR_CLR                                 0xfffffeff
+      #define DMA15_CS_ERROR_MSB                                 8
+      #define DMA15_CS_ERROR_LSB                                 8
+      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS       6:6
+      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_SET        0x00000040
+      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR        0xffffffbf
+      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB        6
+      #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB        6
+      #define DMA15_CS_DREQ_STOPS_DMA_BITS                       5:5
+      #define DMA15_CS_DREQ_STOPS_DMA_SET                        0x00000020
+      #define DMA15_CS_DREQ_STOPS_DMA_CLR                        0xffffffdf
+      #define DMA15_CS_DREQ_STOPS_DMA_MSB                        5
+      #define DMA15_CS_DREQ_STOPS_DMA_LSB                        5
+      #define DMA15_CS_PAUSED_BITS                               4:4
+      #define DMA15_CS_PAUSED_SET                                0x00000010
+      #define DMA15_CS_PAUSED_CLR                                0xffffffef
+      #define DMA15_CS_PAUSED_MSB                                4
+      #define DMA15_CS_PAUSED_LSB                                4
+      #define DMA15_CS_DREQ_BITS                                 3:3
+      #define DMA15_CS_DREQ_SET                                  0x00000008
+      #define DMA15_CS_DREQ_CLR                                  0xfffffff7
+      #define DMA15_CS_DREQ_MSB                                  3
+      #define DMA15_CS_DREQ_LSB                                  3
+      #define DMA15_CS_INT_BITS                                  2:2
+      #define DMA15_CS_INT_SET                                   0x00000004
+      #define DMA15_CS_INT_CLR                                   0xfffffffb
+      #define DMA15_CS_INT_MSB                                   2
+      #define DMA15_CS_INT_LSB                                   2
+      #define DMA15_CS_END_BITS                                  1:1
+      #define DMA15_CS_END_SET                                   0x00000002
+      #define DMA15_CS_END_CLR                                   0xfffffffd
+      #define DMA15_CS_END_MSB                                   1
+      #define DMA15_CS_END_LSB                                   1
+      #define DMA15_CS_ACTIVE_BITS                               0:0
+      #define DMA15_CS_ACTIVE_SET                                0x00000001
+      #define DMA15_CS_ACTIVE_CLR                                0xfffffffe
+      #define DMA15_CS_ACTIVE_MSB                                0
+      #define DMA15_CS_ACTIVE_LSB                                0
+#define DMA15_CONBLK_AD                                          HW_REGISTER_RW( 0x7ee05004 ) 
+   #define DMA15_CONBLK_AD_MASK                                  0xffffffe0
+   #define DMA15_CONBLK_AD_WIDTH                                 32
+   #define DMA15_CONBLK_AD_RESET                                 0000000000
+      #define DMA15_CONBLK_AD_SCB_ADDR_BITS                      31:5
+      #define DMA15_CONBLK_AD_SCB_ADDR_SET                       0xffffffe0
+      #define DMA15_CONBLK_AD_SCB_ADDR_CLR                       0x0000001f
+      #define DMA15_CONBLK_AD_SCB_ADDR_MSB                       31
+      #define DMA15_CONBLK_AD_SCB_ADDR_LSB                       5
+#define DMA15_TI                                                 HW_REGISTER_RO( 0x7ee05008 ) 
+   #define DMA15_TI_MASK                                         0x07fffffb
+   #define DMA15_TI_WIDTH                                        27
+      #define DMA15_TI_NO_WIDE_BURSTS_BITS                       26:26
+      #define DMA15_TI_NO_WIDE_BURSTS_SET                        0x04000000
+      #define DMA15_TI_NO_WIDE_BURSTS_CLR                        0xfbffffff
+      #define DMA15_TI_NO_WIDE_BURSTS_MSB                        26
+      #define DMA15_TI_NO_WIDE_BURSTS_LSB                        26
+      #define DMA15_TI_WAITS_BITS                                25:21
+      #define DMA15_TI_WAITS_SET                                 0x03e00000
+      #define DMA15_TI_WAITS_CLR                                 0xfc1fffff
+      #define DMA15_TI_WAITS_MSB                                 25
+      #define DMA15_TI_WAITS_LSB                                 21
+      #define DMA15_TI_PERMAP_BITS                               20:16
+      #define DMA15_TI_PERMAP_SET                                0x001f0000
+      #define DMA15_TI_PERMAP_CLR                                0xffe0ffff
+      #define DMA15_TI_PERMAP_MSB                                20
+      #define DMA15_TI_PERMAP_LSB                                16
+      #define DMA15_TI_BURST_LENGTH_BITS                         15:12
+      #define DMA15_TI_BURST_LENGTH_SET                          0x0000f000
+      #define DMA15_TI_BURST_LENGTH_CLR                          0xffff0fff
+      #define DMA15_TI_BURST_LENGTH_MSB                          15
+      #define DMA15_TI_BURST_LENGTH_LSB                          12
+      #define DMA15_TI_SRC_IGNORE_BITS                           11:11
+      #define DMA15_TI_SRC_IGNORE_SET                            0x00000800
+      #define DMA15_TI_SRC_IGNORE_CLR                            0xfffff7ff
+      #define DMA15_TI_SRC_IGNORE_MSB                            11
+      #define DMA15_TI_SRC_IGNORE_LSB                            11
+      #define DMA15_TI_SRC_DREQ_BITS                             10:10
+      #define DMA15_TI_SRC_DREQ_SET                              0x00000400
+      #define DMA15_TI_SRC_DREQ_CLR                              0xfffffbff
+      #define DMA15_TI_SRC_DREQ_MSB                              10
+      #define DMA15_TI_SRC_DREQ_LSB                              10
+      #define DMA15_TI_SRC_WIDTH_BITS                            9:9
+      #define DMA15_TI_SRC_WIDTH_SET                             0x00000200
+      #define DMA15_TI_SRC_WIDTH_CLR                             0xfffffdff
+      #define DMA15_TI_SRC_WIDTH_MSB                             9
+      #define DMA15_TI_SRC_WIDTH_LSB                             9
+      #define DMA15_TI_SRC_INC_BITS                              8:8
+      #define DMA15_TI_SRC_INC_SET                               0x00000100
+      #define DMA15_TI_SRC_INC_CLR                               0xfffffeff
+      #define DMA15_TI_SRC_INC_MSB                               8
+      #define DMA15_TI_SRC_INC_LSB                               8
+      #define DMA15_TI_DEST_IGNORE_BITS                          7:7
+      #define DMA15_TI_DEST_IGNORE_SET                           0x00000080
+      #define DMA15_TI_DEST_IGNORE_CLR                           0xffffff7f
+      #define DMA15_TI_DEST_IGNORE_MSB                           7
+      #define DMA15_TI_DEST_IGNORE_LSB                           7
+      #define DMA15_TI_DEST_DREQ_BITS                            6:6
+      #define DMA15_TI_DEST_DREQ_SET                             0x00000040
+      #define DMA15_TI_DEST_DREQ_CLR                             0xffffffbf
+      #define DMA15_TI_DEST_DREQ_MSB                             6
+      #define DMA15_TI_DEST_DREQ_LSB                             6
+      #define DMA15_TI_DEST_WIDTH_BITS                           5:5
+      #define DMA15_TI_DEST_WIDTH_SET                            0x00000020
+      #define DMA15_TI_DEST_WIDTH_CLR                            0xffffffdf
+      #define DMA15_TI_DEST_WIDTH_MSB                            5
+      #define DMA15_TI_DEST_WIDTH_LSB                            5
+      #define DMA15_TI_DEST_INC_BITS                             4:4
+      #define DMA15_TI_DEST_INC_SET                              0x00000010
+      #define DMA15_TI_DEST_INC_CLR                              0xffffffef
+      #define DMA15_TI_DEST_INC_MSB                              4
+      #define DMA15_TI_DEST_INC_LSB                              4
+      #define DMA15_TI_WAIT_RESP_BITS                            3:3
+      #define DMA15_TI_WAIT_RESP_SET                             0x00000008
+      #define DMA15_TI_WAIT_RESP_CLR                             0xfffffff7
+      #define DMA15_TI_WAIT_RESP_MSB                             3
+      #define DMA15_TI_WAIT_RESP_LSB                             3
+      #define DMA15_TI_TDMODE_BITS                               1:1
+      #define DMA15_TI_TDMODE_SET                                0x00000002
+      #define DMA15_TI_TDMODE_CLR                                0xfffffffd
+      #define DMA15_TI_TDMODE_MSB                                1
+      #define DMA15_TI_TDMODE_LSB                                1
+      #define DMA15_TI_INTEN_BITS                                0:0
+      #define DMA15_TI_INTEN_SET                                 0x00000001
+      #define DMA15_TI_INTEN_CLR                                 0xfffffffe
+      #define DMA15_TI_INTEN_MSB                                 0
+      #define DMA15_TI_INTEN_LSB                                 0
+#define DMA15_SOURCE_AD                                          HW_REGISTER_RO( 0x7ee0500c ) 
+   #define DMA15_SOURCE_AD_MASK                                  0xffffffff
+   #define DMA15_SOURCE_AD_WIDTH                                 32
+      #define DMA15_SOURCE_AD_S_ADDR_BITS                        31:0
+      #define DMA15_SOURCE_AD_S_ADDR_SET                         0xffffffff
+      #define DMA15_SOURCE_AD_S_ADDR_CLR                         0x00000000
+      #define DMA15_SOURCE_AD_S_ADDR_MSB                         31
+      #define DMA15_SOURCE_AD_S_ADDR_LSB                         0
+#define DMA15_DEST_AD                                            HW_REGISTER_RO( 0x7ee05010 ) 
+   #define DMA15_DEST_AD_MASK                                    0xffffffff
+   #define DMA15_DEST_AD_WIDTH                                   32
+      #define DMA15_DEST_AD_D_ADDR_BITS                          31:0
+      #define DMA15_DEST_AD_D_ADDR_SET                           0xffffffff
+      #define DMA15_DEST_AD_D_ADDR_CLR                           0x00000000
+      #define DMA15_DEST_AD_D_ADDR_MSB                           31
+      #define DMA15_DEST_AD_D_ADDR_LSB                           0
+#define DMA15_TXFR_LEN                                           HW_REGISTER_RO( 0x7ee05014 ) 
+   #define DMA15_TXFR_LEN_MASK                                   0x3fffffff
+   #define DMA15_TXFR_LEN_WIDTH                                  30
+      #define DMA15_TXFR_LEN_YLENGTH_BITS                        29:16
+      #define DMA15_TXFR_LEN_YLENGTH_SET                         0x3fff0000
+      #define DMA15_TXFR_LEN_YLENGTH_CLR                         0xc000ffff
+      #define DMA15_TXFR_LEN_YLENGTH_MSB                         29
+      #define DMA15_TXFR_LEN_YLENGTH_LSB                         16
+      #define DMA15_TXFR_LEN_XLENGTH_BITS                        15:0
+      #define DMA15_TXFR_LEN_XLENGTH_SET                         0x0000ffff
+      #define DMA15_TXFR_LEN_XLENGTH_CLR                         0xffff0000
+      #define DMA15_TXFR_LEN_XLENGTH_MSB                         15
+      #define DMA15_TXFR_LEN_XLENGTH_LSB                         0
+#define DMA15_STRIDE                                             HW_REGISTER_RO( 0x7ee05018 ) 
+   #define DMA15_STRIDE_MASK                                     0xffffffff
+   #define DMA15_STRIDE_WIDTH                                    32
+      #define DMA15_STRIDE_D_STRIDE_BITS                         31:16
+      #define DMA15_STRIDE_D_STRIDE_SET                          0xffff0000
+      #define DMA15_STRIDE_D_STRIDE_CLR                          0x0000ffff
+      #define DMA15_STRIDE_D_STRIDE_MSB                          31
+      #define DMA15_STRIDE_D_STRIDE_LSB                          16
+      #define DMA15_STRIDE_S_STRIDE_BITS                         15:0
+      #define DMA15_STRIDE_S_STRIDE_SET                          0x0000ffff
+      #define DMA15_STRIDE_S_STRIDE_CLR                          0xffff0000
+      #define DMA15_STRIDE_S_STRIDE_MSB                          15
+      #define DMA15_STRIDE_S_STRIDE_LSB                          0
+#define DMA15_NEXTCONBK                                          HW_REGISTER_RO( 0x7ee0501c ) 
+   #define DMA15_NEXTCONBK_MASK                                  0xffffffe0
+   #define DMA15_NEXTCONBK_WIDTH                                 32
+      #define DMA15_NEXTCONBK_ADDR_BITS                          31:5
+      #define DMA15_NEXTCONBK_ADDR_SET                           0xffffffe0
+      #define DMA15_NEXTCONBK_ADDR_CLR                           0x0000001f
+      #define DMA15_NEXTCONBK_ADDR_MSB                           31
+      #define DMA15_NEXTCONBK_ADDR_LSB                           5
+#define DMA15_DEBUG                                              HW_REGISTER_RW( 0x7ee05020 ) 
+   #define DMA15_DEBUG_MASK                                      0x1ffffff7
+   #define DMA15_DEBUG_WIDTH                                     29
+   #define DMA15_DEBUG_RESET                                     0000000000
+      #define DMA15_DEBUG_LITE_BITS                              28:28
+      #define DMA15_DEBUG_LITE_SET                               0x10000000
+      #define DMA15_DEBUG_LITE_CLR                               0xefffffff
+      #define DMA15_DEBUG_LITE_MSB                               28
+      #define DMA15_DEBUG_LITE_LSB                               28
+      #define DMA15_DEBUG_VERSION_BITS                           27:25
+      #define DMA15_DEBUG_VERSION_SET                            0x0e000000
+      #define DMA15_DEBUG_VERSION_CLR                            0xf1ffffff
+      #define DMA15_DEBUG_VERSION_MSB                            27
+      #define DMA15_DEBUG_VERSION_LSB                            25
+      #define DMA15_DEBUG_DMA_STATE_BITS                         24:16
+      #define DMA15_DEBUG_DMA_STATE_SET                          0x01ff0000
+      #define DMA15_DEBUG_DMA_STATE_CLR                          0xfe00ffff
+      #define DMA15_DEBUG_DMA_STATE_MSB                          24
+      #define DMA15_DEBUG_DMA_STATE_LSB                          16
+      #define DMA15_DEBUG_DMA_ID_BITS                            15:8
+      #define DMA15_DEBUG_DMA_ID_SET                             0x0000ff00
+      #define DMA15_DEBUG_DMA_ID_CLR                             0xffff00ff
+      #define DMA15_DEBUG_DMA_ID_MSB                             15
+      #define DMA15_DEBUG_DMA_ID_LSB                             8
+      #define DMA15_DEBUG_OUTSTANDING_WRITES_BITS                7:4
+      #define DMA15_DEBUG_OUTSTANDING_WRITES_SET                 0x000000f0
+      #define DMA15_DEBUG_OUTSTANDING_WRITES_CLR                 0xffffff0f
+      #define DMA15_DEBUG_OUTSTANDING_WRITES_MSB                 7
+      #define DMA15_DEBUG_OUTSTANDING_WRITES_LSB                 4
+      #define DMA15_DEBUG_READ_ERROR_BITS                        2:2
+      #define DMA15_DEBUG_READ_ERROR_SET                         0x00000004
+      #define DMA15_DEBUG_READ_ERROR_CLR                         0xfffffffb
+      #define DMA15_DEBUG_READ_ERROR_MSB                         2
+      #define DMA15_DEBUG_READ_ERROR_LSB                         2
+      #define DMA15_DEBUG_FIFO_ERROR_BITS                        1:1
+      #define DMA15_DEBUG_FIFO_ERROR_SET                         0x00000002
+      #define DMA15_DEBUG_FIFO_ERROR_CLR                         0xfffffffd
+      #define DMA15_DEBUG_FIFO_ERROR_MSB                         1
+      #define DMA15_DEBUG_FIFO_ERROR_LSB                         1
+      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_BITS           0:0
+      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_SET            0x00000001
+      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_CLR            0xfffffffe
+      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_MSB            0
+      #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_LSB            0
diff --git a/bcm2708_chip/axi_dma2.h b/bcm2708_chip/axi_dma2.h
new file mode 100755 (executable)
index 0000000..81b4ed9
--- /dev/null
@@ -0,0 +1,257 @@
+// This file was generated by the create_regs script
+#define DMA2_BASE                                                0x7e007200
+#define DMA2_CS                                                  HW_REGISTER_RW( 0x7e007200 ) 
+   #define DMA2_CS_MASK                                          0xf0ff017f
+   #define DMA2_CS_WIDTH                                         32
+   #define DMA2_CS_RESET                                         0000000000
+      #define DMA2_CS_RESET_BITS                                 31:31
+      #define DMA2_CS_RESET_SET                                  0x80000000
+      #define DMA2_CS_RESET_CLR                                  0x7fffffff
+      #define DMA2_CS_RESET_MSB                                  31
+      #define DMA2_CS_RESET_LSB                                  31
+      #define DMA2_CS_ABORT_BITS                                 30:30
+      #define DMA2_CS_ABORT_SET                                  0x40000000
+      #define DMA2_CS_ABORT_CLR                                  0xbfffffff
+      #define DMA2_CS_ABORT_MSB                                  30
+      #define DMA2_CS_ABORT_LSB                                  30
+      #define DMA2_CS_DISDEBUG_BITS                              29:29
+      #define DMA2_CS_DISDEBUG_SET                               0x20000000
+      #define DMA2_CS_DISDEBUG_CLR                               0xdfffffff
+      #define DMA2_CS_DISDEBUG_MSB                               29
+      #define DMA2_CS_DISDEBUG_LSB                               29
+      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
+      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
+      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
+      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
+      #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
+      #define DMA2_CS_PANIC_PRIORITY_BITS                        23:20
+      #define DMA2_CS_PANIC_PRIORITY_SET                         0x00f00000
+      #define DMA2_CS_PANIC_PRIORITY_CLR                         0xff0fffff
+      #define DMA2_CS_PANIC_PRIORITY_MSB                         23
+      #define DMA2_CS_PANIC_PRIORITY_LSB                         20
+      #define DMA2_CS_PRIORITY_BITS                              19:16
+      #define DMA2_CS_PRIORITY_SET                               0x000f0000
+      #define DMA2_CS_PRIORITY_CLR                               0xfff0ffff
+      #define DMA2_CS_PRIORITY_MSB                               19
+      #define DMA2_CS_PRIORITY_LSB                               16
+      #define DMA2_CS_ERROR_BITS                                 8:8
+      #define DMA2_CS_ERROR_SET                                  0x00000100
+      #define DMA2_CS_ERROR_CLR                                  0xfffffeff
+      #define DMA2_CS_ERROR_MSB                                  8
+      #define DMA2_CS_ERROR_LSB                                  8
+      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
+      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
+      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
+      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
+      #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
+      #define DMA2_CS_DREQ_STOPS_DMA_BITS                        5:5
+      #define DMA2_CS_DREQ_STOPS_DMA_SET                         0x00000020
+      #define DMA2_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
+      #define DMA2_CS_DREQ_STOPS_DMA_MSB                         5
+      #define DMA2_CS_DREQ_STOPS_DMA_LSB                         5
+      #define DMA2_CS_PAUSED_BITS                                4:4
+      #define DMA2_CS_PAUSED_SET                                 0x00000010
+      #define DMA2_CS_PAUSED_CLR                                 0xffffffef
+      #define DMA2_CS_PAUSED_MSB                                 4
+      #define DMA2_CS_PAUSED_LSB                                 4
+      #define DMA2_CS_DREQ_BITS                                  3:3
+      #define DMA2_CS_DREQ_SET                                   0x00000008
+      #define DMA2_CS_DREQ_CLR                                   0xfffffff7
+      #define DMA2_CS_DREQ_MSB                                   3
+      #define DMA2_CS_DREQ_LSB                                   3
+      #define DMA2_CS_INT_BITS                                   2:2
+      #define DMA2_CS_INT_SET                                    0x00000004
+      #define DMA2_CS_INT_CLR                                    0xfffffffb
+      #define DMA2_CS_INT_MSB                                    2
+      #define DMA2_CS_INT_LSB                                    2
+      #define DMA2_CS_END_BITS                                   1:1
+      #define DMA2_CS_END_SET                                    0x00000002
+      #define DMA2_CS_END_CLR                                    0xfffffffd
+      #define DMA2_CS_END_MSB                                    1
+      #define DMA2_CS_END_LSB                                    1
+      #define DMA2_CS_ACTIVE_BITS                                0:0
+      #define DMA2_CS_ACTIVE_SET                                 0x00000001
+      #define DMA2_CS_ACTIVE_CLR                                 0xfffffffe
+      #define DMA2_CS_ACTIVE_MSB                                 0
+      #define DMA2_CS_ACTIVE_LSB                                 0
+#define DMA2_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007204 ) 
+   #define DMA2_CONBLK_AD_MASK                                   0xffffffe0
+   #define DMA2_CONBLK_AD_WIDTH                                  32
+   #define DMA2_CONBLK_AD_RESET                                  0000000000
+      #define DMA2_CONBLK_AD_SCB_ADDR_BITS                       31:5
+      #define DMA2_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
+      #define DMA2_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
+      #define DMA2_CONBLK_AD_SCB_ADDR_MSB                        31
+      #define DMA2_CONBLK_AD_SCB_ADDR_LSB                        5
+#define DMA2_TI                                                  HW_REGISTER_RO( 0x7e007208 ) 
+   #define DMA2_TI_MASK                                          0x07fffffb
+   #define DMA2_TI_WIDTH                                         27
+      #define DMA2_TI_NO_WIDE_BURSTS_BITS                        26:26
+      #define DMA2_TI_NO_WIDE_BURSTS_SET                         0x04000000
+      #define DMA2_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
+      #define DMA2_TI_NO_WIDE_BURSTS_MSB                         26
+      #define DMA2_TI_NO_WIDE_BURSTS_LSB                         26
+      #define DMA2_TI_WAITS_BITS                                 25:21
+      #define DMA2_TI_WAITS_SET                                  0x03e00000
+      #define DMA2_TI_WAITS_CLR                                  0xfc1fffff
+      #define DMA2_TI_WAITS_MSB                                  25
+      #define DMA2_TI_WAITS_LSB                                  21
+      #define DMA2_TI_PERMAP_BITS                                20:16
+      #define DMA2_TI_PERMAP_SET                                 0x001f0000
+      #define DMA2_TI_PERMAP_CLR                                 0xffe0ffff
+      #define DMA2_TI_PERMAP_MSB                                 20
+      #define DMA2_TI_PERMAP_LSB                                 16
+      #define DMA2_TI_BURST_LENGTH_BITS                          15:12
+      #define DMA2_TI_BURST_LENGTH_SET                           0x0000f000
+      #define DMA2_TI_BURST_LENGTH_CLR                           0xffff0fff
+      #define DMA2_TI_BURST_LENGTH_MSB                           15
+      #define DMA2_TI_BURST_LENGTH_LSB                           12
+      #define DMA2_TI_SRC_IGNORE_BITS                            11:11
+      #define DMA2_TI_SRC_IGNORE_SET                             0x00000800
+      #define DMA2_TI_SRC_IGNORE_CLR                             0xfffff7ff
+      #define DMA2_TI_SRC_IGNORE_MSB                             11
+      #define DMA2_TI_SRC_IGNORE_LSB                             11
+      #define DMA2_TI_SRC_DREQ_BITS                              10:10
+      #define DMA2_TI_SRC_DREQ_SET                               0x00000400
+      #define DMA2_TI_SRC_DREQ_CLR                               0xfffffbff
+      #define DMA2_TI_SRC_DREQ_MSB                               10
+      #define DMA2_TI_SRC_DREQ_LSB                               10
+      #define DMA2_TI_SRC_WIDTH_BITS                             9:9
+      #define DMA2_TI_SRC_WIDTH_SET                              0x00000200
+      #define DMA2_TI_SRC_WIDTH_CLR                              0xfffffdff
+      #define DMA2_TI_SRC_WIDTH_MSB                              9
+      #define DMA2_TI_SRC_WIDTH_LSB                              9
+      #define DMA2_TI_SRC_INC_BITS                               8:8
+      #define DMA2_TI_SRC_INC_SET                                0x00000100
+      #define DMA2_TI_SRC_INC_CLR                                0xfffffeff
+      #define DMA2_TI_SRC_INC_MSB                                8
+      #define DMA2_TI_SRC_INC_LSB                                8
+      #define DMA2_TI_DEST_IGNORE_BITS                           7:7
+      #define DMA2_TI_DEST_IGNORE_SET                            0x00000080
+      #define DMA2_TI_DEST_IGNORE_CLR                            0xffffff7f
+      #define DMA2_TI_DEST_IGNORE_MSB                            7
+      #define DMA2_TI_DEST_IGNORE_LSB                            7
+      #define DMA2_TI_DEST_DREQ_BITS                             6:6
+      #define DMA2_TI_DEST_DREQ_SET                              0x00000040
+      #define DMA2_TI_DEST_DREQ_CLR                              0xffffffbf
+      #define DMA2_TI_DEST_DREQ_MSB                              6
+      #define DMA2_TI_DEST_DREQ_LSB                              6
+      #define DMA2_TI_DEST_WIDTH_BITS                            5:5
+      #define DMA2_TI_DEST_WIDTH_SET                             0x00000020
+      #define DMA2_TI_DEST_WIDTH_CLR                             0xffffffdf
+      #define DMA2_TI_DEST_WIDTH_MSB                             5
+      #define DMA2_TI_DEST_WIDTH_LSB                             5
+      #define DMA2_TI_DEST_INC_BITS                              4:4
+      #define DMA2_TI_DEST_INC_SET                               0x00000010
+      #define DMA2_TI_DEST_INC_CLR                               0xffffffef
+      #define DMA2_TI_DEST_INC_MSB                               4
+      #define DMA2_TI_DEST_INC_LSB                               4
+      #define DMA2_TI_WAIT_RESP_BITS                             3:3
+      #define DMA2_TI_WAIT_RESP_SET                              0x00000008
+      #define DMA2_TI_WAIT_RESP_CLR                              0xfffffff7
+      #define DMA2_TI_WAIT_RESP_MSB                              3
+      #define DMA2_TI_WAIT_RESP_LSB                              3
+      #define DMA2_TI_TDMODE_BITS                                1:1
+      #define DMA2_TI_TDMODE_SET                                 0x00000002
+      #define DMA2_TI_TDMODE_CLR                                 0xfffffffd
+      #define DMA2_TI_TDMODE_MSB                                 1
+      #define DMA2_TI_TDMODE_LSB                                 1
+      #define DMA2_TI_INTEN_BITS                                 0:0
+      #define DMA2_TI_INTEN_SET                                  0x00000001
+      #define DMA2_TI_INTEN_CLR                                  0xfffffffe
+      #define DMA2_TI_INTEN_MSB                                  0
+      #define DMA2_TI_INTEN_LSB                                  0
+#define DMA2_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00720c ) 
+   #define DMA2_SOURCE_AD_MASK                                   0xffffffff
+   #define DMA2_SOURCE_AD_WIDTH                                  32
+      #define DMA2_SOURCE_AD_S_ADDR_BITS                         31:0
+      #define DMA2_SOURCE_AD_S_ADDR_SET                          0xffffffff
+      #define DMA2_SOURCE_AD_S_ADDR_CLR                          0x00000000
+      #define DMA2_SOURCE_AD_S_ADDR_MSB                          31
+      #define DMA2_SOURCE_AD_S_ADDR_LSB                          0
+#define DMA2_DEST_AD                                             HW_REGISTER_RO( 0x7e007210 ) 
+   #define DMA2_DEST_AD_MASK                                     0xffffffff
+   #define DMA2_DEST_AD_WIDTH                                    32
+      #define DMA2_DEST_AD_D_ADDR_BITS                           31:0
+      #define DMA2_DEST_AD_D_ADDR_SET                            0xffffffff
+      #define DMA2_DEST_AD_D_ADDR_CLR                            0x00000000
+      #define DMA2_DEST_AD_D_ADDR_MSB                            31
+      #define DMA2_DEST_AD_D_ADDR_LSB                            0
+#define DMA2_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007214 ) 
+   #define DMA2_TXFR_LEN_MASK                                    0x3fffffff
+   #define DMA2_TXFR_LEN_WIDTH                                   30
+      #define DMA2_TXFR_LEN_YLENGTH_BITS                         29:16
+      #define DMA2_TXFR_LEN_YLENGTH_SET                          0x3fff0000
+      #define DMA2_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
+      #define DMA2_TXFR_LEN_YLENGTH_MSB                          29
+      #define DMA2_TXFR_LEN_YLENGTH_LSB                          16
+      #define DMA2_TXFR_LEN_XLENGTH_BITS                         15:0
+      #define DMA2_TXFR_LEN_XLENGTH_SET                          0x0000ffff
+      #define DMA2_TXFR_LEN_XLENGTH_CLR                          0xffff0000
+      #define DMA2_TXFR_LEN_XLENGTH_MSB                          15
+      #define DMA2_TXFR_LEN_XLENGTH_LSB                          0
+#define DMA2_STRIDE                                              HW_REGISTER_RO( 0x7e007218 ) 
+   #define DMA2_STRIDE_MASK                                      0xffffffff
+   #define DMA2_STRIDE_WIDTH                                     32
+      #define DMA2_STRIDE_D_STRIDE_BITS                          31:16
+      #define DMA2_STRIDE_D_STRIDE_SET                           0xffff0000
+      #define DMA2_STRIDE_D_STRIDE_CLR                           0x0000ffff
+      #define DMA2_STRIDE_D_STRIDE_MSB                           31
+      #define DMA2_STRIDE_D_STRIDE_LSB                           16
+      #define DMA2_STRIDE_S_STRIDE_BITS                          15:0
+      #define DMA2_STRIDE_S_STRIDE_SET                           0x0000ffff
+      #define DMA2_STRIDE_S_STRIDE_CLR                           0xffff0000
+      #define DMA2_STRIDE_S_STRIDE_MSB                           15
+      #define DMA2_STRIDE_S_STRIDE_LSB                           0
+#define DMA2_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00721c ) 
+   #define DMA2_NEXTCONBK_MASK                                   0xffffffe0
+   #define DMA2_NEXTCONBK_WIDTH                                  32
+      #define DMA2_NEXTCONBK_ADDR_BITS                           31:5
+      #define DMA2_NEXTCONBK_ADDR_SET                            0xffffffe0
+      #define DMA2_NEXTCONBK_ADDR_CLR                            0x0000001f
+      #define DMA2_NEXTCONBK_ADDR_MSB                            31
+      #define DMA2_NEXTCONBK_ADDR_LSB                            5
+#define DMA2_DEBUG                                               HW_REGISTER_RW( 0x7e007220 ) 
+   #define DMA2_DEBUG_MASK                                       0x1ffffff7
+   #define DMA2_DEBUG_WIDTH                                      29
+   #define DMA2_DEBUG_RESET                                      0000000000
+      #define DMA2_DEBUG_LITE_BITS                               28:28
+      #define DMA2_DEBUG_LITE_SET                                0x10000000
+      #define DMA2_DEBUG_LITE_CLR                                0xefffffff
+      #define DMA2_DEBUG_LITE_MSB                                28
+      #define DMA2_DEBUG_LITE_LSB                                28
+      #define DMA2_DEBUG_VERSION_BITS                            27:25
+      #define DMA2_DEBUG_VERSION_SET                             0x0e000000
+      #define DMA2_DEBUG_VERSION_CLR                             0xf1ffffff
+      #define DMA2_DEBUG_VERSION_MSB                             27
+      #define DMA2_DEBUG_VERSION_LSB                             25
+      #define DMA2_DEBUG_DMA_STATE_BITS                          24:16
+      #define DMA2_DEBUG_DMA_STATE_SET                           0x01ff0000
+      #define DMA2_DEBUG_DMA_STATE_CLR                           0xfe00ffff
+      #define DMA2_DEBUG_DMA_STATE_MSB                           24
+      #define DMA2_DEBUG_DMA_STATE_LSB                           16
+      #define DMA2_DEBUG_DMA_ID_BITS                             15:8
+      #define DMA2_DEBUG_DMA_ID_SET                              0x0000ff00
+      #define DMA2_DEBUG_DMA_ID_CLR                              0xffff00ff
+      #define DMA2_DEBUG_DMA_ID_MSB                              15
+      #define DMA2_DEBUG_DMA_ID_LSB                              8
+      #define DMA2_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
+      #define DMA2_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
+      #define DMA2_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
+      #define DMA2_DEBUG_OUTSTANDING_WRITES_MSB                  7
+      #define DMA2_DEBUG_OUTSTANDING_WRITES_LSB                  4
+      #define DMA2_DEBUG_READ_ERROR_BITS                         2:2
+      #define DMA2_DEBUG_READ_ERROR_SET                          0x00000004
+      #define DMA2_DEBUG_READ_ERROR_CLR                          0xfffffffb
+      #define DMA2_DEBUG_READ_ERROR_MSB                          2
+      #define DMA2_DEBUG_READ_ERROR_LSB                          2
+      #define DMA2_DEBUG_FIFO_ERROR_BITS                         1:1
+      #define DMA2_DEBUG_FIFO_ERROR_SET                          0x00000002
+      #define DMA2_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
+      #define DMA2_DEBUG_FIFO_ERROR_MSB                          1
+      #define DMA2_DEBUG_FIFO_ERROR_LSB                          1
+      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
+      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
+      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
+      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
+      #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma3.h b/bcm2708_chip/axi_dma3.h
new file mode 100755 (executable)
index 0000000..a2208c0
--- /dev/null
@@ -0,0 +1,257 @@
+// This file was generated by the create_regs script
+#define DMA3_BASE                                                0x7e007300
+#define DMA3_CS                                                  HW_REGISTER_RW( 0x7e007300 ) 
+   #define DMA3_CS_MASK                                          0xf0ff017f
+   #define DMA3_CS_WIDTH                                         32
+   #define DMA3_CS_RESET                                         0000000000
+      #define DMA3_CS_RESET_BITS                                 31:31
+      #define DMA3_CS_RESET_SET                                  0x80000000
+      #define DMA3_CS_RESET_CLR                                  0x7fffffff
+      #define DMA3_CS_RESET_MSB                                  31
+      #define DMA3_CS_RESET_LSB                                  31
+      #define DMA3_CS_ABORT_BITS                                 30:30
+      #define DMA3_CS_ABORT_SET                                  0x40000000
+      #define DMA3_CS_ABORT_CLR                                  0xbfffffff
+      #define DMA3_CS_ABORT_MSB                                  30
+      #define DMA3_CS_ABORT_LSB                                  30
+      #define DMA3_CS_DISDEBUG_BITS                              29:29
+      #define DMA3_CS_DISDEBUG_SET                               0x20000000
+      #define DMA3_CS_DISDEBUG_CLR                               0xdfffffff
+      #define DMA3_CS_DISDEBUG_MSB                               29
+      #define DMA3_CS_DISDEBUG_LSB                               29
+      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
+      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
+      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
+      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
+      #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
+      #define DMA3_CS_PANIC_PRIORITY_BITS                        23:20
+      #define DMA3_CS_PANIC_PRIORITY_SET                         0x00f00000
+      #define DMA3_CS_PANIC_PRIORITY_CLR                         0xff0fffff
+      #define DMA3_CS_PANIC_PRIORITY_MSB                         23
+      #define DMA3_CS_PANIC_PRIORITY_LSB                         20
+      #define DMA3_CS_PRIORITY_BITS                              19:16
+      #define DMA3_CS_PRIORITY_SET                               0x000f0000
+      #define DMA3_CS_PRIORITY_CLR                               0xfff0ffff
+      #define DMA3_CS_PRIORITY_MSB                               19
+      #define DMA3_CS_PRIORITY_LSB                               16
+      #define DMA3_CS_ERROR_BITS                                 8:8
+      #define DMA3_CS_ERROR_SET                                  0x00000100
+      #define DMA3_CS_ERROR_CLR                                  0xfffffeff
+      #define DMA3_CS_ERROR_MSB                                  8
+      #define DMA3_CS_ERROR_LSB                                  8
+      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
+      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
+      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
+      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
+      #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
+      #define DMA3_CS_DREQ_STOPS_DMA_BITS                        5:5
+      #define DMA3_CS_DREQ_STOPS_DMA_SET                         0x00000020
+      #define DMA3_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
+      #define DMA3_CS_DREQ_STOPS_DMA_MSB                         5
+      #define DMA3_CS_DREQ_STOPS_DMA_LSB                         5
+      #define DMA3_CS_PAUSED_BITS                                4:4
+      #define DMA3_CS_PAUSED_SET                                 0x00000010
+      #define DMA3_CS_PAUSED_CLR                                 0xffffffef
+      #define DMA3_CS_PAUSED_MSB                                 4
+      #define DMA3_CS_PAUSED_LSB                                 4
+      #define DMA3_CS_DREQ_BITS                                  3:3
+      #define DMA3_CS_DREQ_SET                                   0x00000008
+      #define DMA3_CS_DREQ_CLR                                   0xfffffff7
+      #define DMA3_CS_DREQ_MSB                                   3
+      #define DMA3_CS_DREQ_LSB                                   3
+      #define DMA3_CS_INT_BITS                                   2:2
+      #define DMA3_CS_INT_SET                                    0x00000004
+      #define DMA3_CS_INT_CLR                                    0xfffffffb
+      #define DMA3_CS_INT_MSB                                    2
+      #define DMA3_CS_INT_LSB                                    2
+      #define DMA3_CS_END_BITS                                   1:1
+      #define DMA3_CS_END_SET                                    0x00000002
+      #define DMA3_CS_END_CLR                                    0xfffffffd
+      #define DMA3_CS_END_MSB                                    1
+      #define DMA3_CS_END_LSB                                    1
+      #define DMA3_CS_ACTIVE_BITS                                0:0
+      #define DMA3_CS_ACTIVE_SET                                 0x00000001
+      #define DMA3_CS_ACTIVE_CLR                                 0xfffffffe
+      #define DMA3_CS_ACTIVE_MSB                                 0
+      #define DMA3_CS_ACTIVE_LSB                                 0
+#define DMA3_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007304 ) 
+   #define DMA3_CONBLK_AD_MASK                                   0xffffffe0
+   #define DMA3_CONBLK_AD_WIDTH                                  32
+   #define DMA3_CONBLK_AD_RESET                                  0000000000
+      #define DMA3_CONBLK_AD_SCB_ADDR_BITS                       31:5
+      #define DMA3_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
+      #define DMA3_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
+      #define DMA3_CONBLK_AD_SCB_ADDR_MSB                        31
+      #define DMA3_CONBLK_AD_SCB_ADDR_LSB                        5
+#define DMA3_TI                                                  HW_REGISTER_RO( 0x7e007308 ) 
+   #define DMA3_TI_MASK                                          0x07fffffb
+   #define DMA3_TI_WIDTH                                         27
+      #define DMA3_TI_NO_WIDE_BURSTS_BITS                        26:26
+      #define DMA3_TI_NO_WIDE_BURSTS_SET                         0x04000000
+      #define DMA3_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
+      #define DMA3_TI_NO_WIDE_BURSTS_MSB                         26
+      #define DMA3_TI_NO_WIDE_BURSTS_LSB                         26
+      #define DMA3_TI_WAITS_BITS                                 25:21
+      #define DMA3_TI_WAITS_SET                                  0x03e00000
+      #define DMA3_TI_WAITS_CLR                                  0xfc1fffff
+      #define DMA3_TI_WAITS_MSB                                  25
+      #define DMA3_TI_WAITS_LSB                                  21
+      #define DMA3_TI_PERMAP_BITS                                20:16
+      #define DMA3_TI_PERMAP_SET                                 0x001f0000
+      #define DMA3_TI_PERMAP_CLR                                 0xffe0ffff
+      #define DMA3_TI_PERMAP_MSB                                 20
+      #define DMA3_TI_PERMAP_LSB                                 16
+      #define DMA3_TI_BURST_LENGTH_BITS                          15:12
+      #define DMA3_TI_BURST_LENGTH_SET                           0x0000f000
+      #define DMA3_TI_BURST_LENGTH_CLR                           0xffff0fff
+      #define DMA3_TI_BURST_LENGTH_MSB                           15
+      #define DMA3_TI_BURST_LENGTH_LSB                           12
+      #define DMA3_TI_SRC_IGNORE_BITS                            11:11
+      #define DMA3_TI_SRC_IGNORE_SET                             0x00000800
+      #define DMA3_TI_SRC_IGNORE_CLR                             0xfffff7ff
+      #define DMA3_TI_SRC_IGNORE_MSB                             11
+      #define DMA3_TI_SRC_IGNORE_LSB                             11
+      #define DMA3_TI_SRC_DREQ_BITS                              10:10
+      #define DMA3_TI_SRC_DREQ_SET                               0x00000400
+      #define DMA3_TI_SRC_DREQ_CLR                               0xfffffbff
+      #define DMA3_TI_SRC_DREQ_MSB                               10
+      #define DMA3_TI_SRC_DREQ_LSB                               10
+      #define DMA3_TI_SRC_WIDTH_BITS                             9:9
+      #define DMA3_TI_SRC_WIDTH_SET                              0x00000200
+      #define DMA3_TI_SRC_WIDTH_CLR                              0xfffffdff
+      #define DMA3_TI_SRC_WIDTH_MSB                              9
+      #define DMA3_TI_SRC_WIDTH_LSB                              9
+      #define DMA3_TI_SRC_INC_BITS                               8:8
+      #define DMA3_TI_SRC_INC_SET                                0x00000100
+      #define DMA3_TI_SRC_INC_CLR                                0xfffffeff
+      #define DMA3_TI_SRC_INC_MSB                                8
+      #define DMA3_TI_SRC_INC_LSB                                8
+      #define DMA3_TI_DEST_IGNORE_BITS                           7:7
+      #define DMA3_TI_DEST_IGNORE_SET                            0x00000080
+      #define DMA3_TI_DEST_IGNORE_CLR                            0xffffff7f
+      #define DMA3_TI_DEST_IGNORE_MSB                            7
+      #define DMA3_TI_DEST_IGNORE_LSB                            7
+      #define DMA3_TI_DEST_DREQ_BITS                             6:6
+      #define DMA3_TI_DEST_DREQ_SET                              0x00000040
+      #define DMA3_TI_DEST_DREQ_CLR                              0xffffffbf
+      #define DMA3_TI_DEST_DREQ_MSB                              6
+      #define DMA3_TI_DEST_DREQ_LSB                              6
+      #define DMA3_TI_DEST_WIDTH_BITS                            5:5
+      #define DMA3_TI_DEST_WIDTH_SET                             0x00000020
+      #define DMA3_TI_DEST_WIDTH_CLR                             0xffffffdf
+      #define DMA3_TI_DEST_WIDTH_MSB                             5
+      #define DMA3_TI_DEST_WIDTH_LSB                             5
+      #define DMA3_TI_DEST_INC_BITS                              4:4
+      #define DMA3_TI_DEST_INC_SET                               0x00000010
+      #define DMA3_TI_DEST_INC_CLR                               0xffffffef
+      #define DMA3_TI_DEST_INC_MSB                               4
+      #define DMA3_TI_DEST_INC_LSB                               4
+      #define DMA3_TI_WAIT_RESP_BITS                             3:3
+      #define DMA3_TI_WAIT_RESP_SET                              0x00000008
+      #define DMA3_TI_WAIT_RESP_CLR                              0xfffffff7
+      #define DMA3_TI_WAIT_RESP_MSB                              3
+      #define DMA3_TI_WAIT_RESP_LSB                              3
+      #define DMA3_TI_TDMODE_BITS                                1:1
+      #define DMA3_TI_TDMODE_SET                                 0x00000002
+      #define DMA3_TI_TDMODE_CLR                                 0xfffffffd
+      #define DMA3_TI_TDMODE_MSB                                 1
+      #define DMA3_TI_TDMODE_LSB                                 1
+      #define DMA3_TI_INTEN_BITS                                 0:0
+      #define DMA3_TI_INTEN_SET                                  0x00000001
+      #define DMA3_TI_INTEN_CLR                                  0xfffffffe
+      #define DMA3_TI_INTEN_MSB                                  0
+      #define DMA3_TI_INTEN_LSB                                  0
+#define DMA3_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00730c ) 
+   #define DMA3_SOURCE_AD_MASK                                   0xffffffff
+   #define DMA3_SOURCE_AD_WIDTH                                  32
+      #define DMA3_SOURCE_AD_S_ADDR_BITS                         31:0
+      #define DMA3_SOURCE_AD_S_ADDR_SET                          0xffffffff
+      #define DMA3_SOURCE_AD_S_ADDR_CLR                          0x00000000
+      #define DMA3_SOURCE_AD_S_ADDR_MSB                          31
+      #define DMA3_SOURCE_AD_S_ADDR_LSB                          0
+#define DMA3_DEST_AD                                             HW_REGISTER_RO( 0x7e007310 ) 
+   #define DMA3_DEST_AD_MASK                                     0xffffffff
+   #define DMA3_DEST_AD_WIDTH                                    32
+      #define DMA3_DEST_AD_D_ADDR_BITS                           31:0
+      #define DMA3_DEST_AD_D_ADDR_SET                            0xffffffff
+      #define DMA3_DEST_AD_D_ADDR_CLR                            0x00000000
+      #define DMA3_DEST_AD_D_ADDR_MSB                            31
+      #define DMA3_DEST_AD_D_ADDR_LSB                            0
+#define DMA3_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007314 ) 
+   #define DMA3_TXFR_LEN_MASK                                    0x3fffffff
+   #define DMA3_TXFR_LEN_WIDTH                                   30
+      #define DMA3_TXFR_LEN_YLENGTH_BITS                         29:16
+      #define DMA3_TXFR_LEN_YLENGTH_SET                          0x3fff0000
+      #define DMA3_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
+      #define DMA3_TXFR_LEN_YLENGTH_MSB                          29
+      #define DMA3_TXFR_LEN_YLENGTH_LSB                          16
+      #define DMA3_TXFR_LEN_XLENGTH_BITS                         15:0
+      #define DMA3_TXFR_LEN_XLENGTH_SET                          0x0000ffff
+      #define DMA3_TXFR_LEN_XLENGTH_CLR                          0xffff0000
+      #define DMA3_TXFR_LEN_XLENGTH_MSB                          15
+      #define DMA3_TXFR_LEN_XLENGTH_LSB                          0
+#define DMA3_STRIDE                                              HW_REGISTER_RO( 0x7e007318 ) 
+   #define DMA3_STRIDE_MASK                                      0xffffffff
+   #define DMA3_STRIDE_WIDTH                                     32
+      #define DMA3_STRIDE_D_STRIDE_BITS                          31:16
+      #define DMA3_STRIDE_D_STRIDE_SET                           0xffff0000
+      #define DMA3_STRIDE_D_STRIDE_CLR                           0x0000ffff
+      #define DMA3_STRIDE_D_STRIDE_MSB                           31
+      #define DMA3_STRIDE_D_STRIDE_LSB                           16
+      #define DMA3_STRIDE_S_STRIDE_BITS                          15:0
+      #define DMA3_STRIDE_S_STRIDE_SET                           0x0000ffff
+      #define DMA3_STRIDE_S_STRIDE_CLR                           0xffff0000
+      #define DMA3_STRIDE_S_STRIDE_MSB                           15
+      #define DMA3_STRIDE_S_STRIDE_LSB                           0
+#define DMA3_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00731c ) 
+   #define DMA3_NEXTCONBK_MASK                                   0xffffffe0
+   #define DMA3_NEXTCONBK_WIDTH                                  32
+      #define DMA3_NEXTCONBK_ADDR_BITS                           31:5
+      #define DMA3_NEXTCONBK_ADDR_SET                            0xffffffe0
+      #define DMA3_NEXTCONBK_ADDR_CLR                            0x0000001f
+      #define DMA3_NEXTCONBK_ADDR_MSB                            31
+      #define DMA3_NEXTCONBK_ADDR_LSB                            5
+#define DMA3_DEBUG                                               HW_REGISTER_RW( 0x7e007320 ) 
+   #define DMA3_DEBUG_MASK                                       0x1ffffff7
+   #define DMA3_DEBUG_WIDTH                                      29
+   #define DMA3_DEBUG_RESET                                      0000000000
+      #define DMA3_DEBUG_LITE_BITS                               28:28
+      #define DMA3_DEBUG_LITE_SET                                0x10000000
+      #define DMA3_DEBUG_LITE_CLR                                0xefffffff
+      #define DMA3_DEBUG_LITE_MSB                                28
+      #define DMA3_DEBUG_LITE_LSB                                28
+      #define DMA3_DEBUG_VERSION_BITS                            27:25
+      #define DMA3_DEBUG_VERSION_SET                             0x0e000000
+      #define DMA3_DEBUG_VERSION_CLR                             0xf1ffffff
+      #define DMA3_DEBUG_VERSION_MSB                             27
+      #define DMA3_DEBUG_VERSION_LSB                             25
+      #define DMA3_DEBUG_DMA_STATE_BITS                          24:16
+      #define DMA3_DEBUG_DMA_STATE_SET                           0x01ff0000
+      #define DMA3_DEBUG_DMA_STATE_CLR                           0xfe00ffff
+      #define DMA3_DEBUG_DMA_STATE_MSB                           24
+      #define DMA3_DEBUG_DMA_STATE_LSB                           16
+      #define DMA3_DEBUG_DMA_ID_BITS                             15:8
+      #define DMA3_DEBUG_DMA_ID_SET                              0x0000ff00
+      #define DMA3_DEBUG_DMA_ID_CLR                              0xffff00ff
+      #define DMA3_DEBUG_DMA_ID_MSB                              15
+      #define DMA3_DEBUG_DMA_ID_LSB                              8
+      #define DMA3_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
+      #define DMA3_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
+      #define DMA3_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
+      #define DMA3_DEBUG_OUTSTANDING_WRITES_MSB                  7
+      #define DMA3_DEBUG_OUTSTANDING_WRITES_LSB                  4
+      #define DMA3_DEBUG_READ_ERROR_BITS                         2:2
+      #define DMA3_DEBUG_READ_ERROR_SET                          0x00000004
+      #define DMA3_DEBUG_READ_ERROR_CLR                          0xfffffffb
+      #define DMA3_DEBUG_READ_ERROR_MSB                          2
+      #define DMA3_DEBUG_READ_ERROR_LSB                          2
+      #define DMA3_DEBUG_FIFO_ERROR_BITS                         1:1
+      #define DMA3_DEBUG_FIFO_ERROR_SET                          0x00000002
+      #define DMA3_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
+      #define DMA3_DEBUG_FIFO_ERROR_MSB                          1
+      #define DMA3_DEBUG_FIFO_ERROR_LSB                          1
+      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
+      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
+      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
+      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
+      #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma4.h b/bcm2708_chip/axi_dma4.h
new file mode 100755 (executable)
index 0000000..1cefda5
--- /dev/null
@@ -0,0 +1,257 @@
+// This file was generated by the create_regs script
+#define DMA4_BASE                                                0x7e007400
+#define DMA4_CS                                                  HW_REGISTER_RW( 0x7e007400 ) 
+   #define DMA4_CS_MASK                                          0xf0ff017f
+   #define DMA4_CS_WIDTH                                         32
+   #define DMA4_CS_RESET                                         0000000000
+      #define DMA4_CS_RESET_BITS                                 31:31
+      #define DMA4_CS_RESET_SET                                  0x80000000
+      #define DMA4_CS_RESET_CLR                                  0x7fffffff
+      #define DMA4_CS_RESET_MSB                                  31
+      #define DMA4_CS_RESET_LSB                                  31
+      #define DMA4_CS_ABORT_BITS                                 30:30
+      #define DMA4_CS_ABORT_SET                                  0x40000000
+      #define DMA4_CS_ABORT_CLR                                  0xbfffffff
+      #define DMA4_CS_ABORT_MSB                                  30
+      #define DMA4_CS_ABORT_LSB                                  30
+      #define DMA4_CS_DISDEBUG_BITS                              29:29
+      #define DMA4_CS_DISDEBUG_SET                               0x20000000
+      #define DMA4_CS_DISDEBUG_CLR                               0xdfffffff
+      #define DMA4_CS_DISDEBUG_MSB                               29
+      #define DMA4_CS_DISDEBUG_LSB                               29
+      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
+      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
+      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
+      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
+      #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
+      #define DMA4_CS_PANIC_PRIORITY_BITS                        23:20
+      #define DMA4_CS_PANIC_PRIORITY_SET                         0x00f00000
+      #define DMA4_CS_PANIC_PRIORITY_CLR                         0xff0fffff
+      #define DMA4_CS_PANIC_PRIORITY_MSB                         23
+      #define DMA4_CS_PANIC_PRIORITY_LSB                         20
+      #define DMA4_CS_PRIORITY_BITS                              19:16
+      #define DMA4_CS_PRIORITY_SET                               0x000f0000
+      #define DMA4_CS_PRIORITY_CLR                               0xfff0ffff
+      #define DMA4_CS_PRIORITY_MSB                               19
+      #define DMA4_CS_PRIORITY_LSB                               16
+      #define DMA4_CS_ERROR_BITS                                 8:8
+      #define DMA4_CS_ERROR_SET                                  0x00000100
+      #define DMA4_CS_ERROR_CLR                                  0xfffffeff
+      #define DMA4_CS_ERROR_MSB                                  8
+      #define DMA4_CS_ERROR_LSB                                  8
+      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
+      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
+      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
+      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
+      #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
+      #define DMA4_CS_DREQ_STOPS_DMA_BITS                        5:5
+      #define DMA4_CS_DREQ_STOPS_DMA_SET                         0x00000020
+      #define DMA4_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
+      #define DMA4_CS_DREQ_STOPS_DMA_MSB                         5
+      #define DMA4_CS_DREQ_STOPS_DMA_LSB                         5
+      #define DMA4_CS_PAUSED_BITS                                4:4
+      #define DMA4_CS_PAUSED_SET                                 0x00000010
+      #define DMA4_CS_PAUSED_CLR                                 0xffffffef
+      #define DMA4_CS_PAUSED_MSB                                 4
+      #define DMA4_CS_PAUSED_LSB                                 4
+      #define DMA4_CS_DREQ_BITS                                  3:3
+      #define DMA4_CS_DREQ_SET                                   0x00000008
+      #define DMA4_CS_DREQ_CLR                                   0xfffffff7
+      #define DMA4_CS_DREQ_MSB                                   3
+      #define DMA4_CS_DREQ_LSB                                   3
+      #define DMA4_CS_INT_BITS                                   2:2
+      #define DMA4_CS_INT_SET                                    0x00000004
+      #define DMA4_CS_INT_CLR                                    0xfffffffb
+      #define DMA4_CS_INT_MSB                                    2
+      #define DMA4_CS_INT_LSB                                    2
+      #define DMA4_CS_END_BITS                                   1:1
+      #define DMA4_CS_END_SET                                    0x00000002
+      #define DMA4_CS_END_CLR                                    0xfffffffd
+      #define DMA4_CS_END_MSB                                    1
+      #define DMA4_CS_END_LSB                                    1
+      #define DMA4_CS_ACTIVE_BITS                                0:0
+      #define DMA4_CS_ACTIVE_SET                                 0x00000001
+      #define DMA4_CS_ACTIVE_CLR                                 0xfffffffe
+      #define DMA4_CS_ACTIVE_MSB                                 0
+      #define DMA4_CS_ACTIVE_LSB                                 0
+#define DMA4_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007404 ) 
+   #define DMA4_CONBLK_AD_MASK                                   0xffffffe0
+   #define DMA4_CONBLK_AD_WIDTH                                  32
+   #define DMA4_CONBLK_AD_RESET                                  0000000000
+      #define DMA4_CONBLK_AD_SCB_ADDR_BITS                       31:5
+      #define DMA4_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
+      #define DMA4_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
+      #define DMA4_CONBLK_AD_SCB_ADDR_MSB                        31
+      #define DMA4_CONBLK_AD_SCB_ADDR_LSB                        5
+#define DMA4_TI                                                  HW_REGISTER_RO( 0x7e007408 ) 
+   #define DMA4_TI_MASK                                          0x07fffffb
+   #define DMA4_TI_WIDTH                                         27
+      #define DMA4_TI_NO_WIDE_BURSTS_BITS                        26:26
+      #define DMA4_TI_NO_WIDE_BURSTS_SET                         0x04000000
+      #define DMA4_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
+      #define DMA4_TI_NO_WIDE_BURSTS_MSB                         26
+      #define DMA4_TI_NO_WIDE_BURSTS_LSB                         26
+      #define DMA4_TI_WAITS_BITS                                 25:21
+      #define DMA4_TI_WAITS_SET                                  0x03e00000
+      #define DMA4_TI_WAITS_CLR                                  0xfc1fffff
+      #define DMA4_TI_WAITS_MSB                                  25
+      #define DMA4_TI_WAITS_LSB                                  21
+      #define DMA4_TI_PERMAP_BITS                                20:16
+      #define DMA4_TI_PERMAP_SET                                 0x001f0000
+      #define DMA4_TI_PERMAP_CLR                                 0xffe0ffff
+      #define DMA4_TI_PERMAP_MSB                                 20
+      #define DMA4_TI_PERMAP_LSB                                 16
+      #define DMA4_TI_BURST_LENGTH_BITS                          15:12
+      #define DMA4_TI_BURST_LENGTH_SET                           0x0000f000
+      #define DMA4_TI_BURST_LENGTH_CLR                           0xffff0fff
+      #define DMA4_TI_BURST_LENGTH_MSB                           15
+      #define DMA4_TI_BURST_LENGTH_LSB                           12
+      #define DMA4_TI_SRC_IGNORE_BITS                            11:11
+      #define DMA4_TI_SRC_IGNORE_SET                             0x00000800
+      #define DMA4_TI_SRC_IGNORE_CLR                             0xfffff7ff
+      #define DMA4_TI_SRC_IGNORE_MSB                             11
+      #define DMA4_TI_SRC_IGNORE_LSB                             11
+      #define DMA4_TI_SRC_DREQ_BITS                              10:10
+      #define DMA4_TI_SRC_DREQ_SET                               0x00000400
+      #define DMA4_TI_SRC_DREQ_CLR                               0xfffffbff
+      #define DMA4_TI_SRC_DREQ_MSB                               10
+      #define DMA4_TI_SRC_DREQ_LSB                               10
+      #define DMA4_TI_SRC_WIDTH_BITS                             9:9
+      #define DMA4_TI_SRC_WIDTH_SET                              0x00000200
+      #define DMA4_TI_SRC_WIDTH_CLR                              0xfffffdff
+      #define DMA4_TI_SRC_WIDTH_MSB                              9
+      #define DMA4_TI_SRC_WIDTH_LSB                              9
+      #define DMA4_TI_SRC_INC_BITS                               8:8
+      #define DMA4_TI_SRC_INC_SET                                0x00000100
+      #define DMA4_TI_SRC_INC_CLR                                0xfffffeff
+      #define DMA4_TI_SRC_INC_MSB                                8
+      #define DMA4_TI_SRC_INC_LSB                                8
+      #define DMA4_TI_DEST_IGNORE_BITS                           7:7
+      #define DMA4_TI_DEST_IGNORE_SET                            0x00000080
+      #define DMA4_TI_DEST_IGNORE_CLR                            0xffffff7f
+      #define DMA4_TI_DEST_IGNORE_MSB                            7
+      #define DMA4_TI_DEST_IGNORE_LSB                            7
+      #define DMA4_TI_DEST_DREQ_BITS                             6:6
+      #define DMA4_TI_DEST_DREQ_SET                              0x00000040
+      #define DMA4_TI_DEST_DREQ_CLR                              0xffffffbf
+      #define DMA4_TI_DEST_DREQ_MSB                              6
+      #define DMA4_TI_DEST_DREQ_LSB                              6
+      #define DMA4_TI_DEST_WIDTH_BITS                            5:5
+      #define DMA4_TI_DEST_WIDTH_SET                             0x00000020
+      #define DMA4_TI_DEST_WIDTH_CLR                             0xffffffdf
+      #define DMA4_TI_DEST_WIDTH_MSB                             5
+      #define DMA4_TI_DEST_WIDTH_LSB                             5
+      #define DMA4_TI_DEST_INC_BITS                              4:4
+      #define DMA4_TI_DEST_INC_SET                               0x00000010
+      #define DMA4_TI_DEST_INC_CLR                               0xffffffef
+      #define DMA4_TI_DEST_INC_MSB                               4
+      #define DMA4_TI_DEST_INC_LSB                               4
+      #define DMA4_TI_WAIT_RESP_BITS                             3:3
+      #define DMA4_TI_WAIT_RESP_SET                              0x00000008
+      #define DMA4_TI_WAIT_RESP_CLR                              0xfffffff7
+      #define DMA4_TI_WAIT_RESP_MSB                              3
+      #define DMA4_TI_WAIT_RESP_LSB                              3
+      #define DMA4_TI_TDMODE_BITS                                1:1
+      #define DMA4_TI_TDMODE_SET                                 0x00000002
+      #define DMA4_TI_TDMODE_CLR                                 0xfffffffd
+      #define DMA4_TI_TDMODE_MSB                                 1
+      #define DMA4_TI_TDMODE_LSB                                 1
+      #define DMA4_TI_INTEN_BITS                                 0:0
+      #define DMA4_TI_INTEN_SET                                  0x00000001
+      #define DMA4_TI_INTEN_CLR                                  0xfffffffe
+      #define DMA4_TI_INTEN_MSB                                  0
+      #define DMA4_TI_INTEN_LSB                                  0
+#define DMA4_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00740c ) 
+   #define DMA4_SOURCE_AD_MASK                                   0xffffffff
+   #define DMA4_SOURCE_AD_WIDTH                                  32
+      #define DMA4_SOURCE_AD_S_ADDR_BITS                         31:0
+      #define DMA4_SOURCE_AD_S_ADDR_SET                          0xffffffff
+      #define DMA4_SOURCE_AD_S_ADDR_CLR                          0x00000000
+      #define DMA4_SOURCE_AD_S_ADDR_MSB                          31
+      #define DMA4_SOURCE_AD_S_ADDR_LSB                          0
+#define DMA4_DEST_AD                                             HW_REGISTER_RO( 0x7e007410 ) 
+   #define DMA4_DEST_AD_MASK                                     0xffffffff
+   #define DMA4_DEST_AD_WIDTH                                    32
+      #define DMA4_DEST_AD_D_ADDR_BITS                           31:0
+      #define DMA4_DEST_AD_D_ADDR_SET                            0xffffffff
+      #define DMA4_DEST_AD_D_ADDR_CLR                            0x00000000
+      #define DMA4_DEST_AD_D_ADDR_MSB                            31
+      #define DMA4_DEST_AD_D_ADDR_LSB                            0
+#define DMA4_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007414 ) 
+   #define DMA4_TXFR_LEN_MASK                                    0x3fffffff
+   #define DMA4_TXFR_LEN_WIDTH                                   30
+      #define DMA4_TXFR_LEN_YLENGTH_BITS                         29:16
+      #define DMA4_TXFR_LEN_YLENGTH_SET                          0x3fff0000
+      #define DMA4_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
+      #define DMA4_TXFR_LEN_YLENGTH_MSB                          29
+      #define DMA4_TXFR_LEN_YLENGTH_LSB                          16
+      #define DMA4_TXFR_LEN_XLENGTH_BITS                         15:0
+      #define DMA4_TXFR_LEN_XLENGTH_SET                          0x0000ffff
+      #define DMA4_TXFR_LEN_XLENGTH_CLR                          0xffff0000
+      #define DMA4_TXFR_LEN_XLENGTH_MSB                          15
+      #define DMA4_TXFR_LEN_XLENGTH_LSB                          0
+#define DMA4_STRIDE                                              HW_REGISTER_RO( 0x7e007418 ) 
+   #define DMA4_STRIDE_MASK                                      0xffffffff
+   #define DMA4_STRIDE_WIDTH                                     32
+      #define DMA4_STRIDE_D_STRIDE_BITS                          31:16
+      #define DMA4_STRIDE_D_STRIDE_SET                           0xffff0000
+      #define DMA4_STRIDE_D_STRIDE_CLR                           0x0000ffff
+      #define DMA4_STRIDE_D_STRIDE_MSB                           31
+      #define DMA4_STRIDE_D_STRIDE_LSB                           16
+      #define DMA4_STRIDE_S_STRIDE_BITS                          15:0
+      #define DMA4_STRIDE_S_STRIDE_SET                           0x0000ffff
+      #define DMA4_STRIDE_S_STRIDE_CLR                           0xffff0000
+      #define DMA4_STRIDE_S_STRIDE_MSB                           15
+      #define DMA4_STRIDE_S_STRIDE_LSB                           0
+#define DMA4_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00741c ) 
+   #define DMA4_NEXTCONBK_MASK                                   0xffffffe0
+   #define DMA4_NEXTCONBK_WIDTH                                  32
+      #define DMA4_NEXTCONBK_ADDR_BITS                           31:5
+      #define DMA4_NEXTCONBK_ADDR_SET                            0xffffffe0
+      #define DMA4_NEXTCONBK_ADDR_CLR                            0x0000001f
+      #define DMA4_NEXTCONBK_ADDR_MSB                            31
+      #define DMA4_NEXTCONBK_ADDR_LSB                            5
+#define DMA4_DEBUG                                               HW_REGISTER_RW( 0x7e007420 ) 
+   #define DMA4_DEBUG_MASK                                       0x1ffffff7
+   #define DMA4_DEBUG_WIDTH                                      29
+   #define DMA4_DEBUG_RESET                                      0000000000
+      #define DMA4_DEBUG_LITE_BITS                               28:28
+      #define DMA4_DEBUG_LITE_SET                                0x10000000
+      #define DMA4_DEBUG_LITE_CLR                                0xefffffff
+      #define DMA4_DEBUG_LITE_MSB                                28
+      #define DMA4_DEBUG_LITE_LSB                                28
+      #define DMA4_DEBUG_VERSION_BITS                            27:25
+      #define DMA4_DEBUG_VERSION_SET                             0x0e000000
+      #define DMA4_DEBUG_VERSION_CLR                             0xf1ffffff
+      #define DMA4_DEBUG_VERSION_MSB                             27
+      #define DMA4_DEBUG_VERSION_LSB                             25
+      #define DMA4_DEBUG_DMA_STATE_BITS                          24:16
+      #define DMA4_DEBUG_DMA_STATE_SET                           0x01ff0000
+      #define DMA4_DEBUG_DMA_STATE_CLR                           0xfe00ffff
+      #define DMA4_DEBUG_DMA_STATE_MSB                           24
+      #define DMA4_DEBUG_DMA_STATE_LSB                           16
+      #define DMA4_DEBUG_DMA_ID_BITS                             15:8
+      #define DMA4_DEBUG_DMA_ID_SET                              0x0000ff00
+      #define DMA4_DEBUG_DMA_ID_CLR                              0xffff00ff
+      #define DMA4_DEBUG_DMA_ID_MSB                              15
+      #define DMA4_DEBUG_DMA_ID_LSB                              8
+      #define DMA4_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
+      #define DMA4_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
+      #define DMA4_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
+      #define DMA4_DEBUG_OUTSTANDING_WRITES_MSB                  7
+      #define DMA4_DEBUG_OUTSTANDING_WRITES_LSB                  4
+      #define DMA4_DEBUG_READ_ERROR_BITS                         2:2
+      #define DMA4_DEBUG_READ_ERROR_SET                          0x00000004
+      #define DMA4_DEBUG_READ_ERROR_CLR                          0xfffffffb
+      #define DMA4_DEBUG_READ_ERROR_MSB                          2
+      #define DMA4_DEBUG_READ_ERROR_LSB                          2
+      #define DMA4_DEBUG_FIFO_ERROR_BITS                         1:1
+      #define DMA4_DEBUG_FIFO_ERROR_SET                          0x00000002
+      #define DMA4_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
+      #define DMA4_DEBUG_FIFO_ERROR_MSB                          1
+      #define DMA4_DEBUG_FIFO_ERROR_LSB                          1
+      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
+      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
+      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
+      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
+      #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma5.h b/bcm2708_chip/axi_dma5.h
new file mode 100755 (executable)
index 0000000..a8f6a1f
--- /dev/null
@@ -0,0 +1,257 @@
+// This file was generated by the create_regs script
+#define DMA5_BASE                                                0x7e007500
+#define DMA5_CS                                                  HW_REGISTER_RW( 0x7e007500 ) 
+   #define DMA5_CS_MASK                                          0xf0ff017f
+   #define DMA5_CS_WIDTH                                         32
+   #define DMA5_CS_RESET                                         0000000000
+      #define DMA5_CS_RESET_BITS                                 31:31
+      #define DMA5_CS_RESET_SET                                  0x80000000
+      #define DMA5_CS_RESET_CLR                                  0x7fffffff
+      #define DMA5_CS_RESET_MSB                                  31
+      #define DMA5_CS_RESET_LSB                                  31
+      #define DMA5_CS_ABORT_BITS                                 30:30
+      #define DMA5_CS_ABORT_SET                                  0x40000000
+      #define DMA5_CS_ABORT_CLR                                  0xbfffffff
+      #define DMA5_CS_ABORT_MSB                                  30
+      #define DMA5_CS_ABORT_LSB                                  30
+      #define DMA5_CS_DISDEBUG_BITS                              29:29
+      #define DMA5_CS_DISDEBUG_SET                               0x20000000
+      #define DMA5_CS_DISDEBUG_CLR                               0xdfffffff
+      #define DMA5_CS_DISDEBUG_MSB                               29
+      #define DMA5_CS_DISDEBUG_LSB                               29
+      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
+      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
+      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
+      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
+      #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
+      #define DMA5_CS_PANIC_PRIORITY_BITS                        23:20
+      #define DMA5_CS_PANIC_PRIORITY_SET                         0x00f00000
+      #define DMA5_CS_PANIC_PRIORITY_CLR                         0xff0fffff
+      #define DMA5_CS_PANIC_PRIORITY_MSB                         23
+      #define DMA5_CS_PANIC_PRIORITY_LSB                         20
+      #define DMA5_CS_PRIORITY_BITS                              19:16
+      #define DMA5_CS_PRIORITY_SET                               0x000f0000
+      #define DMA5_CS_PRIORITY_CLR                               0xfff0ffff
+      #define DMA5_CS_PRIORITY_MSB                               19
+      #define DMA5_CS_PRIORITY_LSB                               16
+      #define DMA5_CS_ERROR_BITS                                 8:8
+      #define DMA5_CS_ERROR_SET                                  0x00000100
+      #define DMA5_CS_ERROR_CLR                                  0xfffffeff
+      #define DMA5_CS_ERROR_MSB                                  8
+      #define DMA5_CS_ERROR_LSB                                  8
+      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
+      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
+      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
+      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
+      #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
+      #define DMA5_CS_DREQ_STOPS_DMA_BITS                        5:5
+      #define DMA5_CS_DREQ_STOPS_DMA_SET                         0x00000020
+      #define DMA5_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
+      #define DMA5_CS_DREQ_STOPS_DMA_MSB                         5
+      #define DMA5_CS_DREQ_STOPS_DMA_LSB                         5
+      #define DMA5_CS_PAUSED_BITS                                4:4
+      #define DMA5_CS_PAUSED_SET                                 0x00000010
+      #define DMA5_CS_PAUSED_CLR                                 0xffffffef
+      #define DMA5_CS_PAUSED_MSB                                 4
+      #define DMA5_CS_PAUSED_LSB                                 4
+      #define DMA5_CS_DREQ_BITS                                  3:3
+      #define DMA5_CS_DREQ_SET                                   0x00000008
+      #define DMA5_CS_DREQ_CLR                                   0xfffffff7
+      #define DMA5_CS_DREQ_MSB                                   3
+      #define DMA5_CS_DREQ_LSB                                   3
+      #define DMA5_CS_INT_BITS                                   2:2
+      #define DMA5_CS_INT_SET                                    0x00000004
+      #define DMA5_CS_INT_CLR                                    0xfffffffb
+      #define DMA5_CS_INT_MSB                                    2
+      #define DMA5_CS_INT_LSB                                    2
+      #define DMA5_CS_END_BITS                                   1:1
+      #define DMA5_CS_END_SET                                    0x00000002
+      #define DMA5_CS_END_CLR                                    0xfffffffd
+      #define DMA5_CS_END_MSB                                    1
+      #define DMA5_CS_END_LSB                                    1
+      #define DMA5_CS_ACTIVE_BITS                                0:0
+      #define DMA5_CS_ACTIVE_SET                                 0x00000001
+      #define DMA5_CS_ACTIVE_CLR                                 0xfffffffe
+      #define DMA5_CS_ACTIVE_MSB                                 0
+      #define DMA5_CS_ACTIVE_LSB                                 0
+#define DMA5_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007504 ) 
+   #define DMA5_CONBLK_AD_MASK                                   0xffffffe0
+   #define DMA5_CONBLK_AD_WIDTH                                  32
+   #define DMA5_CONBLK_AD_RESET                                  0000000000
+      #define DMA5_CONBLK_AD_SCB_ADDR_BITS                       31:5
+      #define DMA5_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
+      #define DMA5_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
+      #define DMA5_CONBLK_AD_SCB_ADDR_MSB                        31
+      #define DMA5_CONBLK_AD_SCB_ADDR_LSB                        5
+#define DMA5_TI                                                  HW_REGISTER_RO( 0x7e007508 ) 
+   #define DMA5_TI_MASK                                          0x07fffffb
+   #define DMA5_TI_WIDTH                                         27
+      #define DMA5_TI_NO_WIDE_BURSTS_BITS                        26:26
+      #define DMA5_TI_NO_WIDE_BURSTS_SET                         0x04000000
+      #define DMA5_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
+      #define DMA5_TI_NO_WIDE_BURSTS_MSB                         26
+      #define DMA5_TI_NO_WIDE_BURSTS_LSB                         26
+      #define DMA5_TI_WAITS_BITS                                 25:21
+      #define DMA5_TI_WAITS_SET                                  0x03e00000
+      #define DMA5_TI_WAITS_CLR                                  0xfc1fffff
+      #define DMA5_TI_WAITS_MSB                                  25
+      #define DMA5_TI_WAITS_LSB                                  21
+      #define DMA5_TI_PERMAP_BITS                                20:16
+      #define DMA5_TI_PERMAP_SET                                 0x001f0000
+      #define DMA5_TI_PERMAP_CLR                                 0xffe0ffff
+      #define DMA5_TI_PERMAP_MSB                                 20
+      #define DMA5_TI_PERMAP_LSB                                 16
+      #define DMA5_TI_BURST_LENGTH_BITS                          15:12
+      #define DMA5_TI_BURST_LENGTH_SET                           0x0000f000
+      #define DMA5_TI_BURST_LENGTH_CLR                           0xffff0fff
+      #define DMA5_TI_BURST_LENGTH_MSB                           15
+      #define DMA5_TI_BURST_LENGTH_LSB                           12
+      #define DMA5_TI_SRC_IGNORE_BITS                            11:11
+      #define DMA5_TI_SRC_IGNORE_SET                             0x00000800
+      #define DMA5_TI_SRC_IGNORE_CLR                             0xfffff7ff
+      #define DMA5_TI_SRC_IGNORE_MSB                             11
+      #define DMA5_TI_SRC_IGNORE_LSB                             11
+      #define DMA5_TI_SRC_DREQ_BITS                              10:10
+      #define DMA5_TI_SRC_DREQ_SET                               0x00000400
+      #define DMA5_TI_SRC_DREQ_CLR                               0xfffffbff
+      #define DMA5_TI_SRC_DREQ_MSB                               10
+      #define DMA5_TI_SRC_DREQ_LSB                               10
+      #define DMA5_TI_SRC_WIDTH_BITS                             9:9
+      #define DMA5_TI_SRC_WIDTH_SET                              0x00000200
+      #define DMA5_TI_SRC_WIDTH_CLR                              0xfffffdff
+      #define DMA5_TI_SRC_WIDTH_MSB                              9
+      #define DMA5_TI_SRC_WIDTH_LSB                              9
+      #define DMA5_TI_SRC_INC_BITS                               8:8
+      #define DMA5_TI_SRC_INC_SET                                0x00000100
+      #define DMA5_TI_SRC_INC_CLR                                0xfffffeff
+      #define DMA5_TI_SRC_INC_MSB                                8
+      #define DMA5_TI_SRC_INC_LSB                                8
+      #define DMA5_TI_DEST_IGNORE_BITS                           7:7
+      #define DMA5_TI_DEST_IGNORE_SET                            0x00000080
+      #define DMA5_TI_DEST_IGNORE_CLR                            0xffffff7f
+      #define DMA5_TI_DEST_IGNORE_MSB                            7
+      #define DMA5_TI_DEST_IGNORE_LSB                            7
+      #define DMA5_TI_DEST_DREQ_BITS                             6:6
+      #define DMA5_TI_DEST_DREQ_SET                              0x00000040
+      #define DMA5_TI_DEST_DREQ_CLR                              0xffffffbf
+      #define DMA5_TI_DEST_DREQ_MSB                              6
+      #define DMA5_TI_DEST_DREQ_LSB                              6
+      #define DMA5_TI_DEST_WIDTH_BITS                            5:5
+      #define DMA5_TI_DEST_WIDTH_SET                             0x00000020
+      #define DMA5_TI_DEST_WIDTH_CLR                             0xffffffdf
+      #define DMA5_TI_DEST_WIDTH_MSB                             5
+      #define DMA5_TI_DEST_WIDTH_LSB                             5
+      #define DMA5_TI_DEST_INC_BITS                              4:4
+      #define DMA5_TI_DEST_INC_SET                               0x00000010
+      #define DMA5_TI_DEST_INC_CLR                               0xffffffef
+      #define DMA5_TI_DEST_INC_MSB                               4
+      #define DMA5_TI_DEST_INC_LSB                               4
+      #define DMA5_TI_WAIT_RESP_BITS                             3:3
+      #define DMA5_TI_WAIT_RESP_SET                              0x00000008
+      #define DMA5_TI_WAIT_RESP_CLR                              0xfffffff7
+      #define DMA5_TI_WAIT_RESP_MSB                              3
+      #define DMA5_TI_WAIT_RESP_LSB                              3
+      #define DMA5_TI_TDMODE_BITS                                1:1
+      #define DMA5_TI_TDMODE_SET                                 0x00000002
+      #define DMA5_TI_TDMODE_CLR                                 0xfffffffd
+      #define DMA5_TI_TDMODE_MSB                                 1
+      #define DMA5_TI_TDMODE_LSB                                 1
+      #define DMA5_TI_INTEN_BITS                                 0:0
+      #define DMA5_TI_INTEN_SET                                  0x00000001
+      #define DMA5_TI_INTEN_CLR                                  0xfffffffe
+      #define DMA5_TI_INTEN_MSB                                  0
+      #define DMA5_TI_INTEN_LSB                                  0
+#define DMA5_SOURCE_AD                                           HW_REGISTER_RO( 0x7e00750c ) 
+   #define DMA5_SOURCE_AD_MASK                                   0xffffffff
+   #define DMA5_SOURCE_AD_WIDTH                                  32
+      #define DMA5_SOURCE_AD_S_ADDR_BITS                         31:0
+      #define DMA5_SOURCE_AD_S_ADDR_SET                          0xffffffff
+      #define DMA5_SOURCE_AD_S_ADDR_CLR                          0x00000000
+      #define DMA5_SOURCE_AD_S_ADDR_MSB                          31
+      #define DMA5_SOURCE_AD_S_ADDR_LSB                          0
+#define DMA5_DEST_AD                                             HW_REGISTER_RO( 0x7e007510 ) 
+   #define DMA5_DEST_AD_MASK                                     0xffffffff
+   #define DMA5_DEST_AD_WIDTH                                    32
+      #define DMA5_DEST_AD_D_ADDR_BITS                           31:0
+      #define DMA5_DEST_AD_D_ADDR_SET                            0xffffffff
+      #define DMA5_DEST_AD_D_ADDR_CLR                            0x00000000
+      #define DMA5_DEST_AD_D_ADDR_MSB                            31
+      #define DMA5_DEST_AD_D_ADDR_LSB                            0
+#define DMA5_TXFR_LEN                                            HW_REGISTER_RO( 0x7e007514 ) 
+   #define DMA5_TXFR_LEN_MASK                                    0x3fffffff
+   #define DMA5_TXFR_LEN_WIDTH                                   30
+      #define DMA5_TXFR_LEN_YLENGTH_BITS                         29:16
+      #define DMA5_TXFR_LEN_YLENGTH_SET                          0x3fff0000
+      #define DMA5_TXFR_LEN_YLENGTH_CLR                          0xc000ffff
+      #define DMA5_TXFR_LEN_YLENGTH_MSB                          29
+      #define DMA5_TXFR_LEN_YLENGTH_LSB                          16
+      #define DMA5_TXFR_LEN_XLENGTH_BITS                         15:0
+      #define DMA5_TXFR_LEN_XLENGTH_SET                          0x0000ffff
+      #define DMA5_TXFR_LEN_XLENGTH_CLR                          0xffff0000
+      #define DMA5_TXFR_LEN_XLENGTH_MSB                          15
+      #define DMA5_TXFR_LEN_XLENGTH_LSB                          0
+#define DMA5_STRIDE                                              HW_REGISTER_RO( 0x7e007518 ) 
+   #define DMA5_STRIDE_MASK                                      0xffffffff
+   #define DMA5_STRIDE_WIDTH                                     32
+      #define DMA5_STRIDE_D_STRIDE_BITS                          31:16
+      #define DMA5_STRIDE_D_STRIDE_SET                           0xffff0000
+      #define DMA5_STRIDE_D_STRIDE_CLR                           0x0000ffff
+      #define DMA5_STRIDE_D_STRIDE_MSB                           31
+      #define DMA5_STRIDE_D_STRIDE_LSB                           16
+      #define DMA5_STRIDE_S_STRIDE_BITS                          15:0
+      #define DMA5_STRIDE_S_STRIDE_SET                           0x0000ffff
+      #define DMA5_STRIDE_S_STRIDE_CLR                           0xffff0000
+      #define DMA5_STRIDE_S_STRIDE_MSB                           15
+      #define DMA5_STRIDE_S_STRIDE_LSB                           0
+#define DMA5_NEXTCONBK                                           HW_REGISTER_RO( 0x7e00751c ) 
+   #define DMA5_NEXTCONBK_MASK                                   0xffffffe0
+   #define DMA5_NEXTCONBK_WIDTH                                  32
+      #define DMA5_NEXTCONBK_ADDR_BITS                           31:5
+      #define DMA5_NEXTCONBK_ADDR_SET                            0xffffffe0
+      #define DMA5_NEXTCONBK_ADDR_CLR                            0x0000001f
+      #define DMA5_NEXTCONBK_ADDR_MSB                            31
+      #define DMA5_NEXTCONBK_ADDR_LSB                            5
+#define DMA5_DEBUG                                               HW_REGISTER_RW( 0x7e007520 ) 
+   #define DMA5_DEBUG_MASK                                       0x1ffffff7
+   #define DMA5_DEBUG_WIDTH                                      29
+   #define DMA5_DEBUG_RESET                                      0000000000
+      #define DMA5_DEBUG_LITE_BITS                               28:28
+      #define DMA5_DEBUG_LITE_SET                                0x10000000
+      #define DMA5_DEBUG_LITE_CLR                                0xefffffff
+      #define DMA5_DEBUG_LITE_MSB                                28
+      #define DMA5_DEBUG_LITE_LSB                                28
+      #define DMA5_DEBUG_VERSION_BITS                            27:25
+      #define DMA5_DEBUG_VERSION_SET                             0x0e000000
+      #define DMA5_DEBUG_VERSION_CLR                             0xf1ffffff
+      #define DMA5_DEBUG_VERSION_MSB                             27
+      #define DMA5_DEBUG_VERSION_LSB                             25
+      #define DMA5_DEBUG_DMA_STATE_BITS                          24:16
+      #define DMA5_DEBUG_DMA_STATE_SET                           0x01ff0000
+      #define DMA5_DEBUG_DMA_STATE_CLR                           0xfe00ffff
+      #define DMA5_DEBUG_DMA_STATE_MSB                           24
+      #define DMA5_DEBUG_DMA_STATE_LSB                           16
+      #define DMA5_DEBUG_DMA_ID_BITS                             15:8
+      #define DMA5_DEBUG_DMA_ID_SET                              0x0000ff00
+      #define DMA5_DEBUG_DMA_ID_CLR                              0xffff00ff
+      #define DMA5_DEBUG_DMA_ID_MSB                              15
+      #define DMA5_DEBUG_DMA_ID_LSB                              8
+      #define DMA5_DEBUG_OUTSTANDING_WRITES_BITS                 7:4
+      #define DMA5_DEBUG_OUTSTANDING_WRITES_SET                  0x000000f0
+      #define DMA5_DEBUG_OUTSTANDING_WRITES_CLR                  0xffffff0f
+      #define DMA5_DEBUG_OUTSTANDING_WRITES_MSB                  7
+      #define DMA5_DEBUG_OUTSTANDING_WRITES_LSB                  4
+      #define DMA5_DEBUG_READ_ERROR_BITS                         2:2
+      #define DMA5_DEBUG_READ_ERROR_SET                          0x00000004
+      #define DMA5_DEBUG_READ_ERROR_CLR                          0xfffffffb
+      #define DMA5_DEBUG_READ_ERROR_MSB                          2
+      #define DMA5_DEBUG_READ_ERROR_LSB                          2
+      #define DMA5_DEBUG_FIFO_ERROR_BITS                         1:1
+      #define DMA5_DEBUG_FIFO_ERROR_SET                          0x00000002
+      #define DMA5_DEBUG_FIFO_ERROR_CLR                          0xfffffffd
+      #define DMA5_DEBUG_FIFO_ERROR_MSB                          1
+      #define DMA5_DEBUG_FIFO_ERROR_LSB                          1
+      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_BITS            0:0
+      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_SET             0x00000001
+      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_CLR             0xfffffffe
+      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_MSB             0
+      #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_LSB             0
diff --git a/bcm2708_chip/axi_dma6.h b/bcm2708_chip/axi_dma6.h
new file mode 100755 (executable)
index 0000000..988f002
--- /dev/null
@@ -0,0 +1,257 @@
+// This file was generated by the create_regs script
+#define DMA6_BASE                                                0x7e007600
+#define DMA6_CS                                                  HW_REGISTER_RW( 0x7e007600 ) 
+   #define DMA6_CS_MASK                                          0xf0ff017f
+   #define DMA6_CS_WIDTH                                         32
+   #define DMA6_CS_RESET                                         0000000000
+      #define DMA6_CS_RESET_BITS                                 31:31
+      #define DMA6_CS_RESET_SET                                  0x80000000
+      #define DMA6_CS_RESET_CLR                                  0x7fffffff
+      #define DMA6_CS_RESET_MSB                                  31
+      #define DMA6_CS_RESET_LSB                                  31
+      #define DMA6_CS_ABORT_BITS                                 30:30
+      #define DMA6_CS_ABORT_SET                                  0x40000000
+      #define DMA6_CS_ABORT_CLR                                  0xbfffffff
+      #define DMA6_CS_ABORT_MSB                                  30
+      #define DMA6_CS_ABORT_LSB                                  30
+      #define DMA6_CS_DISDEBUG_BITS                              29:29
+      #define DMA6_CS_DISDEBUG_SET                               0x20000000
+      #define DMA6_CS_DISDEBUG_CLR                               0xdfffffff
+      #define DMA6_CS_DISDEBUG_MSB                               29
+      #define DMA6_CS_DISDEBUG_LSB                               29
+      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS           28:28
+      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_SET            0x10000000
+      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR            0xefffffff
+      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB            28
+      #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB            28
+      #define DMA6_CS_PANIC_PRIORITY_BITS                        23:20
+      #define DMA6_CS_PANIC_PRIORITY_SET                         0x00f00000
+      #define DMA6_CS_PANIC_PRIORITY_CLR                         0xff0fffff
+      #define DMA6_CS_PANIC_PRIORITY_MSB                         23
+      #define DMA6_CS_PANIC_PRIORITY_LSB                         20
+      #define DMA6_CS_PRIORITY_BITS                              19:16
+      #define DMA6_CS_PRIORITY_SET                               0x000f0000
+      #define DMA6_CS_PRIORITY_CLR                               0xfff0ffff
+      #define DMA6_CS_PRIORITY_MSB                               19
+      #define DMA6_CS_PRIORITY_LSB                               16
+      #define DMA6_CS_ERROR_BITS                                 8:8
+      #define DMA6_CS_ERROR_SET                                  0x00000100
+      #define DMA6_CS_ERROR_CLR                                  0xfffffeff
+      #define DMA6_CS_ERROR_MSB                                  8
+      #define DMA6_CS_ERROR_LSB                                  8
+      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS        6:6
+      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_SET         0x00000040
+      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR         0xffffffbf
+      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB         6
+      #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB         6
+      #define DMA6_CS_DREQ_STOPS_DMA_BITS                        5:5
+      #define DMA6_CS_DREQ_STOPS_DMA_SET                         0x00000020
+      #define DMA6_CS_DREQ_STOPS_DMA_CLR                         0xffffffdf
+      #define DMA6_CS_DREQ_STOPS_DMA_MSB                         5
+      #define DMA6_CS_DREQ_STOPS_DMA_LSB                         5
+      #define DMA6_CS_PAUSED_BITS                                4:4
+      #define DMA6_CS_PAUSED_SET                                 0x00000010
+      #define DMA6_CS_PAUSED_CLR                                 0xffffffef
+      #define DMA6_CS_PAUSED_MSB                                 4
+      #define DMA6_CS_PAUSED_LSB                                 4
+      #define DMA6_CS_DREQ_BITS                                  3:3
+      #define DMA6_CS_DREQ_SET                                   0x00000008
+      #define DMA6_CS_DREQ_CLR                                   0xfffffff7
+      #define DMA6_CS_DREQ_MSB                                   3
+      #define DMA6_CS_DREQ_LSB                                   3
+      #define DMA6_CS_INT_BITS                                   2:2
+      #define DMA6_CS_INT_SET                                    0x00000004
+      #define DMA6_CS_INT_CLR                                    0xfffffffb
+      #define DMA6_CS_INT_MSB                                    2
+      #define DMA6_CS_INT_LSB                                    2
+      #define DMA6_CS_END_BITS                                   1:1
+      #define DMA6_CS_END_SET                                    0x00000002
+      #define DMA6_CS_END_CLR                                    0xfffffffd
+      #define DMA6_CS_END_MSB                                    1
+      #define DMA6_CS_END_LSB                                    1
+      #define DMA6_CS_ACTIVE_BITS                                0:0
+      #define DMA6_CS_ACTIVE_SET                                 0x00000001
+      #define DMA6_CS_ACTIVE_CLR                                 0xfffffffe
+      #define DMA6_CS_ACTIVE_MSB                                 0
+      #define DMA6_CS_ACTIVE_LSB                                 0
+#define DMA6_CONBLK_AD                                           HW_REGISTER_RW( 0x7e007604 ) 
+   #define DMA6_CONBLK_AD_MASK                                   0xffffffe0
+   #define DMA6_CONBLK_AD_WIDTH                                  32
+   #define DMA6_CONBLK_AD_RESET                                  0000000000
+      #define DMA6_CONBLK_AD_SCB_ADDR_BITS                       31:5
+      #define DMA6_CONBLK_AD_SCB_ADDR_SET                        0xffffffe0
+      #define DMA6_CONBLK_AD_SCB_ADDR_CLR                        0x0000001f
+      #define DMA6_CONBLK_AD_SCB_ADDR_MSB                        31
+      #define DMA6_CONBLK_AD_SCB_ADDR_LSB                        5
+#define DMA6_TI                                                  HW_REGISTER_RO( 0x7e007608 ) 
+   #define DMA6_TI_MASK                                          0x07fffffb
+   #define DMA6_TI_WIDTH                                         27
+      #define DMA6_TI_NO_WIDE_BURSTS_BITS                        26:26
+      #define DMA6_TI_NO_WIDE_BURSTS_SET                         0x04000000
+      #define DMA6_TI_NO_WIDE_BURSTS_CLR                         0xfbffffff
+      #define DMA6_TI_NO_WIDE_BURSTS_MSB                         26
+      #define DMA6_TI_NO_WIDE_BURSTS_LSB                         26
+      #define DMA6_TI_WAITS_BITS                                 25:21
+      #define DMA6_TI_WAITS_SET                                  0x03e00000
+      #define DMA6_TI_WAITS_CLR                                  0xfc1fffff
+      #define DMA6_TI_WAITS_MSB                                  25
+      #define DMA6_TI_WAITS_LSB                                  21
+      #define DMA6_TI_PERMAP_BITS                                20:16
+      #define DMA6_TI_PERMAP_SET                                 0x001f0000
+      #define DMA6_TI_PERMAP_CLR                                 0xffe0ffff
+      #define DMA6_TI_PERMAP_MSB                                 20
+      #define DMA6_TI_PERMAP_LSB                                 16
+      #define DMA6_TI_BURST_LENGTH_BITS                          15:12
+      #define DMA6_TI_BURST_LENGTH_SET                           0x0000f000
+      #define DMA6_TI_BURST_LENGTH_CLR                           0xffff0fff
+      #define DMA6_TI_BURST_LENGTH_MSB                           15
+      #define DMA6_TI_BURST_LENGTH_LSB                           12
+      #define DMA6_TI_SRC_IGNORE_BITS                            11:11
+      #define DMA6_TI_SRC_IGNORE_SET                             0x00000800
+      #define DMA6_TI_SRC_IGNORE_CLR                             0xfffff7ff
+      #define DMA6_TI_SRC_IGNORE_MSB                             11
+      #define DMA6_TI_SRC_IGNORE_LSB                             11
+      #define DMA6_TI_SRC_DREQ_BITS                              10:10
+      #define DMA6_TI_SRC_DREQ_SET                               0x00000400
+      #define DMA6_TI_SRC_DREQ_CLR                               0xfffffbff
+      #define DMA6_TI_SRC_DREQ_MSB                               10
+      #define DMA6_TI_SRC_DREQ_LSB                               10
+      #define DMA6_TI_SRC_WIDTH_BITS                             9:9
+      #define DMA6_TI_SRC_WIDTH_SET                              0x00000200
+      #define DMA6_TI_SRC_WIDTH_CLR                              0xfffffdff
+      #define DMA6_TI_SRC_WIDTH_MSB                              9
+      #define DMA6_TI_SRC_WIDTH_LSB                              9
+      #define DMA6_TI_SRC_INC_BITS