Run astyle on codebase
authorAlyssa Rosenzweig <alyssa@rosenzweig.io>
Fri, 6 Jan 2017 19:30:33 +0000 (11:30 -0800)
committerAlyssa Rosenzweig <alyssa@rosenzweig.io>
Fri, 6 Jan 2017 19:30:33 +0000 (11:30 -0800)
14 files changed:
arm_chainloader/chainloader.h
arm_chainloader/drivers/mailbox.cc
arm_chainloader/drivers/mbr_disk.cc
arm_chainloader/drivers/sd_proto.hpp
arm_chainloader/drivers/sdhost_impl.cc
arm_chainloader/loader.cc
arm_chainloader/main.c
arm_loader.cc
arm_monitor.c
hardware.h
romstage.c
sdram.c
style.sh [changed mode: 0644->0755]
trap.c

index 6f416d2..7d838da 100644 (file)
@@ -11,7 +11,7 @@ extern "C" {
 \r
 static inline void __attribute__((noreturn)) hang_cpu() {\r
        __asm__ __volatile__ (\r
-               "wfi\n"\r
+           "wfi\n"\r
        );\r
 \r
        /* in case the above fails */\r
index b691094..93b967f 100644 (file)
@@ -25,7 +25,7 @@ Mailbox driver.
 template<typename T>
 static bool wait_for_mask(T& reg, uint32_t mask, bool is_set, int timeout) {
        while ((reg & mask) == (is_set ? 0 : mask)) {
-               if (timeout == 0) 
+               if (timeout == 0)
                        return false;
                timeout--;
                udelay(1);
index 2f2d021..fced100 100644 (file)
@@ -57,8 +57,8 @@ struct Mbr {
 \r
 static_assert(sizeof(Mbr) >= 512, "What the fuck");\r
 \r
-#define MBR_FAT16 0x04 \r
-#define MBR_FAT32 0x0B \r
+#define MBR_FAT16 0x04\r
+#define MBR_FAT32 0x0B\r
 #define MBR_FAT32_INT13 0x0C\r
 #define MBR_FAT16_INT13 0x0E\r
 #define MBR_LINUX 0x83\r
@@ -66,13 +66,20 @@ static_assert(sizeof(Mbr) >= 512, "What the fuck");
 \r
 static const char* mbr_fs_to_string(int fs) {\r
        switch (fs) {\r
-               case MBR_FAT32: return "FAT32"; \r
-               case MBR_FAT32_INT13: return "FAT32-INT13"; \r
-               case MBR_FAT16_INT13: return "FAT16-INT13";\r
-               case MBR_FAT16: return "FAT16";\r
-               case MBR_LINUX: return "Linux (ext2/ext3)";\r
-               case MBR_NTFS: return "NTFS";\r
-               default: return "<Unknown>";\r
+       case MBR_FAT32:\r
+               return "FAT32";\r
+       case MBR_FAT32_INT13:\r
+               return "FAT32-INT13";\r
+       case MBR_FAT16_INT13:\r
+               return "FAT16-INT13";\r
+       case MBR_FAT16:\r
+               return "FAT16";\r
+       case MBR_LINUX:\r
+               return "Linux (ext2/ext3)";\r
+       case MBR_NTFS:\r
+               return "NTFS";\r
+       default:\r
+               return "<Unknown>";\r
        }\r
 }\r
 \r
@@ -96,7 +103,7 @@ struct MbrImpl {
        inline int get_partition_type(uint8_t volume) {\r
                if (volume > 3)\r
                        return 0;\r
-               return mbr->mbr_part[volume].part_typ;  \r
+               return mbr->mbr_part[volume].part_typ;\r
        }\r
 \r
        bool read_block(uint8_t volume, uint32_t sector, uint32_t* buf) {\r
@@ -119,7 +126,7 @@ struct MbrImpl {
                }\r
 \r
                if (!validate_signature()) {\r
-                        panic("invalid master boot record signature (got 0x%x)", mbr->mbr_sig);\r
+                       panic("invalid master boot record signature (got 0x%x)", mbr->mbr_sig);\r
                }\r
 \r
                logf("MBR contents:\n");\r
@@ -159,13 +166,13 @@ DSTATUS disk_initialize (BYTE pdrv) {
 \r
        BYTE pt = g_MbrDisk.get_partition_type(pdrv);\r
        switch (pt) {\r
-               case MBR_FAT32_INT13:\r
-               case MBR_FAT16_INT13:\r
-               case MBR_FAT32:\r
-               case MBR_FAT16:\r
-                       logf("Mounting FAT partition %d of type 0x%x\n", pdrv, pt);\r
-                       g_FatFsDiskInitialized = true;\r
-                       return static_cast<DRESULT>(0);\r
+       case MBR_FAT32_INT13:\r
+       case MBR_FAT16_INT13:\r
+       case MBR_FAT32:\r
+       case MBR_FAT16:\r
+               logf("Mounting FAT partition %d of type 0x%x\n", pdrv, pt);\r
+               g_FatFsDiskInitialized = true;\r
+               return static_cast<DRESULT>(0);\r
        }\r
        logf("Disk %d isn't a FAT volume (partition type is 0x%x)!\n", pdrv, pt);\r
        return STA_NOINIT;\r
@@ -176,8 +183,7 @@ DSTATUS disk_status (BYTE pdrv) {
 }\r
 \r
 DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count) {\r
-       while (count--)\r
-       {\r
+       while (count--) {\r
                g_MbrDisk.read_block(pdrv, sector, buff);\r
                sector++;\r
                buff += g_MbrDisk.get_block_size();\r
@@ -186,21 +192,20 @@ DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count) {
 }\r
 \r
 DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff) {\r
-       switch (cmd)\r
-       {\r
-               case CTRL_SYNC:\r
-                       return (DRESULT)0;\r
-               case GET_SECTOR_SIZE:\r
-                       *(WORD*)buff = g_MbrDisk.get_block_size();\r
-                       return (DRESULT)0;\r
-\r
-               case GET_SECTOR_COUNT:\r
-                       *(WORD*)buff = 0;\r
-                       return (DRESULT)0;\r
-\r
-               case GET_BLOCK_SIZE:\r
-                       *(WORD*)buff = 1;\r
-                       return (DRESULT)0;\r
+       switch (cmd) {\r
+       case CTRL_SYNC:\r
+               return (DRESULT)0;\r
+       case GET_SECTOR_SIZE:\r
+               *(WORD*)buff = g_MbrDisk.get_block_size();\r
+               return (DRESULT)0;\r
+\r
+       case GET_SECTOR_COUNT:\r
+               *(WORD*)buff = 0;\r
+               return (DRESULT)0;\r
+\r
+       case GET_BLOCK_SIZE:\r
+               *(WORD*)buff = 1;\r
+               return (DRESULT)0;\r
        }\r
        return RES_PARERR;\r
 }\r
index 4aaf5bf..d6163da 100644 (file)
 \r
 #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start), (len))\r
 static inline int\r
-__bitfield(uint32_t *src, int start, int len)\r
-{\r
+__bitfield(uint32_t *src, int start, int len) {\r
        uint8_t *sp;\r
        uint32_t dst, mask;\r
        int shift, bs, bc;\r
index ebe5af2..8406cb1 100644 (file)
@@ -79,8 +79,8 @@ struct BCM2708GPIO {
 \r
        static void set(uint32_t pin_num, BCM2708PinmuxSetting setting) {\r
                uint32_t* fsel = reinterpret_cast<uint32_t*>(\r
-                       reinterpret_cast<uint32_t>(&GP_FSEL0) + (0x4 * (pin_num/10))\r
-               );\r
+                                    reinterpret_cast<uint32_t>(&GP_FSEL0) + (0x4 * (pin_num/10))\r
+                                );\r
                uint32_t pin_shift = (pin_num % 10) * 3;\r
 \r
 \r
@@ -136,7 +136,7 @@ struct BCM2708SDHost : BlockDevice {
 \r
                sts = SH_HSTS;\r
                if (sts & SDHSTS_ERROR_MASK)\r
-                       SH_HSTS = sts; \r
+                       SH_HSTS = sts;\r
 \r
                current_cmd = command & SH_CMD_COMMAND_SET;\r
 \r
@@ -197,13 +197,13 @@ struct BCM2708SDHost : BlockDevice {
                SH_HCFG = 0;\r
                SH_HBCT = 0;\r
                SH_HBLC = 0;\r
-       \r
+\r
                uint32_t temp = SH_EDM;\r
 \r
                temp &= ~((SDEDM_THRESHOLD_MASK<<SDEDM_READ_THRESHOLD_SHIFT) |\r
-                 (SDEDM_THRESHOLD_MASK<<SDEDM_WRITE_THRESHOLD_SHIFT));\r
+                         (SDEDM_THRESHOLD_MASK<<SDEDM_WRITE_THRESHOLD_SHIFT));\r
                temp |= (SAFE_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |\r
-                       (SAFE_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);\r
+                       (SAFE_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);\r
 \r
                SH_EDM = temp;\r
                udelay(300);\r
@@ -237,7 +237,7 @@ struct BCM2708SDHost : BlockDevice {
                        logf("ERROR: unknown error, SH_CMD=0x%x\n", SH_CMD);\r
                        return false;\r
                }\r
-               \r
+\r
 \r
                return true;\r
        }\r
@@ -291,7 +291,7 @@ struct BCM2708SDHost : BlockDevice {
 \r
        bool identify_card() {\r
                logf("identifying card ...\n");\r
-               \r
+\r
                send_136_resp(MMC_ALL_SEND_CID);\r
                if (!wait_and_get_response())\r
                        return false;\r
@@ -400,7 +400,7 @@ struct BCM2708SDHost : BlockDevice {
 \r
 \r
                        volatile uint32_t data = SH_DATA;\r
-                       \r
+\r
 #ifdef DUMP_READ\r
                        printf("%08x ", data);\r
 #endif\r
@@ -471,8 +471,7 @@ struct BCM2708SDHost : BlockDevice {
                        capacity_bytes = (SD_CSD_V2_CAPACITY(csd) * block_length);\r
 \r
                        clock_div = 5;\r
-               }\r
-               else if (SD_CSD_CSDVER(csd) == SD_CSD_CSDVER_1_0) {\r
+               } else if (SD_CSD_CSDVER(csd) == SD_CSD_CSDVER_1_0) {\r
                        printf("    CSD     : Ver 1.0\n");\r
                        printf("    Capacity: %d\n", SD_CSD_CAPACITY(csd));\r
                        printf("    Size    : %d\n", SD_CSD_C_SIZE(csd));\r
@@ -483,12 +482,11 @@ struct BCM2708SDHost : BlockDevice {
                        capacity_bytes = (SD_CSD_CAPACITY(csd) * block_length);\r
 \r
                        clock_div = 10;\r
-               }\r
-               else {\r
+               } else {\r
                        printf("ERROR: Unknown CSD version 0x%x!\n", SD_CSD_CSDVER(csd));\r
                        return false;\r
                }\r
-       \r
+\r
                printf("    BlockLen: 0x%x\n", block_length);\r
 \r
                if (!select_card()) {\r
@@ -498,7 +496,7 @@ struct BCM2708SDHost : BlockDevice {
 \r
                if (SD_CSD_CSDVER(csd) == SD_CSD_CSDVER_1_0) {\r
                        /*\r
-                        * only needed for 1.0 ones, the 2.0 ones have this \r
+                        * only needed for 1.0 ones, the 2.0 ones have this\r
                         * fixed at 512.\r
                         */\r
                        logf("Setting block length to 512 ...\n");\r
@@ -530,10 +528,10 @@ struct BCM2708SDHost : BlockDevice {
                is_sdhc = false;\r
 \r
                logf("hcfg 0x%X, cdiv 0x%X, edm 0x%X, hsts 0x%X\n",\r
-                       SH_HCFG,\r
-                       SH_CDIV,\r
-                       SH_EDM,\r
-                       SH_HSTS);\r
+                    SH_HCFG,\r
+                    SH_CDIV,\r
+                    SH_EDM,\r
+                    SH_HSTS);\r
 \r
                logf("Restarting the eMMC controller ...\n");\r
 \r
@@ -558,8 +556,7 @@ struct BCM2708SDHost : BlockDevice {
                                        panic("fifo flush cycle %d failed", i);\r
                                }\r
                        }\r
-               }\r
-               else {\r
+               } else {\r
                        panic("failed to reinitialize the eMMC controller");\r
                }\r
        }\r
@@ -595,7 +592,7 @@ struct BCM2708SDHost : BlockDevice {
 \r
                SH_CMD = 0;\r
                SH_ARG = 0;\r
-       }\r
+       }\r
 \r
        BCM2708SDHost() {\r
                restart_controller();\r
index bf13fa1..adc00de 100644 (file)
@@ -35,7 +35,7 @@ FATFS g_BootVolumeFs;
 typedef void (*linux_t)(uint32_t, uint32_t, void*);
 
 static_assert((MEM_USABLE_START+0x800000) < KERNEL_LOAD_ADDRESS,
-       "memory layout would not allow for kernel to be loaded at KERNEL_LOAD_ADDRESS, please check memory_map.h");
+              "memory layout would not allow for kernel to be loaded at KERNEL_LOAD_ADDRESS, please check memory_map.h");
 
 struct LoaderImpl {
        inline bool file_exists(const char* path) {
@@ -45,10 +45,10 @@ struct LoaderImpl {
        size_t read_file(const char* path, uint8_t*& dest, bool should_alloc = true) {
                /* ensure file exists first */
                if(!file_exists(path))
-                   panic("attempted to read %s, but it does not exist", path);
+                       panic("attempted to read %s, but it does not exist", path);
 
                /* read entire file into buffer */
-               FIL fp; 
+               FIL fp;
                f_open(&fp, path, FA_READ);
 
                unsigned int len = f_size(&fp);
@@ -85,14 +85,14 @@ struct LoaderImpl {
 
                int node = fdt_path_offset(v_fdt, "/chosen");
                if (node < 0)
-                   panic("no chosen node in fdt");
+                       panic("no chosen node in fdt");
 
                res = fdt_setprop(v_fdt, node, "bootargs", cmdline, strlen((char*) cmdline) + 1);
 
                /* pass in a memory map, skipping first meg for bootcode */
                int memory = fdt_path_offset(v_fdt, "/memory");
                if(memory < 0)
-                   panic("no memory node in fdt");
+                       panic("no memory node in fdt");
 
                /* start the memory map at 1M/16 and grow continuous for 256M
                 * TODO: does this disrupt I/O? */
@@ -112,7 +112,7 @@ struct LoaderImpl {
                        bd->stop();
        }
 
-       LoaderImpl() {  
+       LoaderImpl() {
                logf("Mounting boot partitiion ...\n");
                FRESULT r = f_mount(&g_BootVolumeFs, ROOT_VOLUME_PREFIX, 1);
                if (r != FR_OK) {
@@ -126,7 +126,7 @@ struct LoaderImpl {
 
                cmdline[cmdlen - 1] = 0;
                logf("kernel cmdline: %s\n", cmdline);
-               
+
                /* load flat device tree */
                uint8_t* fdt = load_fdt("rpi.dtb", cmdline);
 
index d3961f2..0962ea2 100644 (file)
@@ -15,26 +15,35 @@ static void heap_init() {
 
        init_memory_pool(hs, start_of_heap);
 }
+
 static const char* get_execution_mode_name() {
        uint32_t cpsr = arm_get_cpsr() & ARM32_MODE_MASK;
 
        switch (cpsr) {
-               case ARM32_USR: return "User";
-               case ARM32_FIQ: return "FIQ";
-               case ARM32_IRQ: return "IRQ";
-               case ARM32_SVC: return "Supervisor";
-               case ARM32_MON: return "Secure Monitor";
-               case ARM32_ABT: return "Abort";
-               case ARM32_UND: return "Undefined Instruction";
-               case ARM32_HYP: return "Hypervisor";
-               case ARM32_SYS: return "System";
-               default: return "Unknown Mode";
+       case ARM32_USR:
+               return "User";
+       case ARM32_FIQ:
+               return "FIQ";
+       case ARM32_IRQ:
+               return "IRQ";
+       case ARM32_SVC:
+               return "Supervisor";
+       case ARM32_MON:
+               return "Secure Monitor";
+       case ARM32_ABT:
+               return "Abort";
+       case ARM32_UND:
+               return "Undefined Instruction";
+       case ARM32_HYP:
+               return "Hypervisor";
+       case ARM32_SYS:
+               return "System";
+       default:
+               return "Unknown Mode";
        }
 }
 
-void main(bool security_supported)
-{
+void main(bool security_supported) {
        /* wait for peripheral access */
        while(ARM_ID != ARM_IDVAL);
        udelay(500);
@@ -42,8 +51,8 @@ void main(bool security_supported)
        logf("Started on ARM, continuing boot from here ...\n");
 
        logf("Firmware data: SDRAM_SIZE=%d, VPU_CPUID=0x%X\n",
-               g_FirmwareData.sdram_size,
-               g_FirmwareData.vpu_cpuid);
+            g_FirmwareData.sdram_size,
+            g_FirmwareData.vpu_cpuid);
 
        if (security_supported) {
                logf("Security extensions are supported!\n");
index ff007bd..e3281c8 100644 (file)
@@ -76,7 +76,7 @@ static void enable_power() {
        udelay(10);\r
        PM_PROC = pmv;\r
 \r
-       logf("POWUP PM_PROC: 0x%X\n", PM_PROC); \r
+       logf("POWUP PM_PROC: 0x%X\n", PM_PROC);\r
 \r
        /* wait for POWOK */\r
        logf("waiting for power up ...\n");\r
@@ -92,7 +92,7 @@ static void enable_power() {
                        PM_PROC = pmv;\r
                }\r
        }\r
-       \r
+\r
        pmv |= PM_PROC_ISPOW_SET;\r
        PM_PROC = pmv;\r
 \r
@@ -128,7 +128,7 @@ static uint32_t g_BrespTab[] = {
 static void do_bresp_cycle() {\r
        /* my little axi - peripherals are magic */\r
        logf("Cycling AXI bits ...\n\t");\r
-       \r
+\r
        for (int i = 0; i < sizeof(g_BrespTab)/sizeof(g_BrespTab[0]); i++) {\r
                bresp_cycle_write(g_BrespTab[i]);\r
 \r
@@ -141,7 +141,7 @@ static void do_bresp_cycle() {
 \r
 void setup_bridge(bool bresp_cycle) {\r
        logf("setting up async bridge ...\n");\r
\r
+\r
        if (bresp_cycle) {\r
                assert_global_reset();\r
                do_bresp_cycle();\r
@@ -153,9 +153,9 @@ void setup_bridge(bool bresp_cycle) {
        ARM_CONTROL1 &= ~ARM_C1_REQSTOP;\r
        udelay(300);\r
 \r
-       if (!bresp_cycle) \r
+       if (!bresp_cycle)\r
                assert_global_reset();\r
-       \r
+\r
        logf("bridge init done, PM_PROC is now: 0x%X!\n", PM_PROC);\r
 }\r
 \r
@@ -222,8 +222,8 @@ static void arm_load_code() {
                uint8_t* mem8 = (uint8_t*)(mem);\r
                if (start[i] != mem8[i])\r
                        panic("copy failed at 0x%X expected 0x%X, got 0x%X", (uint32_t)&mem8[i],\r
-                               *((uint32_t*)&mem8[i]),\r
-                               *((uint32_t*)&start[i]));\r
+                             *((uint32_t*)&mem8[i]),\r
+                             *((uint32_t*)&start[i]));\r
        }\r
 }\r
 \r
@@ -233,7 +233,7 @@ static void arm_pmap_enter(uint32_t bus_address, uint32_t arm_address) {
        uint32_t index = arm_address >> 24;\r
        uint32_t pte = bus_address >> 21;\r
 \r
-       tte[index] = pte; \r
+       tte[index] = pte;\r
 \r
        //logf("Translation: [0x%X => 0x%X] 0x%X => 0x%X\n", index * 4, bus_address >> 21, bus_address, arm_address);\r
 }\r
index 122b6d2..3de7119 100644 (file)
@@ -25,8 +25,8 @@ First stage monitor.
  */\r
 void arm_monitor_interrupt() {\r
        printf("VPU MBOX rcv: 0x%X, cnf 0x%X\n",\r
-               ARM_1_MAIL1_RD,\r
-               ARM_1_MAIL1_CNF);\r
+              ARM_1_MAIL1_RD,\r
+              ARM_1_MAIL1_CNF);\r
 }\r
 \r
 void monitor_start() {\r
index 5bbcdf5..37ea961 100644 (file)
@@ -28,11 +28,11 @@ that are missing from the release. This is also used by ARM.
 #define VC4_CPUID_BCM2709_PLUS 0x40\r
 \r
 #ifdef __arm__\r
-       #define HW_REGISTER_RW(addr) (*(volatile unsigned int *)(VC4_TO_ARM_PERIPH(addr)))  \r
-       #define HW_REGISTER_RO(addr) (*(const volatile unsigned int *)(VC4_TO_ARM_PERIPH(addr)))\r
+#define HW_REGISTER_RW(addr) (*(volatile unsigned int *)(VC4_TO_ARM_PERIPH(addr)))\r
+#define HW_REGISTER_RO(addr) (*(const volatile unsigned int *)(VC4_TO_ARM_PERIPH(addr)))\r
 #else\r
-       #define HW_REGISTER_RW(addr) (*(volatile unsigned int *)(addr))  \r
-       #define HW_REGISTER_RO(addr) (*(const volatile unsigned int *)(addr))\r
+#define HW_REGISTER_RW(addr) (*(volatile unsigned int *)(addr))\r
+#define HW_REGISTER_RO(addr) (*(const volatile unsigned int *)(addr))\r
 #endif\r
 \r
 #define mmio_read32(addr) HW_REGISTER_RW(addr)\r
index aa7879b..b4899c4 100644 (file)
@@ -41,8 +41,7 @@ uint32_t g_CPUID;
 #define UART_ITOP   (UART_BASE+0x88)\r
 #define UART_TDR    (UART_BASE+0x8C)\r
 \r
-void uart_putc(unsigned int ch)\r
-{\r
+void uart_putc(unsigned int ch) {\r
        while(UART_MSR & 0x20);\r
        UART_RBRTHRDLL = ch;\r
 }\r
@@ -111,7 +110,7 @@ void switch_vpu_to_pllc() {
 \r
        A2W_PLLC_FRAC = A2W_PASSWORD | 87380;\r
        A2W_PLLC_CTRL = A2W_PASSWORD | 52 | 0x1000;\r
-       \r
+\r
        A2W_PLLC_ANA3 = A2W_PASSWORD | 0x100;\r
        A2W_PLLC_ANA2 = A2W_PASSWORD | 0x0;\r
        A2W_PLLC_ANA1 = A2W_PASSWORD | 0x144000;\r
@@ -121,8 +120,8 @@ void switch_vpu_to_pllc() {
 \r
        /* hold all */\r
        CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |\r
-               CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
-               CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;\r
+                 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
+                 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;\r
 \r
        A2W_PLLC_DIG3 = A2W_PASSWORD | 0x0;\r
        A2W_PLLC_DIG2 = A2W_PASSWORD | 0x400000;\r
@@ -139,16 +138,16 @@ void switch_vpu_to_pllc() {
        A2W_PLLC_CORE0 = A2W_PASSWORD | 2;\r
 \r
        CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |\r
-               CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
-               CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET | CM_PLLC_LOADCORE0_SET;\r
+                 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
+                 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET | CM_PLLC_LOADCORE0_SET;\r
 \r
        CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |\r
-               CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
-               CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;\r
+                 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
+                 CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET;\r
 \r
        CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET |\r
-               CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
-               CM_PLLC_HOLDCORE1_SET;\r
+                 CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET |\r
+                 CM_PLLC_HOLDCORE1_SET;\r
 \r
        CM_VPUCTL = CM_PASSWORD | CM_VPUCTL_FRAC_SET | CM_SRC_OSC | CM_VPUCTL_GATE_SET;\r
        CM_VPUDIV = CM_PASSWORD | (4 << 12);\r
@@ -174,16 +173,16 @@ int _main(unsigned int cpuid, unsigned int load_address) {
        uart_init();\r
 \r
        printf(\r
-               "==================================================================\n"\r
-               "::\n"\r
-               ":: kFW for bcm270x, Copyright 2016-2017 rpi-open-firmware authors \n"\r
-               "::\n"\r
-               ":: BUILDATE  : %s %s \n"\r
-               ":: BUILDSTYLE: %s \n"\r
-               "::\n"\r
-               "==================================================================\n",\r
-               __DATE__, __TIME__,\r
-               "OPENSOURCE"\r
+           "==================================================================\n"\r
+           "::\n"\r
+           ":: kFW for bcm270x, Copyright 2016-2017 rpi-open-firmware authors \n"\r
+           "::\n"\r
+           ":: BUILDATE  : %s %s \n"\r
+           ":: BUILDSTYLE: %s \n"\r
+           "::\n"\r
+           "==================================================================\n",\r
+           __DATE__, __TIME__,\r
+           "OPENSOURCE"\r
        );\r
 \r
        printf("CPUID    = 0x%X\n", cpuid);\r
diff --git a/sdram.c b/sdram.c
index e69428b..47ca064 100644 (file)
--- a/sdram.c
+++ b/sdram.c
@@ -33,7 +33,7 @@ VideoCoreIV SDRAM initialization code.
  PT1:\r
        Minimum Idle time after first CKE assertion\r
        Minimum CKE low time after completion of power ramp\r
- PT2: \r
+ PT2:\r
        DAI Duration\r
  */\r
 \r
@@ -56,13 +56,20 @@ uint32_t g_RAMSize = RAM_SIZE_UNKNOWN;
 \r
 static const char* lpddr2_manufacturer_name(uint32_t mr) {\r
        switch (mr) {\r
-               case 1: return "Samsung";\r
-               case 2: return "Qimonda";\r
-               case 3: return "Elpida";\r
-               case 4: return "Etron";\r
-               case 5: return "Nanya";\r
-               case 6: return "Hynix";\r
-               default: return "Unknown";\r
+       case 1:\r
+               return "Samsung";\r
+       case 2:\r
+               return "Qimonda";\r
+       case 3:\r
+               return "Elpida";\r
+       case 4:\r
+               return "Etron";\r
+       case 5:\r
+               return "Nanya";\r
+       case 6:\r
+               return "Hynix";\r
+       default:\r
+               return "Unknown";\r
        }\r
 }\r
 \r
@@ -71,11 +78,16 @@ static const char* lpddr2_manufacturer_name(uint32_t mr) {
 \r
 static unsigned lpddr2_size(uint32_t mr) {\r
        switch (mr) {\r
-               case 0x58: return RAM_SIZE_1GB;\r
-               case 0x18: return RAM_SIZE_512MB;\r
-               case 0x14: return RAM_SIZE_256MB;\r
-               case 0x10: return RAM_SIZE_128MB;\r
-               default: return RAM_SIZE_UNKNOWN;\r
+       case 0x58:\r
+               return RAM_SIZE_1GB;\r
+       case 0x18:\r
+               return RAM_SIZE_512MB;\r
+       case 0x14:\r
+               return RAM_SIZE_256MB;\r
+       case 0x10:\r
+               return RAM_SIZE_128MB;\r
+       default:\r
+               return RAM_SIZE_UNKNOWN;\r
        }\r
 }\r
 \r
@@ -113,13 +125,13 @@ ALWAYS_INLINE void reset_phy_dll() {
 \r
        DPHY_CSR_GLBL_DQ_DLL_RESET = 0x1;\r
        APHY_CSR_GLBL_ADDR_DLL_RESET = 0x1;\r
-       \r
+\r
        /* stall ... */\r
        SD_CS;\r
        SD_CS;\r
        SD_CS;\r
        SD_CS;\r
-       \r
+\r
        DPHY_CSR_GLBL_DQ_DLL_RESET = 0x0;\r
        APHY_CSR_GLBL_ADDR_DLL_RESET = 0x0;\r
 \r
@@ -233,52 +245,52 @@ void reset_with_timing(lpddr2_timings_t* T) {
        clkman_update_end();\r
 \r
        SD_SA =\r
-               (T->tREFI << SD_SA_RFSH_T_LSB)\r
-                       | SD_SA_PGEHLDE_SET\r
-                       | SD_SA_CLKSTOP_SET\r
-                       | SD_SA_POWSAVE_SET\r
-                       | 0x3214;\r
+           (T->tREFI << SD_SA_RFSH_T_LSB)\r
+           | SD_SA_PGEHLDE_SET\r
+           | SD_SA_CLKSTOP_SET\r
+           | SD_SA_POWSAVE_SET\r
+           | 0x3214;\r
 \r
        SD_SB =\r
-               SD_SB_REORDER_SET\r
-                       | (T->banklow << SD_SB_BANKLOW_LSB)\r
-                       | SD_SB_EIGHTBANK_SET\r
-                       | (T->rowbits << SD_SB_ROWBITS_LSB)\r
-                       | (T->colbits << SD_SB_COLBITS_LSB);\r
+           SD_SB_REORDER_SET\r
+           | (T->banklow << SD_SB_BANKLOW_LSB)\r
+           | SD_SB_EIGHTBANK_SET\r
+           | (T->rowbits << SD_SB_ROWBITS_LSB)\r
+           | (T->colbits << SD_SB_COLBITS_LSB);\r
 \r
        logf("SDRAM Addressing Mode: Bank=%d Row=%d Col=%d SB=0x%X\n", T->banklow, T->rowbits, T->colbits, SD_SB);\r
 \r
        SD_SC =\r
-               (T->tRFCab << SD_SC_T_RFC_LSB)\r
-                       | (T->tRRD << SD_SC_T_RRD_LSB)\r
-                       | (T->tWR << SD_SC_T_WR_LSB)\r
-                       | (T->tWTR << SD_SC_T_WTR_LSB)\r
-                       | (3 << SD_SC_WL_LSB);\r
+           (T->tRFCab << SD_SC_T_RFC_LSB)\r
+           | (T->tRRD << SD_SC_T_RRD_LSB)\r
+           | (T->tWR << SD_SC_T_WR_LSB)\r
+           | (T->tWTR << SD_SC_T_WTR_LSB)\r
+           | (3 << SD_SC_WL_LSB);\r
 \r
        SD_SD =\r
-               (T->tRPab << SD_SD_T_RPab_LSB)\r
-                       | (T->tRC << SD_SD_T_RC_LSB)\r
-                       | (T->tXP << SD_SD_T_XP_LSB)\r
-                       | (T->tRASmin << SD_SD_T_RAS_LSB)\r
-                       | (T->tRPpb << SD_SD_T_RPpb_LSB)\r
-                       | (T->tRCD << SD_SD_T_RCD_LSB);\r
+           (T->tRPab << SD_SD_T_RPab_LSB)\r
+           | (T->tRC << SD_SD_T_RC_LSB)\r
+           | (T->tXP << SD_SD_T_XP_LSB)\r
+           | (T->tRASmin << SD_SD_T_RAS_LSB)\r
+           | (T->tRPpb << SD_SD_T_RPpb_LSB)\r
+           | (T->tRCD << SD_SD_T_RCD_LSB);\r
 \r
        SD_SE =\r
-               (1 << SD_SE_RL_EN_LSB)\r
-                       | (4 << SD_SE_RL_LSB)\r
-                       | (T->tFAW << SD_SE_T_FAW_LSB)\r
-                       | (T->tRTP << SD_SE_T_RTP_LSB)\r
-                       | (T->tXSR << SD_SE_T_XSR_LSB);\r
+           (1 << SD_SE_RL_EN_LSB)\r
+           | (4 << SD_SE_RL_LSB)\r
+           | (T->tFAW << SD_SE_T_FAW_LSB)\r
+           | (T->tRTP << SD_SE_T_RTP_LSB)\r
+           | (T->tXSR << SD_SE_T_XSR_LSB);\r
 \r
        SD_PT1 =\r
-               (T->tINIT3 << SD_PT1_T_INIT3_LSB)\r
-                       | (T->tINIT1 << SD_PT1_T_INIT1_LSB);\r
+           (T->tINIT3 << SD_PT1_T_INIT3_LSB)\r
+           | (T->tINIT1 << SD_PT1_T_INIT1_LSB);\r
 \r
        SD_PT2 =\r
-               T->tINIT5 << SD_PT2_T_INIT5_LSB;\r
+           T->tINIT5 << SD_PT2_T_INIT5_LSB;\r
 \r
        SD_MRT =\r
-               0x3 << SD_MRT_T_MRW_LSB;\r
+           0x3 << SD_MRT_T_MRW_LSB;\r
 \r
        reset_phy_dll();\r
 \r
@@ -292,10 +304,10 @@ void reset_with_timing(lpddr2_timings_t* T) {
 \r
        /* woo, turn on sdram! */\r
        SD_CS =\r
-               (((4 << SD_CS_ASHDN_T_LSB)\r
-                       | SD_CS_STATEN_SET\r
-                       | SD_CS_EN_SET)\r
-               & ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET;\r
+           (((4 << SD_CS_ASHDN_T_LSB)\r
+             | SD_CS_STATEN_SET\r
+             | SD_CS_EN_SET)\r
+            & ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET;\r
 }\r
 \r
 unsigned int read_mr(unsigned int addr) {\r
@@ -310,7 +322,7 @@ unsigned int write_mr(unsigned int addr, unsigned int data, bool wait) {
        while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}\r
 \r
        SD_MR = (addr & 0xFF) | ((data & 0xFF) << 8) | SD_MR_RW_SET;\r
-       \r
+\r
        if (wait) {\r
                unsigned int mrr;\r
                while (((mrr = SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}\r
@@ -319,8 +331,7 @@ unsigned int write_mr(unsigned int addr, unsigned int data, bool wait) {
                        panic("MR write timed out (addr=%d data=0x%X)", addr, data);\r
 \r
                return mrr;\r
-       }\r
-       else {\r
+       } else {\r
                return 0;\r
        }\r
 }\r
@@ -356,8 +367,7 @@ static void switch_to_cprman_clock(unsigned int source, unsigned int div) {
        logf("busy set, switch complete!\n");\r
 }\r
 \r
-static void init_clkman()\r
-{\r
+static void init_clkman() {\r
        uint32_t ctrl = 0;\r
 \r
        clkman_update_begin();\r
@@ -365,7 +375,7 @@ static void init_clkman()
        clkman_update_end();\r
 }\r
 \r
-       #define CALL_INIT_CLKMAN init_clkman();\r
+#define CALL_INIT_CLKMAN init_clkman();\r
 \r
 \r
 /*****************************************************************************\r
@@ -460,8 +470,7 @@ static void selftest_at(uint32_t addr) {
        }\r
 }\r
 \r
-static void selftest()\r
-{\r
+static void selftest() {\r
        logf("Starting self test ...\n");\r
 \r
        selftest_at(RT_BASE);\r
@@ -490,7 +499,7 @@ void sdram_init() {
        PM_SMPS = PM_PASSWORD | 0x1;\r
        A2W_SMPS_LDO1 = A2W_PASSWORD | 0x40000;\r
        A2W_SMPS_LDO0 = A2W_PASSWORD | 0x0;\r
-       \r
+\r
        A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_DDREN_SET;\r
 \r
        /*\r
@@ -511,7 +520,7 @@ void sdram_init() {
        SD_SC = 0x6000431;\r
        SD_SD = 0x10000011;\r
        SD_SE = 0x10106000;\r
-       SD_PT1 = 0x0AF002; \r
+       SD_PT1 = 0x0AF002;\r
        SD_PT2 = 0x8C;\r
        SD_MRT = 0x3;\r
        SD_CS = 0x200042;\r
@@ -520,7 +529,7 @@ void sdram_init() {
        logf("waiting for SDUP (%X) ...\n", SD_CS);\r
        for (;;) if (SD_CS & SD_CS_SDUP_SET) break;\r
        logf("SDRAM controller has arrived! (%X)\n", SD_CS);\r
-       \r
+\r
        /* RL = 6 / WL = 3 */\r
        write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, false);\r
        calibrate_pvt_early();\r
@@ -541,9 +550,9 @@ void sdram_init() {
        g_RAMSize = lpddr2_size(bc);\r
 \r
        logf("SDRAM Type: %s %s LPDDR2 (BC=0x%X)\n",\r
-               lpddr2_manufacturer_name(vendor_id),\r
-               size_to_string[g_RAMSize],\r
-               bc);\r
+            lpddr2_manufacturer_name(vendor_id),\r
+            size_to_string[g_RAMSize],\r
+            bc);\r
 \r
        if (g_RAMSize == RAM_SIZE_UNKNOWN)\r
                panic("unknown ram size (MR8 response was 0x%X)", bc);\r
@@ -563,8 +572,7 @@ void sdram_init() {
                g_InitSdramParameters.colbits = 3;\r
                g_InitSdramParameters.rowbits = 3;\r
                g_InitSdramParameters.banklow = 3;\r
-       }\r
-       else if (g_RAMSize == RAM_SIZE_512MB) {\r
+       } else if (g_RAMSize == RAM_SIZE_512MB) {\r
                logf("*** USING LOW tREFI (~7.8us) FOR 512MB, YOUR RAM MAY LEAK!!!!\n");\r
 \r
                g_InitSdramParameters.colbits = 2;\r
old mode 100644 (file)
new mode 100755 (executable)
index 487fc6e..049c27f
--- a/style.sh
+++ b/style.sh
@@ -5,7 +5,7 @@
 
 # a handful of subprojects (BCM headers, libfdt, etc.) are included in-tree
 # to avoid create merge conflicts when pulling upstream, only style our code
-FILES="*.c *.h arm_chainloader/*.c arm_chainloader/*.cc arm_chainloader/*.h arm_chainloader/drivers/*.cc arm_chainloader/drivers/*.hpp"
+FILES="*.c *.cc *.h arm_chainloader/*.c arm_chainloader/*.cc arm_chainloader/*.h arm_chainloader/drivers/*.cc arm_chainloader/drivers/*.hpp"
 
 # run astyle with tabs and attached braces
 astyle --style=attach --indent=tab $FILES
diff --git a/trap.c b/trap.c
index dbaaa1a..c311008 100644 (file)
--- a/trap.c
+++ b/trap.c
@@ -42,50 +42,50 @@ static void print_vpu_state(vc4_saved_state_t* pcb) {
        printf("VPU registers:\n");\r
 \r
        printf(\r
-               REGISTER_FORMAT_STRING("   "),\r
-               pcb->r0,\r
-               pcb->r1,\r
-               pcb->r2,\r
-               pcb->r3,\r
-               pcb->r4,\r
-               pcb->r5,\r
-               pcb->r6,\r
-               pcb->r7,\r
-               pcb->r8,\r
-               pcb->r9, \r
-               pcb->r10,\r
-               pcb->r11,\r
-               pcb->r12,\r
-               pcb->r13,\r
-               pcb->r14,\r
-               pcb->r15,\r
-               pcb->pc,\r
-               pcb->lr,\r
-               pcb->sr\r
+           REGISTER_FORMAT_STRING("   "),\r
+           pcb->r0,\r
+           pcb->r1,\r
+           pcb->r2,\r
+           pcb->r3,\r
+           pcb->r4,\r
+           pcb->r5,\r
+           pcb->r6,\r
+           pcb->r7,\r
+           pcb->r8,\r
+           pcb->r9,\r
+           pcb->r10,\r
+           pcb->r11,\r
+           pcb->r12,\r
+           pcb->r13,\r
+           pcb->r14,\r
+           pcb->r15,\r
+           pcb->pc,\r
+           pcb->lr,\r
+           pcb->sr\r
        );\r
 \r
        printf("Exception info (IC0):\n");\r
 \r
        printf(\r
-               "   src0: 0x%08x src1: 0x%08x vaddr: 0x%08x\n"\r
-               "      C: 0x%08x    S: 0x%08x\n",\r
-               IC0_SRC0,\r
-               IC0_SRC1,\r
-               IC0_VADDR,\r
-               IC0_C,\r
-               IC0_S\r
+           "   src0: 0x%08x src1: 0x%08x vaddr: 0x%08x\n"\r
+           "      C: 0x%08x    S: 0x%08x\n",\r
+           IC0_SRC0,\r
+           IC0_SRC1,\r
+           IC0_VADDR,\r
+           IC0_C,\r
+           IC0_S\r
        );\r
 \r
        printf("Exception info (IC1):\n");\r
 \r
        printf(\r
-               "   src0: 0x%08x src1: 0x%08x vaddr: 0x%08x\n"\r
-               "      C: 0x%08x    S: 0x%08x\n",\r
-               IC1_SRC0,\r
-               IC1_SRC1,\r
-               IC1_VADDR,\r
-               IC1_C,\r
-               IC1_S\r
+           "   src0: 0x%08x src1: 0x%08x vaddr: 0x%08x\n"\r
+           "      C: 0x%08x    S: 0x%08x\n",\r
+           IC1_SRC0,\r
+           IC1_SRC1,\r
+           IC1_VADDR,\r
+           IC1_C,\r
+           IC1_S\r
        );\r
 }\r
 \r
@@ -95,7 +95,7 @@ void sleh_fatal(vc4_saved_state_t* pcb, uint32_t n) {
        print_vpu_state(pcb);\r
 \r
        printf("We are hanging here ...\n");\r
-       \r
+\r
        hang_cpu();\r
 }\r
 \r
@@ -109,8 +109,7 @@ void sleh_irq(vc4_saved_state_t* pcb, uint32_t tp) {
 \r
        if (source == INTERRUPT_ARM) {\r
                arm_monitor_interrupt();\r
-       }\r
-       else {\r
+       } else {\r
                print_vpu_state(pcb);\r
                panic("unknown interrupt source!");\r
        }\r
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