shader: MESA_SHADER_FRAGMENT
source_sha1: {0x22ca7d74, 0x23cf8986, 0x82a7d2d6, 0x65557b44, 0x520714be}
name: GLSL1
label: shaders/glmark/1-18.shader_test
stage: 4
next_stage: 4
inputs_read: 32
outputs_written: 4
subgroup_size: 1
bit_sizes_float: 0x30
first_ubo_is_default_ubo: true
flrp_lowered: true
color0_interp: 0
color1_interp: 0
inputs: 1
outputs: 1
uniforms: 0
decl_var shader_in INTERP_MODE_NONE mediump vec4 dist (VARYING_SLOT_VAR0.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE mediump vec4 gl_FragData[0] (FRAG_RESULT_DATA0.xyzw, 0, 0)
decl_function main (0 params)

impl main {
	block block_0:
	/* preds: */
	vec2 32 ssa_4 = intrinsic load_barycentric_pixel () (interp_mode=0)
	vec1 32 ssa_3 = load_const (0x00000000 = 0.000000)
	vec4 16 ssa_5 = intrinsic load_interpolated_input (ssa_4, ssa_3) (base=0, component=0, dest_type=float16 /*144*/, io location=32 slots=1 mediump /*8388768*/)	/* dist */
	vec2 16 ssa_24 = fmul ssa_5.xy, ssa_5.ww
	vec1 16 ssa_8 = fmul ssa_5.z, ssa_5.w
	vec1 16 ssa_9 = fmin ssa_24.y, ssa_8
	vec1 16 ssa_10 = fmin ssa_24.x, ssa_9
	vec1 16 ssa_2 = load_const (0xc000 = -2.000000)
	vec1 16 ssa_11 = fmul ssa_2, ssa_10
	vec1 16 ssa_12 = fmul ssa_11, ssa_10
	vec1 32 ssa_13 = f2f32 ssa_12
	vec1 32 ssa_14 = fexp2 ssa_13
	vec1 16 ssa_15 = f2f16 ssa_14
	vec1 16 ssa_32 = load_const (0x3a66 = 0.799805)
	vec1 16 ssa_31 = load_const (0x3800 = 0.500000)
	vec2 16 ssa_33 = vec2 ssa_31, ssa_32
	vec1 16 ssa_28 = load_const (0x3800 = 0.500000)
	vec1 16 ssa_29 = load_const (0x3268 = 0.200195)
	vec2 16 ssa_30 = vec2 ssa_28, ssa_29
	vec2 16 ssa_27 = ffma ssa_15.xx, ssa_30, ssa_33
	vec4 16 ssa_21 = vec4 ssa_15, ssa_27.x, ssa_27.y, ssa_27.y
	intrinsic store_output (ssa_21, ssa_3) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float16 /*144*/, io location=4 slots=1 mediump /*8388740*/, xfb() /*0*/, xfb2() /*0*/)	/* gl_FragData[0] */
	/* succs: block_1 */
	block block_1:
}

block0 {
   43 = MOV.i32 r60
   34 = MOV.i32 r61
   5 = LD_VAR_BUF_IMM.f16.v4.store.f16.f32.center 34, index:0
   35, 36 = SPLIT.i32 5
   24 = FMA.v2f16 35, 36.h11, u256.neg
   8 = FMA.v2f16 36.h00, 36.h11, u256.neg
   9 = FMIN.v2f16.nan_suppress 24.h11, 8.h00
   10 = FMIN.v2f16.nan_suppress 24.h00, 9.h00
   11 = FMA.v2f16 u270.neg.h11, 10.h00, u256.neg
   12 = FMA.v2f16 11.h00, 10.h00, u256.neg
   13 = F16_TO_F32 12.h00
   46 = IADD_IMM.i32 u256, index:24
   37 = FMA_RSCALE.f32 13, u264, u256.neg, 46
   38 = F32_TO_S32 37
   14 = FEXP.f32 38, 37
   15 = V2F32_TO_V2F16 14, 14
   47 = IADD_IMM.i32 u256, index:845690880
   48 = IADD_IMM.i32 u256, index:979777536
   27 = FMA.v2f16 15.h00, 47, 48
   41 = MKVEC.v2i16 15.h00, 27.h00
   42 = IADD.v2u16 27.h11, u256
   21 = COLLECT.i32 41, 42 
   44 = ATEST 43, 42.h11, atest-param
   45 = BLEND.f16 21, 44, blend_descriptor_0, blend_descriptor_0[1], _.h00, sr_count:2, sr_count_2:2
}

block0 {
   r0 = LD_VAR_BUF_IMM.f16.v4.store.f16.f32.center r61, index:0
   r0 = FMA.v2f16 r0, r1.h11, u256.neg
   r1 = FMA.v2f16 r1.h00, r1.h11, u256.neg
   r1 = FMIN.v2f16.nan_suppress r0.h11, r1.h00
   r0 = FMIN.v2f16.nan_suppress r0.h00, r1.h00
   r1 = FMA.v2f16 u270.neg.h11, r0.h00, u256.neg
   r0 = FMA.v2f16 r1.h00, r0.h00, u256.neg
   r0 = F16_TO_F32 r0.h00
   r1 = IADD_IMM.i32 u256, index:24
   r0 = FMA_RSCALE.f32 r0, u264, u256.neg, r1
   r1 = F32_TO_S32 r0
   r0 = FEXP.f32 r1, r0
   r0 = V2F32_TO_V2F16 r0, r0
   r1 = IADD_IMM.i32 u256, index:845690880
   r2 = IADD_IMM.i32 u256, index:979777536
   r1 = FMA.v2f16 r0.h00, r1, r2
   r0 = MKVEC.v2i16 r0.h00, r1.h00
   r1 = IADD.v2u16 r1.h11, u256
   r60 = ATEST r60, r1.h11, atest-param
   r48 = BLEND.f16 r0, r60, blend_descriptor_0, blend_descriptor_0[1], _.h00, sr_count:2, sr_count_2:2
}

block0 {
   r0 = LD_VAR_BUF_IMM.f16.flow1.v4.store.f16.f32.center ^r61, index:0
   r0 = FMA.v2f16.flow13 ^r0, r1.h11, u256.neg
   r1 = FMA.v2f16 ^r1.h00, ^r1.h11, u256.neg
   r1 = FMIN.v2f16.nan_suppress r0.h11, ^r1.h00
   r0 = FMIN.v2f16.nan_suppress ^r0.h00, ^r1.h00
   r1 = FMA.v2f16 u270.neg.h11, r0.h00, u256.neg
   r0 = FMA.v2f16 ^r1.h00, ^r0.h00, u256.neg
   r0 = F16_TO_F32 ^r0.h00
   r1 = IADD_IMM.i32 u256, index:24
   r0 = FMA_RSCALE.f32 ^r0, u264, u256.neg, ^r1
   r1 = F32_TO_S32 r0
   r0 = FEXP.f32 ^r1, ^r0
   r0 = V2F32_TO_V2F16 ^r0, ^r0
   r1 = IADD_IMM.i32 u256, index:845690880
   r2 = IADD_IMM.i32 u256, index:979777536
   r1 = FMA.v2f16 r0.h00, ^r1, ^r2
   r0 = MKVEC.v2i16 ^r0.h00, r1.h00
   r1 = IADD.v2u16.flow8 ^r1.h11, u256
   r60 = ATEST.flow9 ^r60, r1.h11, atest-param
   r48 = BLEND.flow15.f16 r0, ^r60, blend_descriptor_0, blend_descriptor_0[1], _.h00, sr_count:2, sr_count_2:2
}

   LD_VAR_BUF_IMM.f16.slot0.v4.src_f32.center.store.wait0 @r0:r1, ^r61, index:0x0
   FMA.v2f16.discard r0, ^r0, r1.h11, 0x0.neg
   FMA.v2f16 r1, ^r1.h00, ^r1.h11, 0x0.neg
   FMIN.v2f16 r1, r0.h11, ^r1.h00
   FMIN.v2f16 r0, ^r0.h00, ^r1.h00
   FMA.v2f16 r1, 0x40000000.neg.h11, r0.h00, 0x0.neg
   FMA.v2f16 r0, ^r1.h00, ^r0.h00, 0x0.neg
   F16_TO_F32 r0, ^r0.h0
   IADD_IMM.i32 r1, 0x0, #0x18
   FMA_RSCALE.f32 r0, ^r0, 0x3F800000, 0x0.neg, ^r1
   F32_TO_S32 r1, r0
   FEXP.f32 r0, ^r1, ^r0
   V2F32_TO_V2F16 r0, ^r0, ^r0
   IADD_IMM.i32 r1, 0x0, #0x32683800
   IADD_IMM.i32 r2, 0x0, #0x3A663800
   FMA.v2f16 r1, r0.h00, ^r1, ^r2
   MKVEC.v2i16 r0, ^r0.h00, r1.h00
   IADD.v2u16.wait0126 r1, ^r1.h11, 0x0
   ATEST.wait @r60, ^r60, r1.h1, atest_datum.w0
   BLEND.slot1.v4.f16.end @r0:r1, blend_descriptor_0.w0, r60, target:0x0
   IADD_IMM.i32 r48, 0x0, #0x0
   BRANCHZI.eq.absolute 0x0, blend_descriptor_0.w1